HR1001L Enhanced LLC Controller with Adaptive Dead-Time Control

HR1001L Enhanced LLC Conroller wih Adapive Dead-Time Conrol DESCRIPTIO The HR1001L is an enhanced LLC conroller ha provides new, adapive, dead-ime adjusmen (ADTA) and capaciive mode proecion (CMP) feaures. The HR1001L is he OCP lach-off version of he HR1001B. ADTA insers a dead ime beween he wo complimenary gae oupus auomaically by keeping he oupus off while sensing he dv/d curren of he half-bridge swiching node. ADTA feaures an easier design, lower EMI, and higher efficiency. The HR1001L incorporaes ani-capaciive mode proecion, which prevens poenially desrucive capaciive mode swiching if he oupu is shored or has a severe overload. This feaure proecs he MOSFET during abnormal condiions, making he converer robus. The HR1001L has a programmable oscillaor ha ses boh he maximum and minimum swiching frequencies. I sars up a a programmed maximum swiching frequency and decays unil he conrol loop akes over o preven excessive inrush curren. The HR1001L eners conrolled burs mode a ligh loads o minimize he power consumpion and ighen oupu regulaion. Full proecion feaures include wo-level overcurren proecion (OCP), exernal-lach shudown, brown-in/brown-ou, capaciive mode proecion (CMP), and over-emperaure proecion (OTP). FEATURES Two-Level Over-Curren Proecion (OCP): Frequency Shif and Lach-Off Mode Adapive Dead-Time Adjusmen (ADTA) Capaciive Mode Proecion (CMP) 50% Duy Cycle, Variable Frequency Conrol for Resonan Half-Bridge Converer 600V High-Side Gae Driver wih Inegraed Boosrap Diode wih a High-Accuracy Oscillaor of High dv/d Immuniy Operaes up o 600kHz Lached o Disable Inpu for Easy Proecion Remoe On/Off Conrol and Brown-Ou Proecion hrough BO Programmable Burs Mode Operaion a Ligh Load on-linear Sof Sar for Monoonic Oupu Volage Rise Available in a SOIC-16 Package APPLICATIOS LCD and PDP TVs Deskop PCs and Servers Telecom SMPS AC/DC Adaper, Open-Frame SMPS Video Game Consoles Elecronic Lighing Ballas All MPS pars are lead-free, halogen-free, and adhere o he RoS direcive. For MPS green saus, please visi he MPS websie under Qualiy Assurance. MPS and The Fuure of Analog IC Technology are regisered rademarks of Monolihic Power Sysems, Inc. HR1001L Rev.1.0 www.monolihicpower.com 1

HR1001L EHACED LLC COTROLLER TPICAL APPLICATIO PRELIMIAR SPECIFICATIOS SUBJECT TO CHAGE BO V DC Css Rss CT Rfmax Rfmin SS TIMER CT FSET BURST CS BO LATCH 1 2 3 4 5 6 7 8 16 15 14 13 HR1001L 12 11 10 9 BST SW C VCC LG GD HBVS C BST C HBVS S1 S2 Cr VCC Lr Lm D1 D2 Oupu Cf Rf Rs Cs TL431 HR1001L Rev.1.0 www.monolihicpower.com 2

ORDERIG IFORMATIO HR1001L EHACED LLC COTROLLER Par umber* Package Top Marking HR1001LGS SOIC-16 See Below * For Tape & Reel, add suffix Z (e.g. HR1001LGS Z) TOP MARKIG MPS: MPS prefix : ear code WW: Week code HR1001L: Par number LLLLLLLLL: Lo number PACKAGE REFERECE TOP VIEW SS TIMER CT 1 2 3 16 15 14 FSET 4 13 HR1001L BURST 5 12 CS BO LATCH 6 7 8 11 10 9 BST SW C VCC LG GD HBVS SOIC-16 HR1001L Rev.1.0 www.monolihicpower.com 3

HR1001L EHACED LLC COTROLLER ABSOLUTE MAXIMUM RATIGS (1) BST volage........ -0.3V o 618V SW volage...... -3V o 600V Max volage slew rae of SW..... 50V/ns Supply volage (VCC)..... Self-limied Sink curren of HBVS..... ±65mA Volage on HBVS....... -0.3V o self-limi Source curren of FSET..... 2mA Volage raing of LG.... -0.3V o V CC Volage on CS........ -3V o 6V Oher analog inpus and oupus... -0.3V o 6V Coninuous power dissipaion (T A = +25 C) (2) P IC.... 1.56W Juncion emperaure.... 150 C Lead emperaure....260 C Sorage emperaure..... -65 C o +150 C ESD immuniy...bst,, SW passes HBM 2.5kV, oher pins can pass HBM 4kV. Recommended Operaing Condiions (3) Supply volage (VCC)..... 13V o 15.5V Analog inpus and oupus... -0.3V o 6V Operaing juncion emp (T J )....-40 C o +125 C Thermal Resisance (4) θ JA θ JC SOIC-16...80...35 C/W OTES: 1) Exceeding hese raings may damage he device. 2) The maximum allowable power dissipaion is a funcion of he maximum juncion emperaure T J (MAX), he juncion-oambien hermal resisance θ JA, and he ambien emperaure T A. The maximum allowable coninuous power dissipaion a any ambien emperaure is calculaed by P D (MAX) = (T J (MAX)-T A)/θ JA. Exceeding he maximum allowable power dissipaion produces an excessive die emperaure, causing he regulaor o go ino hermal shudown. Inernal hermal shudown circuiry proecs he device from permanen damage. 3) The device is no guaraneed o funcion ouside of is operaing condiions. 4) Measured on a JESD51-7, 4-layer PCB. HR1001L Rev.1.0 www.monolihicpower.com 4

HR1001L EHACED LLC COTROLLER ELECTRICAL CHARACTERISTICS VCC = 13V, C = C LG = 1nF, CT = 470pF, R FSET = 12kΩ, T J = -40 C~125 C, min and max values are guaraneed by characerizaion, ypical values are esed under 25 C, unless oherwise specified. Parameer Symbol Condiion Min Typ Max Unis IC Supply Volage (VCC) VCC operaing range 8.9 15.5 V VCC high hreshold, IC swich on V CCH 10.3 11 11.7 V VCC low hreshold, IC swich off V CCL 7.5 8.2 8.9 V Hyseresis V CC-hys 2.8 V VCC clamp volage V CC-Clamp I Clamp = 1mA 16.5 V IC Supply Curren (VCC) Sar-up curren Quiescen curren I sar-up I Q I Q-f Before he device urns on, VCC = VCC H - 0.2V Device on, V Burs < 1.23V, R FSET =12k, F MI = 60kHz Device on, V Burs < 1.23V, R FSET = 3.57k, F BURST = 200kHz 250 320 μa 1.2 1.5 ma 1.42 1.8 ma Operaing curren I CC-nor Device on V Burs = V FSET 3 5 ma Residual consumpion I Faul High-Side Floaing Gae Driver Supply (BST, SW) VCC < 8.2V or V LATCH > 1.85V or V CS > 1.5V or V TIMER > 3.5V or V BO < 1.81V or V BO > 5.5V or OTP 240 350 420 μa BST leakage curren I LK-BST V BST = 600V, T J = 25 C 12 µa SW leakage curren I LK-SW V SW = 582V, T J = 25 C 12 µa Curren Sensing (CS) Inpu bias curren I CS V CS = 0 o V CSlach 2 µa Frequency shif hreshold V CS-OCR 0.71 0.78 0.85 V OCP hreshold V CS-OCP 1.41 1.5 1.59 V Curren polariy comparaor reference when urns off Curren polariy comparaor reference when LG urns off Line Volage Sensing (BO) V CSPR 50 85 131 mv V CSR -131-85 -50 mv Sar-up hreshold volage V BO-On 2.30 2.4 V Turn-off hreshold volage V BO-Off 1.72 1.81 V Clamp level V BO-Clamp 5.1 5.5 5.9 V Lach Funcion (LATCH) Inpu bias curren (V LATCH = 0 o V h ) I LATCH 1 µa LATCH hreshold V LATCH 1.72 1.85 1.95 V HR1001L Rev.1.0 www.monolihicpower.com 5

HR1001L EHACED LLC COTROLLER ELECTRICAL CHARACTERISTICS (coninued) VCC = 13V, C = C LG = 1nF, CT = 470pF, R FSET = 12kΩ, T J = -40 C~125 C, min and max values are guaraneed by characerizaion, ypical values are esed under 25 C, unless oherwise specified. Parameer Symbol Condiion Min Typ Max Unis Oscillaor Oupu duy cycle D T J = 25 C 48 50 52 % T J = -40~125 C 47 50 53 % Oscillaion frequency f osc CT 150pF, R FSET 2k 600 khz CT peak value V CFp 3.8 V CT valley value V CFv 0.9 V Volage reference a FSET V REF 1.87 2 2.05 V Dead ime DT MI C HBVS = 5pF, ypically 180 235 290 ns DT MAX 1 µs DT -floa HBVS floaing 250 350 450 ns Timer for CMP CMP 52 µs Half-Bridge Volage Sense (HBVS) Volage clamp Minimum volage change rae ha can be deeced V HBVS- Clamp 7.6 V dv min /d C HBVS = 5pF, ypically 180 V/µs Turn-on delay T d Slope finish o urn-on delay 100 ns Sof-Sar Funcion (SS) Discharge resisance R d V CS > V CS-OCR 130 Ω Sandby Funcion (BURST) Disable hreshold V Burs 1.17 1.23 1.28 V Hyseresis V Burs-hys 30 100 mv Delayed Shudown (TIMER) Charge curren Threshold for forced operaion a maximum frequency I TIMER V TIMERfmax V TIMER = 1V, V CS = 0.85V, T J = 25 C 80 130 180 µa 1.80 2 2.10 V Shudown hreshold V TIMER-SD 3.2 3.5 3.7 V Resar hreshold V TIMER-R 0.21 0.28 0.35 V Low-Side Gae Driver (LG, Referenced o GD) Peak source curren (5) I sourcepk 0.75 A Peak sink curren (5) I sinkpk 0.87 A Sourcing resisor R source Isrc = 0.1A 4 Ω Sinking resisor R sink Isnk = 0.1A 2 Ω Fall ime f 30 ns Rise ime LG-r 30 ns UVLO sauraion VCC = 0 o V CCH, I sink = 2mA 1 V HR1001L Rev.1.0 www.monolihicpower.com 6

HR1001L EHACED LLC COTROLLER TPICAL PERFORMACE CHARACTERISTICS Performance waveforms are generaed using he evaluaion board buil wih he design example on page 22, V AC = 120V, V OUT = 24V, I OUT = 4.16A, T A = 25 C, unless oherwise noed. HR1001L Rev.1.0 www.monolihicpower.com 8

HR1001L EHACED LLC COTROLLER TPICAL PERFORMACE CHARACTERISTICS (coninued) Performance waveforms are generaed using he evaluaion board buil wih he design example on page 22, V AC = 120V, V OUT = 24V, I OUT = 4.16A, T A = 25 C, unless oherwise noed. HR1001L Rev.1.0 www.monolihicpower.com 9

PI FUCTIOS HR1001L EHACED LLC COTROLLER Pin # ame Descripion 1 SS Sof sar. Connec an exernal capacior from SS o GD and a resisor o FSET o se he maximum oscillaor frequency and he ime consan for he frequency shif during sar-up. An inernal swich discharges he capacior when he chip urns off (VCC < UVLO, BO < 1.81V or > 5.5V, LATCH > 1.85V, CS > 1.5V, TIMER > 2V, hermal shudown) o guaranee a sof sar. Period beween over-curren and shudown. Connec a capacior and a resisor from TIMER o GD o se he maximum duraion from an over-curren condiion before he IC sops swiching. Whenever he volage on CS exceeds 0.78V, an inernal 130µA curren source charges he capacior. An exernal resisor discharges his capacior slowly. If he 2 TIMER volage on TIMER reaches 2V, he sof-sar capacior discharges compleely, raising is swiching frequency o is maximum value. The 130µA curren source remains on. When he volage exceeds 3.5V, he IC sops swiching and laches. The inernal curren source urns off, and he volage decays. Two evens are required for he IC o resume sof sar: 1) he volage on TIMER mus drop below 0.28V; 2) VCC mus drop below he UVLO hreshold and rise up o he VCC high hreshold. Time se. An inernal curren source programmed by an exernal nework conneced o 3 CT FSET charges and discharges a capacior conneced o GD. This deermines he converer s swiching frequency. Swiching frequency se. FSET provides a precise 2V reference. A resisor conneced from FSET o GD defines a curren ha ses he minimum oscillaor frequency. Connec 4 FSET he phooransisor of an opocoupler o FSET hrough a resisor o close he feedback loop ha modulaes he oscillaor frequency. This regulaes he converer s oupu volage. The value of his resisor ses he maximum operaing frequency. An R-C series conneced from FSET o GD ses he frequency shif a sar-up o preven excessive inrush energy. Burs mode operaion hreshold. BURST senses he volage relaed o he feedback conrol, which is compared o an inernal reference (1.23V). When he volage on BURST is lower han his reference, he IC eners an idle sae and reduces is quiescen curren. 5 BURST When he feedback drives BURST above 1.26V (30mV hyseresis), he chip resumes swiching. There is no sof sar. The burs funcion enables burs mode operaion when he load falls below a programmed level ha is deermined by connecing an appropriae resisor o he opocoupler o FSET (see he Block Diagram on page 12). Connec BURST o FSET if burs mode is no used. Curren sense of he half-bridge. CS uses a sense resisor or a capaciive divider o sense he primary-side curren. CS has he following funcions: Over-curren regulaion: If he sensed volage exceeds he 0.78V hreshold, he sofsar capacior on SS discharges inernally. The frequency increases, limiing he power hroughou. Under an oupu shor circui, his normally resuls in a nearconsan peak primary curren. TIMER limis he duraion of his condiion. Over-curren proecion (OCP): If he primary-side curren coninues o rise despie he 6 CS frequency increase, OCP eners lach mode when V CS > 1.5V. This requires cycling he IC supply volage o resar. The lach is removed once he volage on VCC drops below he UVLO hreshold. Capaciive mode proecion (CMP): Once LG urns off, CS is compared o he V CSR capaciive mode proecion (CMP) hreshold. If V CS > V CSR, he gae is blocked from urning on unil he slope is deeced or he CMP imer is complee. When urns off, CS is compared o he V CSPR CMP hreshold. If Vcs < V CSPR, he low-side gae is blocked from urning on unil he slope is deeced or he CMP imer is complee. If a capaciive mode saus is deeced, SS is no discharged immediaely; here is a 1µs delay. Afer he blanking ime delay, SS is discharged if he capaciive mode faul remains. This prevens he influence of CS noise effecively. Connec CS o GD if he CMP funcion is no used. HR1001L Rev.1.0 www.monolihicpower.com 10

PI FUCTIOS (coninued) HR1001L EHACED LLC COTROLLER Pin # ame Descripion 7 BO Inpu volage sense and brown-in/brown-ou proecion. If he volage on BO is over 2.3V, he IC enables he gae driver. If he volage on BO is below 1.81V, he IC is disabled. IC lach off. When he volage on LATCH exceeds 1.85V, he IC shus down and lowers is 8 LATCH bias curren o is pre-sar-up level. LATCH is rese when he volage on VCC is discharged below is UVLO hreshold. Connec LATCH o GD if he funcion is no used. 9 HBVS Half-bridge dv/d sense. To deec he dv/d of he half-bridge, a high-volage capacior is conneced beween SW and HBVS. The dv/d curren hrough HVBS is used o adjus he dead-ime adapively beween he high-side gae and he low-side gae. 10 GD Ground. GD is he curren reurn for boh he low-side gae driver and he IC bias. Connec all exernal ground connecions wih a race o GD, one for signals and a second for pulsed curren reurn. 11 LG Low-side gae driver oupu. The driver is capable of a 0.8A of source/sink peak curren o drive he lower MOSFET of he half-bridge. LG is pulled o GD during UVLO. 12 VCC Supply volage. VCC supplies boh he IC bias and he low-side gae driver. Use a small bypass capacior (e.g.: 0.1µF) o ge a clean bias volage for he IC signal. 13 C High-volage spacer. o inernal connecion. C isolaes he high-volage pin and eases compliance wih safey regulaions (creepage disance) on he PCB. 14 SW High-side swich source. SW is he curren reurn for he high-side gae drive curren. SW requires careful layou o preven large spikes below ground. High-side floaing gae driver oupu. is capable of a 0.8A source/sink peak curren 15 o drive he upper MOSFET of he half-bridge. Connec an inernal resisor o SW o ensure ha does no floa during UVLO. 16 BST Bias for floaing volage supply of he high-side gae driver. Connec a boosrap capacior beween BST and SW. This capacior is charged by an inernal boosrap diode driven in phase wih he low-side gae driver. HR1001L Rev.1.0 www.monolihicpower.com 11

HR1001L EHACED LLC COTROLLER BLOCK DIAGRAM VCC BST Vbus Inernal Circui Level Shifer HSG Driver CBOOT SW Lr BURST 1.26V/ 1.23V 2V Sandby Ifmin OTP Dmin/ Dada/ DTmax Driving Logic ADTA VDD LSG Driver LG GD HBVS Resonan Tank Curren Cr FSET Slope Deeced/ 52µs Timer Ou CMP Righ Wrong Curren Polariy SS Conrol Logic OCP 1.5V CS OCR 0.78V LATCH CT VCLK Boos _OK Q Disable 2.3V/1.81V S R UVLO 1.85V TIMER BO Figure 1: Funcional Block Diagram HR1001L Rev.1.0 www.monolihicpower.com 12

HR1001L EHACED LLC COTROLLER APPLICATIO IFORMATIO Oscillaor Figure 2 shows he oscillaor block diagram. A modulaed curren charges and discharges he CT capacior repeaedly beween is peak valley hresholds, which deermines he oscillaor frequency. Rf min R ss C ss Rf max FSET GD CT 0.9V 3.8 V I se + - + - 2V R S Q HR1001L I s-1 I se I s-2 2I se Figure 2: Oscillaor Block Diagram FSET ses he CT charging curren, I SET (I S-1 ). When CT passes is peak hreshold (3.8V), he filp-flop is se, and a discharging curren source of wice he charge curren is enabled. The difference beween hese wo currens forces he charging and discharging of CT o be equal. When he volage on he CT capacior falls below is valley hreshold (0.9 V), he flip-flop is rese and urns off he discharging curren source. This sars a new swiching cycle. Figure 3 shows he deailed waveform of he oscillaor. CT LG SW TD Figure 3: CT Waveform and Gae Signal CT An R-C nework conneced o FSET exernally deermines he normal swiching frequency and he sof sar swiching frequency. Rf min from FSET o GD conribues o he maximum resisance of he exernal R-C nework when he phooransisor does no conduc. This ses he FSET minimum source curren, which defines he minimum swiching frequency. Under normal operaion, he phooransisor adjuss he curren flow hrough Rf max o modulae he frequency for oupu volage regulaion. When he phooransisor is sauraed, he curren hrough Rf max is a is maximum, which ses he frequency a is maximum. An R-C in series conneced beween FSET and GD shifs he frequency a sar-up. Please see he Sof-Sar Operaion secion on page 14 for deails. Se he minimum and maximum frequencies wih Equaion (1) and Equaion (2): 1 fmin (1) 3 CT Rf f max min min 1 (2) 3 CT (Rf Rf ) Typically, he CT capaciance is beween 0.1nF and 1nF. Calculae Rf min and Rf max wih Equaion (3) and Equaion (4) : 1 Rfmin (3) 3 CT f Rf max min min Rfmin fmax 1 f max (4) I is recommended o use a CT capacior less han or equal o 330pF for bes overall emperaure performance. HR1001L Rev.1.0 www.monolihicpower.com 13

HR1001L EHACED LLC COTROLLER Sof-Sar (SS) Operaion For he resonan half-bridge converer, he power delivered is inversely proporional o is swiching frequency. To ensure ha he converer sars or resars wih safe currens, he sof sar forces a high iniial swiching frequency unil he value is conrolled by he closed loop. The sof sar is achieved using an exernal R-C series circui (see Figure 4). Rf min R SS C SS FSET SS 4 HR1001L Figure 4: Sof-Sar Block When he IC sars up, he SS volage is 0V, and he sof-sar resisor (R SS ) is in parallel o Rf min. Rf min and R SS deermine he iniial frequency, which can be calculaed wih Equaion (5): f sar min 1 1 (5) 3 CT (Rf R ) During sar-up, C SS charges unil is volage reaches he reference (2V) and he curren hrough R SS decays o zero. This period akes abou 5x(R SS xc SS ) microseconds. During his period, he swiching frequency change follows an exponenial curve. Iniially, he C SS charge reduces he frequency relaively quickly, bu he rae decreases gradually. Afer he sof-sar period, he swiching frequency is dominaed by he feedback loop o regulae he oupu volage. Wih he sof sar, he curren of he resonan ank increases gradually during sar-up. Selec he sof-sar R-C nework wih Equaion (6) and Equaion (7) : R ss Rf fsar f min min 1 ss (6) Selec an iniial frequency (f sar ) a leas four imes f min. When selecing C SS, here is a radeoff beween he desired sof-sar operaion and he over-curren proecion (OCP) speed. See he Over-Curren Proecion secion on page 17 for deails. Adapive Dead-Time Adjusmen (ADTA) When operaing in inducive mode, he sof swiching of he power MOSFETs resuls in high efficiency of he resonan converer. A fixed dead ime may resul in hard swiching a ligh load, especially when he magneizing inducance (Lm) is oo large. A dead ime ha is oo long may lead o loss of he ZVS sae. The curren may change polariy during he dead ime, which can resul in capaciive mode swiching. The adapive dead-ime conrol adjuss he dead ime auomaically by deecing he dv/d of he half-bridge swiching node (SW). The HR1001L incorporaes an inelligen adapive dead-ime adjusmen (ADTA) logic circui, which deecs he dv/d of SW and insers a proper dead ime auomaically. For he exernal circui, connec a capacior (5pF, ypically) beween SW and HBVS o sense dv/d. Figure 5 shows he simplified block diagram of ADTA. Figure 6 shows he operaion waveform of ADTA. LG ADTA Logic LG CLK CLK VDD HSG Driver LSG Driver BST SW LG GD HBVS Figure 5: Block Diagram of ADTA D1 Vbus CBOOT Lr CHBVS id Cr C ss -3 3 10 (7) R ss HR1001L Rev.1.0 www.monolihicpower.com 14

HR1001L EHACED LLC COTROLLER i r V SW V HBVS Dead ime adapively adjused i m Curren of CHBVS CLK i d LG TDmin Figure 6: Operaion Waveform of ADTA When swiches off, he SW volage swings from high o low due o he resonan ank curren (Ir). Accordingly, his negaive dv/d pulls curren from HBVS via C HBVS. If he dv/d curren is higher han he inernal comparison curren, he HBVS volage (V HBVS ) is pulled down and clamped a zero. When SW sops slewing and he differenial curren sops, V HBVS begins ramping up. LG urns on afer a delay (minimum dead ime). Dead ime is defined as he duraion beween urning off and LG urning on. When LG swiches off, he SW volage swings from low o high, and a posiive dv/d curren is deeced via C HBVS. The dead ime beween LG urning off and urning on is mainained auomaically by sensing he dv/d curren. To avoid damaging HBVS, CHBVS should be seleced wih careful consideraion. Keep he dv/d curren below 65mA using Equaion (8): dv id CHBVS 65mA (8) d If C HBVS is oo low o sense he dv/d, he minimum volage change rae (dv min /d) mus be accouned for o design he proper C HBVS. Firs, calculae he peak magneizing curren (Im) wih Equaion (9): I V in m (9) 8 Lm fmax Design C HBVS using Equaion (10): 700μA C C oss HBVS I 2 (10) Where C oss is he oupu capaciance when he drain-source volage on he MOSFET is near zero vols (refer o he C oss characerisics curve in he MOSFET s daashee). In a ypical design, Lm = 870µH, V I = 450Vdc, and f max = 140kHz, and C HBVS is calculaed a 4.5pF. 5pF is suiable for mos MOSFETs. Figure 7 illusraes a possible dead ime by ADTA logic. oe ha here are hree kinds of dead ime: minimum dead ime (DT MI ), maximum dead ime (DT MAX ), and adjused dead ime (DT ADJ ), which is beween DT MI and DT MAX. ADTA logic ses DT MI = 235ns. When he SW ransiion ime is smaller han DT MI, he logic does no le he gae urn on, which prevens a shoo-hrough beween he low-side and high-side MOSFETs. A maximum dead ime (DT MAX = 1µs) forces he gae o urn on, prevening duy cycle losses or sof swiching. ADTA adjuss he dead ime auomaically and ensures zero-volage swiching (ZVS), which enables more flexibiliy in he MOSFET and Lm selecion. ADTA also prevens hard swiching if he design does no accoun for ligh load or no load carefully. A ligh load, he swiching frequency goes high, and he magneizing curren goes low, risking hard swiching ha can lead o a hermal or reliabiliy issue. V osc V CLK V gae V SW V DT m DT min DT min DT max LG LG 1 2 3 4 5 6 7 8 Figure 7: Dead Time in ADTA HR1001L Rev.1.0 www.monolihicpower.com 15

HR1001L EHACED LLC COTROLLER If HBVS is no conneced, he inernal circui canno deec he differenial curren from HBVS, so he dead ime remains fixed a 350ns. Figure 8 and Figure 9 show he waveforms of he dead ime when urns off and when LG urns off respecively. ADTA logic insers he dead ime auomaically according o he ransiion shape of SW. If HBVS is pulled down oo low by he negaive curren of C HBVS, he dead ime from urning off o LG urning on may be oo long. To clamp HBVS a zero and ensure an opimum dead ime, connec a Schoky diode (D1) (such as BAT54) on HBVS o GD. V Figure 8: Dead Time a High-o-Low Transiion V LG V SW V HBVS V SW V HBVS V LG V Figure 9: Dead Time a Low-o-High Transiion Capaciive Mode Proecion (CMP) When he resonan HB converer oupu is in overload or shor circui condiion, i may cause he converer o run ino a capaciive region. In capaciive mode, he volage applied o he resonan ank causes he curren of he resonan ank o lag. Under his condiion, he body diode of one of he MOSFETs is conducing. The oher MOSFET should no be urned on o avoid device failure. The funcional block diagram of capaciive mode proecion (CMP) is shown in Figure 10. Figure 11 shows he operaing curren principle of CMP. CSPOS and CSEG sand for he curren polariy, which is generaed by comparing he volage on CS wih he inernal V CSR and V CSPR volage reference. A 0, LG urns off. CSEG is high, which means he curren is in he correc direcion and is operaing in inducive mode. A 1, urns off. CSPOS is high, which means he curren is in he correc direcion and is operaing in inducive mode. A 2, LG urns off for a second ime. CSEG is low, indicaing ha he curren is in he wrong direcion (he low-side MOSFET body diode is conducing), and he converer is operaing in capaciive mode. SW does no swing high unil he curren reurns o he correc polariy. DT says high and VOSC is sopped, prevening he oher MOSFET from urning on. This prevens capaciive swiching. A 3, he curren reurns o he correc polariy, and he oher MOSFET urns on afer he dv/d curren is deeced. Beween 2 and 5, he correc curren polariy canno be deeced, or here is so lile curren ha SW is unable o be pulled up or down. Evenually, he imer (52µs) for CMP expires, and he oher MOSFET is forced o swich on (see Figure 11). HR1001L Rev.1.0 www.monolihicpower.com 16

CLR CLR HR1001L EHACED LLC COTROLLER FSET SS TIMER Ise 130µA Proecion Timer 2V 2.0 V 3.5 V 0.28 V Discharge: OCR CMP Re-Sar Conrol Logic Capaciive Deeced CMP Lach Off Q Q S R Q Proecion Timer Q SET Q SET Q HR1001L D D UVLO Figure 10: Block Diagram of CMP and OCP V osc V CLK Vgae V SW Vcs CSEG CSPOS Vss DT LG CLK CLK OCP OCR DTmin DTmin Timer ou VDD -85 mv 85 mv 1.5 V 0.78 V DTmax Slope Missing HSG Driver LSG Driver LG LG BST SW LG GD CS 0 1 2 3 4 5 6 Figure 11: Operaing Principle of CMP When capaciive mode operaion is deeced, he V SS conrol signal goes high, urning on an inernal ransisor o discharge C SS (afer a 1µs blanking delay). This causes he frequency o increase o a very high level quickly o limi he oupu power. The V SS conrol is rese, and he sof sar is acivaed when he firs gae driver is swiched off afer CMP. The swiching frequency decreases smoohly unil he conrol loop akes over. V H V L Figure 12: Capaciive Mode Proecion Waveform ir V S Vbus Cr CBOOT Lr Figure 12 shows he CMP behavior when he oupu is shored. The curren polariy goes in he wrong direcion when LG swiches off. The CMP logic deecs his capaciive mode immediaely and prevens from urning on. This prevens desrucive capaciive swiching. Once he curren (Ir) reurns o he correc polariy, SW ramps up, dv/d curren is deeced, and urns on a he ZVS sae. Over-Curren Proecion (OCP) The HR1001L provides wo levels of overcurren proecion (see Figure 13). The firs level of proecion occurs when he volage on CS (V CS ) exceeds 0.78V. Once his occurs, wo acions ake place. Firs, he inernal ransisor conneced beween SS and GD urns on for a leas 10µs, which discharges C SS. This creaes a sharp increase in he oscillaor frequency, reducing he energy ransferred o he oupu. Second, an inernal 130µA curren source urns on o charge C TIMER, ramping up he TIMER volage. If V CS drops below 0.78V before he volage on TIMER (V TIMER ) reaches 2V, boh he discharge of C SS and he charge of C TIMER are sopped. The converer resumes normal operaion. OC is he ime for V TIMER o rise from 0V o 2V. I is a delay ime for over-curren regulaion. There is no simple relaionship beween OC and C TIMER. Selec C TIMER based on experimenal resuls. Based on experimens, C TIMER may increase he operaing ime by 100ms. If V CS is sill larger han 0.78V afer V TIMER rises o 2V, C ss is discharged compleely. Simulaneously, he inernal 130µA curren source coninues o charge C TIMER unil V TIMER reaches 3.5V, hen urns off all gae drivers and eners a lach-off mode. The lach is rese when he volage on VCC is lower han he UVLO hreshold. Use Equaion (11) o calculae he ime i akes for V TIMER o rise from 2V o 3.5V: 4 10 C (11) OP TIMER Even if he lach is rese, he HR1001L will ener sof sar again unil V TIMER decreases o 0.28V. Calculae his ime period wih Equaion (12): =R C ln 3.5 2.5R C 0.28 OFF TIMER TIMER TIMER TIMER (12) HR1001L Rev.1.0 www.monolihicpower.com 17

HR1001L EHACED LLC COTROLLER The second level of proecion is riggered when V CS rises o 1.5V. Typically, his condiion occurs when V CS coninues o rise during a shor circui. The IC sops swiching immediaely and laches off unil he volage on VCC drops below he UVLO hreshold. The ime sequence of OCP is shown in Figure 13. OCP limis he energy ransferred from he primary side o he secondary side during an overload or shor-circui condiion. Excessive power consumpion due o high coninuous currens can damage he secondary-side windings and recifiers. When OCP is riggered, he converer eners a lached-off proecion mode. VCC SS ICr VCS VCCH VCCL VSS VCS-OCP VCS-OCR OC OP STOP SS Calculae R S wih Equaion (14): 0.8 C Rs< (1 r ) I C Crpk S (14) Where I Crpk is he peak curren of he resonan ank a a low inpu volage and full load, and can be calculaed wih Equaion (15): VO IO I Crpk ( ) ( ) 4L f 2 m s 2 2 (15) Where is he urns raio of he ransformer, lo is he oupu curren, Vo is he oupu volage, f S is he swiching frequency, and L m is he magneizing inducance. For capaciive mode deecion in no-load or small-load condiion, R S should fulfill he condiion in Equaion (16): 85mV C (16) r R S (1 ) Im CS TIMER Vou VTIMER-SD VTIMER-fmax VTIMER-R ormal Operaion Over Load Pmin Shudown (Lach) Sof-Sar OCP(Lach-off Mode) Figure 13: OCP Timing Sequence Curren Sensing There are wo curren sensing mehods: lossless curren sensing and curren sensing wih a sense resisor. Generally, a lossless curren sensing soluion is used in high-power applicaions (see Figure 14). Sof-Sar In some condiions, especially when a large L m is used, i is difficul o saisfy boh Equaion (14) and Equaion (16). The IC will operae wihou CMP funcion a ligh load if i is no under he resricion of Equaion (16). The R1 and C1 nework is used o aenuae swiching noise on CS. The ime consan should be in he range of 100ns. An alernae soluion uses a sense resisor in series wih he resonan ank (see Figure 15). This mehod is simple, bu causes unnecessary power loss on he sense resisor. Lr CS C1 R1 Rs Cs Cr CS R1 C1 Cr Rs Figure 14: Curren Sensing wih a Lossless ework Design he lossless curren sensing nework wih Equaion (13): Cs Cr (13) 100 Figure 15: Curren Sensing wih a Sense Resisor Design he sense resisor using Equaion (17): 0.78 R S (17) I Crpk HR1001L Rev.1.0 www.monolihicpower.com 18

HR1001L EHACED LLC COTROLLER Inpu Volage Sensing (BI/BO) The HR1001L sops swiching when he inpu volage drops below a specified value and resars when he inpu volage reurns o normal. This funcion guaranees ha he resonan halfbridge converer always operaes wihin he specified inpu-volage range. The IC senses he volage on BO (V BO ) hrough he ap of a resisor divider conneced o he recified AC volage or he PFC oupu. Figure 16 shows he line-sensing inernal block diagram. R H R L BO 7 2.3 V/ 1.81 V 5.5 V Shudown VinOK HR1001L Figure 16: Inpu Volage Sensing Block If V BO is higher han 2.3V, he IC provides he gae driver oupus. The IC does no sop he gae driver unil V BO drops below 1.81V. For a minimum operaion inpu volage of he half-bridge (V I-min ), selec a value for R H large enough o reduce power loss a no load. Then R L can be calculaed wih Equaion (18): 1.81 RL RH (18) V 1.81 I-min For addiional proecion, he IC shus down when V BO exceeds he inernal 5.5V clamp volage. When V BO is beween 2.3V and 5.5V, he IC operaes normally. Burs Mode Operaion A ligh load or in he absence of a load, he maximum frequency limis he resonan halfbridge swiching frequency. To conrol he oupu volage and limi power consumpion, he HR1001L enables compaible converers o operae in burs mode. This grealy reduces he average swiching frequency, reducing he average residual magneizing curren and he associaed losses. Operaing in burs mode requires seing up BURST. If he volage on BURST (V BURST ) drops below 1.23V, he HR1001L shus down and LG, only leaving he 2V reference volage on FSET and SS o reain he previous sae and minimize power consumpion. When V BURST exceeds 1.23V by over 30mV, he HR1001L resumes normal operaion. Based on he burs mode operaion principle, BURST mus be conneced o he feedback loop. Figure 17 shows a ypical circui connecing BURST o he feedback signal for narrow inpu volage range applicaions. Rfmin Rfmax FSET 4 HR1001L BURST 5 Figure 17: Burs Mode Operaion Se-Up In addiion o seing he oscillaor maximum frequency a sar-up, Rf max deermines he maximum burs mode frequency. Afer deermining f max, calculae Rf max wih Equaion (19): Rf max 3 Rf 8 fmax f min min 1 (19) f max corresponds o a load poin (P Burs ) where he peak curren flow hrough he ransformer is oo low o cause audible noise. The above burs mode inroducion is based on a narrow inpu volage range. The inpu volage deermines he swiching frequency as well. This means ha P Burs has a large variance over he wide inpu volage range. To sabilize P Burs over he inpu range, use he circui in Figure 18 o inser he inpu volage signal ino he feedback loop. Rfmin Rss Css Rfmax RB1 Css FSET BURST RB2 HR1001L Figure 18: Burs Mode Operaion Se-Up for a Wide Inpu Volage Range BO Vin RH RL HR1001L Rev.1.0 www.monolihicpower.com 19

HR1001L EHACED LLC COTROLLER R B1 and R B2 in Figure 18 correc agains he wide inpu volage range. Selec boh resisors based on experimenal resuls. oe ha he oal resisance of R B1 and R B2 should be much larger han R H o minimize he effec on V BO. During burs mode operaion when he load is lower han P Burs, he swiching frequency is clamped a he maximum frequency. The oupu volage mus rise over he seing value o increase he curren flowing hrough he opocoupler. Therefore, he volage on Rf max rises due o he increased phooransisor curren. Then V BURST drops below 1.23V, riggering he gae signal off sae. The curren flows hrough he opocoupler decreases unil he oupu volage falls below he seing value, causing V BURST o rise. When V BURST exceeds 1.23V by over 30mV, he IC resars o generae he gae signal. The IC operaes in his mode under no load or ligh load o decrease he average power consumpion. Lach Operaion The HR1001L provides a simple lach-off funcion hrough LATCH. Applying an exernal volage over 1.85V o HBVS causes he IC o ener a lached shudown. Afer he IC is lached, is consumpion drops. Reseing he IC requires dropping he VCC volage below he UVLO hreshold (see Figure 19). LATCH 9 1.85 V + - HR1001L UVLO S Q Disable R VCC 12 High-Side Driver Level Shifer 16 15 14 HR1001L BST SW Figure 20: High-Side Gae Driver C BST Low-Side Gae Driver (LG) LG provides he gae driver signal for he lowside MOSFET. The maximum volage on LG is 16V. Under cerain applicaions, a large volage spike occurs on LG due o oscillaions from he long-gae driver wire, he MOSFET parasiic capaciance, and he small gae driver resisor. This volage spike is dangerous o LG, so a 15V Zener diode close o LG and GD is recommended (see Figure 21). HR1001L Low-Side Driver Vs 11 LG Rg 15 V 10 GD Cgd Cgs SW Figure 21: Low-Side Gae Driver Cds Figure 19: Lach Funcion Block High-Side Gae Driver () The exernal BST capacior provides energy o he high-side gae driver. An inegraed boosrap diode charges his capacior hrough VCC. This diode simplifies he exernal driving circui for he high-side swich, allowing he BST capacior o charge when he low-side MOSFET is on (see Figure 20). To provide enough gae driver power (considering he BST capacior charge ime), use a 100nF o 470nF capacior for he BST capacior. HR1001L Rev.1.0 www.monolihicpower.com 20

HR1001L EHACED LLC COTROLLER Design Example A 100W LED driver is designed wih he specificaions below (see Table 1). Table 1: Design Example Inpu AC volage 90-305V AC Oupu volage 24V Oupu curren 4.16A Figure 22 shows he deailed applicaion schemaic. The ypical performance and circui waveforms are shown in he Typical Performance Characerisics secion. PFC Sage LLC Sage Figure 22: Design Example for a 24V/4.16A Oupu HR1001L Rev.1.0 www.monolihicpower.com 21

HR1001L EHACED LLC COTROLLER COTROL FLOW CHART START VCC capacior is charged by exernal circui VCC>11 V & BO>2.3 V? Sof Sar Slope deeced? ADTA Fixed DT=350ns CMP ormal operaion, IFse conrols fs Lached Shudown OCP OTP Brown-Ou UVLO Burs Mode Vcs>85mV or Vcs<-85mV Monior LATCH Monior CS Monior Thermal Monior BO Monior VCC Monior Burs Enable CMP Monior curren polariy once he gae driver is urning off Polariy is wrong? CMP imer à 52µs 1. Discharge SS cap afer 1µs delay 2. VCLK is held 3. Boh HSG and LSG are urned off CMP imer ou? LATCH>1.85V 1. Lach off he swiching pulse 2. Sof-sar capacior is fully discharged VCC<8.2V 1. Sop discharging he sof-sar capacior 2. Sop charging he TIMER capacior 3. Coninue normal operaion CS>0.78V 1. Discharge sof- sar capacior (10µs), increasing swiching frequency 2. TIMER capacior is charged (10µs) by an inernal 130µA curren source CS>0.78V CS>1.5V (Lach) Monior TIMER TIMER>2V 1. Swiching frequency is pushed o maximum 2. Sof-sar capacior is fully discharged 3. TIMER capacior is charged by an inernal 130µA curren source TIMER>3.5V (Lach) >150ºC 1. Sop he swiching pulse 2. Sof-sar capacior is fully discharged <120ºC BO>5.5 V or BO<1.81 V 1. Sop he swiching pulse 2. Sof-sar capacior is fully discharged 2.3 V<BO<5.5 V VCC<8.2 V 1. Sop he swiching pulse 2. Sof-sar capacior is fully discharged VCC>11 V Burs<1.23 V Sop he swiching pulse Burs>1.26 V Resume he swiching pulse o slope deeced? 1. Sop he swiching pulse 2. Sof sar capacior is fully discharged 3. Sop charging TIMER capacior 1. Sop he swiching pulse 2. TIMER capacior is discharged by exernal resisor Turn on he oher gae driver VCC<8.2V TIMER<0.28 V & VCC<8.2V Figure 23: Conrol Flow Char HR1001L Rev.1.0 www.monolihicpower.com 22

HR1001L EHACED LLC COTROLLER TPICAL APPLICATIO CIRCUIT PFC Pre-Regulaor Resonan Half-Bridge MP44010/ MP44014 HR1001L Figure 24: Applicaion Circui HR1001L Rev.1.0 www.monolihicpower.com 23

HR1001L EHACED LLC COTROLLER SSTEM TIMIG VCC VCCH VCCL Unplug from Main Inpu Over Temperaure LG/ Sof Sar LATCH CS VCS-OCP VCS-OCR TIMER VTIMER-SD VTIMER-fmax VTIMER-R BO VBO-On VBO-Off Burs VBurs VLATCH UVLO Brown- ormal In Lach Sof Sar Shudown OCP OCP (Lach) OCP (Lach) Brown-Ou OTP Burs Mode Figure 25: Sysem Timing Diagram HR1001L Rev.1.0 www.monolihicpower.com 24

HR1001L EHACED LLC COTROLLER PACKAGE IFORMATIO SOIC-16 OTICE: The informaion in his documen is subjec o change wihou noice. Users should warran and guaranee ha hird pary Inellecual Propery righs are no infringed upon when inegraing MPS producs ino any applicaion. MPS will no assume any legal responsibiliy for any said applicaions. HR1001L Rev. 1.0 www.monolihicpower.com 25