Lecture 6: Electronics Beyond the Logic Switches Xufeng Kou School of Information Science and Technology ShanghaiTech University EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 1
Outline Analog electronics MOSFET Operational Amplifier A/D and D/A conversion Power Electronics Memories EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 2
Logic Switch - MOSFET Metal-oxide-semiconductor field-effect transistor With the increase of V gs On/Off On-state: carrier channel formed, where the current can flow Off-state: carrier channel does not exist, no path for current to pass Control Actively controlled by electrical field Most importantly, MOSFET can be scaled down! EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry
MOSFET Beyond the ON/OFF States For digital electronics For analog electronics Cut off R 1 Conducting R 2 R 3 EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry
MOSFET I-V Characteristics I DS Linear region: I DS nc 2 ox W L [2( V GS V ) V DS A voltage-controlled resistor th V 2 DS ] Saturation region: V DS I D ncox W ( sat) ( VGS Vth 2 L 2 ) A voltage controlled current source EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 5
Basic MOSFET Amplifier DC load line: slope = 1/R D R D Transconductance g C V V Voltage Gain A m V n v v 0 i ox W L g m GS R D EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 6 th
Amplifier An electronic device that increases the power of a signal Taking energy from a power supply controlling the output to match the input signal shape but with a larger amplitude The opposite of an attenuator An amplifier provides gain, an attenuator provides loss Power supply EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 7
Operational Amplifier An Operational Amplifier (Op-Amp) is an integrated circuit that uses external voltage to amplify the input through a very high gain. Huge variety of applications, low cost, and ease of mass production make them extremely popular EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 8
Operational Amplifier (Cont.) Output gain high A v ~= 10 6 Tiny difference in the input voltages result in a very large output voltage Output limited by supply voltages One Useful Application: Analog Comparator If V + >V -, V out = HVS If V + <V -, V out = LVS If V + =V -, V out = 0V EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 9
Ideal Op-Amp R in is infinite R out is zero Amplification (Gain) V out / V in = Unlimited bandwidth V out = 0 when Voltage inputs = 0 EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 10
Analog Comparator Uses: Low-voltage alarms,night light controller EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 11
Pulse Width Modulator Output changes when V in ~= V pot Potentiometer used to vary duty cycle Uses: Motor controllers EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 12
Non-Inverting Op-Amp V in V out V in (1 R R 2 1 ) Uses: Amplify straight up EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 13
virtual ground Inverting Op-Amp V out R R f in V in Uses: Amplify straight up EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 14
Analog Adder Add multiple sensors inputs until a threshold is reached. EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 15
Analog Substractor V out V R3 R 2 1 R4 V1R ( R R ) R R 4 2 1 1 3 If all resistors are equal: V out V 2 V 1 EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 16
Integrating Op-Amp Uses: PID Controller EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 17
Differentiating Op-Amp Uses: PID Controller EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 18
Ideal Op-Amp vs Real Op-Amp Ideal Op-Amp Typical Op-Amp Input Resistance infinity 10 6 (bipolar) 10 9-10 12 (FET) Input Current 0 10-12 10-8 A Output Resistance 0 100 1000 Operational Gain infinity 10 5-10 9 Common Mode Gain 0 10-5 Bandwidth infinity Attenuates and phases at high frequencies (depends on slew rate) Temperature independent Bandwidth and gain EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 19
A Real Op-Amp Circuit EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 20
Op-Amp Applications Audio system Bio-electric signal EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 21
Conversion between A/D Connecting the digital computers and physical world EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 22
A/D and D/A Conversions Symbols EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 23
Digital-to-Analog Converters Pulse-width modulation The R-2R ladder DAC V out = a n 1 2 + a n 2 4 + + a 2 2 n 2 + a 1 2 n 1 + a 0 2 n EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 24
Analog-to-Digital Converters Flash ADC (also known as a Direct conversion ADC) Successive approximation ADC EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 25
Application: Digital Audio System EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 26
Signal and Power Signal a function that conveys information about the behavior or attributes of some phenomenon Power is a necessity for the acquisition, conditioning, transmission, storage, and visualization of signals (data) EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 27
Different Forms of Power Direct current (DC) power Alternating current (AC) power EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 28
Power Electronics The application of solid-state electronics to the control and conversion of electric power Conversions among different forms AC to DC (rectifier) DC to AC (inverter) DC to DC (DC-to-DC converter) AC to AC (AC-to-AC converter) EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 29
Half-Wave Rectifier Without filter capacitor With filter capacitor EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 30
Full-Wave Rectifier EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 31
DC-to-AC Inverter EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 32
Computer System Processor Reg Cache Memory-I/O bus Memory I/O controller I/O controller I/O controller Disk Disk Display Network EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 33
Levels in Memory Hierarchy cache virtual memory CPU regs C 8 B a 32 B Memory 8 KB c h e disk size: speed: $/Mbyte: block size: Register Cache Memory Disk Memory 200 B 2 ns 8 B 3MB~8MB 4 ns $100/MB 32 B 8 GB 60 ns $1.50/MB 8 KB 1000 GB 8 ms $0.05/MB slower, cheaper EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 34
Conceptual: linear array Random Access Chip Architecture Each box holds some data But this does not lead to a nice layout shape Too long and skinny Create a 2-D array! Decode Row and Column addresses EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 35
Memory Architecture: Decoders Using MUX Intuitive architecture for N M memory Too many select signals. Decoder reduces the number of select signals -> K = log 2 N EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 36
Memory Architecture CORE: -Keep square within a 2:1 ratio -Rows are word lines -Columns are bit lines -Data in and out on columns DECODERS: -Needed to reduce total number of pins -N+M address lines for 2 (N+M) bits of storage MULTIPLEXING: -Used to select one or more columns for input or output of data EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 37
Storage Mechanism Static Dynamic State Node (S) State Node (S) EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 38
Random Access Memories (RAM) STATIC Random Access Memories (SRAM) Data stored as long as supply is applied Larger (6 transistors/cell) Fast Differential (usually) DYNAMIC Random Access Memories (DRAM) Periodic refresh required Smaller (1~3 transistors/cell) Slower Single ended EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 39
Cache - Static RAM (SRAM) Fast ~4 ns access time Persistent as long as power is supplied no refresh required Expensive ~$100/MByte 6 transistors/bit Stable High immunity to noise and environmental disturbances Technology for caches EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 40
6-Transistor CMOS SRAM Cell EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 41
Anatomy of an SRAM Cell bit line bit line b b word line Stable Configurations 0 1 1 0 (6 transistors) Terminology: bit line: carries data word line: used for addressing Write: 1. set bit lines to new data value b is set to the opposite of b 2. raise word line to high sets cell to new state (may involve flipping relative to old state) Read: 1. set bit lines high 2. set word line high 3. see which bit line goes low EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 42
CMOS SRAM Analysis - Write k k n p C n C p ox ox W L W L 2 2 VQ VDSATp kn, M 6[( VDD VTn) VQ ] k p, M 4[( VDD VTp ) VDSATp ] 2 2 EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 43
CMOS SRAM Analysis - Write W PR W 4 6 / / L L 4 6 EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 44
CMOS SRAM Analysis - Read V DD V DD k n, M 5 [( V DD V V EE 224 Solid State Electronics II Tn 2 VDSATn ) VDSATn ] kn, M1[( VDD VTn) V Lecture 23: Lattice and symmetry V 2 2 ] 45
CMOS SRAM Analysis - Read EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 46
Memory - Dynamic RAM (DRAM) Slower than SRAM access time ~60 nsec Nonpersistant every row must be accessed every ~1 ms (refreshed) Cheaper than SRAM ~$1.50 / MByte 1 transistor/bit Fragile electrical noise, light, radiation Workhorse memory technology EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 47
Anatomy of a DRAM Cell Bit Line Access Transistor Word Line Storage Node C node C BL Writing Word Line Bit Line V Reading Word Line Bit Line Storage Node V ~ C node / C BL EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 48
3-Transistor DRAM Cell No constraints on device ratios Reads are non-destructive EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 49
Floating Gate MOSFET = Flash +++++ Assume: V DS =V D - V S =+12V What happens if?: V GS =V G V S= +12 V Then what happens?: to jailed electrons if V GS is set to 0V? EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry
Reading Memory State drain lines Control gate lines Change in Threshold Voltage due to Screening Effect of Floating Gate Read mode: Apply intermediate voltage, check whether current is flowing or not EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry
Writing Memory State Control gate voltage determines whether electrons are injected to, or push/pulled out of floating gate. EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry
NOR vs NAND Addressing Word = control gate; bit = drain NOR NAND 10x better endurance Fast read (~100 ns) Slow write (~10 μs) Used for Code EE 224 Solid State Electronics II Smaller cell size Slow read (~1 μs) Faster write (~1 μs) Used for Data Lecture 3: Lattice and symmetry
Solid-State Drive EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry
Solid-State Drive: Architecture EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry
Solid-State Drive: Architecture EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry
Solid-State Drive: Architecture EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry
Solid-State Drive: Advantages EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry
Solid-State Drive: Disadvantages EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry
Summary of Conventional Memories EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry