Prototype Performance and Design of the ATLAS Pixel Sensor

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Prototype Performance and Design of the ATLAS Pixel Sensor F. Hügging, for the ATLAS Pixel Collaboration Contents: - Introduction - Sensor Concept - Performance fi before and after irradiation - Conclusion Pixel 2000 June 2000, Genova, Italy F. Hügging - University of Dortmund

Participating Institutes Canada University of Toronto Czech Republic Academy of Sciences - Institue of Physics of Prague, Charles University of Prague, Czech Technical University of Prague France CPPM, Marseille Germany Bonn University, Dortmund University, Siegen University, Bergische University - Wuppertal, MPI Munich (R&D only) Italy INFN and University of Genova, INFN and University of Milano, INFN and University of Udine Netherlands NIKHEF - Amsterdam USA University of New York - Albany, LBL and University of California - Berkeley, University of California - Irvine, University of New Mexico - Albuquerque, University of Oklahoma, University of California - Santa Cruz, University of Wisconsin - Madison 2

Requirements pixel size 50µm x 400µm 50 µm pitch 12µm diameter bump connection total active area 2.3m 2 (2228 modules) high yield testability 10 years operation fault tolerance harsh radiation enviroment up to 10 15 cm -2 (1 MeV neutron eq.) radiation hard technology and design 3

Development Strategy Design Studies - performed within ATLAS - Prototype Sensors concerning - isolation technique - design of the pixel cell Studies of Silicon - performed within ROSE - Various Si Impurities concerning - damage parameters - fabrication process Radiation Tolerant Sensors 4

Sensor Concept 50*400 µm 2 pixel size n on n pixel moderated p-spray isolation 3 sensor tiles per wafer various test and monitor structures Photo of Prototype 1 Wafer 5

Sensor Concept before irradiation: p-on-n n-on-n after irradiation: have to be operated (almost) fully depleted potential drop on the read out side only single sided processing necessary can be operated partially depleted potential drop on the back side double sided processing needed 6

Isolation Techniques p-stop p-spray moderated p-spray before irr. : low E-field high E-field low E-field after irr. : high E-field low E-field low E-field 7

Quality Assurance Quality test plan for sensor production: I-V characteristics on every sensor before bonding, depletion on every wafer process parameters on special test structures (e.g. p-spray dose) both at vendor and at institutes for better control see talk by J. Klaiber-Lodewigs photo of bias grid structure 8

Performance leakage current before irradiation 9

Test Beam Studies Single Chip detectors bump bonded to FE electronics tested designs in CERN SPS Testbeam p-stop Design: Tile 1 p-spray Design: Tile 2, SSGb, SNGb radiation tests with p and p (sensors only) 10

Charge Collection Tile 1 Design: n + pixel and p-stop isolation Threshold 2 Ke p-stop contact hole metal n-implant pass. hole 11

Charge Collection Tile 2 Design: n + pixel and p-spray isolation Threshold 2 Ke contact hole metal n-implant pass. hole 12

Charge Collection Explanation for bad charge CCE of Tile 2 Design a modified Version of the Tile 2 design was introduced detailed 3D Simulations to understand this effect are in progress 13

Charge Collection SSGb Design: final design Threshold 2 Ke 14

Charge Collection SNGb Design: p-spray isolation, no bias grid Threshold 2 Ke 15

Charge Collection: Summary Old Design 280µm New Design 280µm Tile 1 Tile 2 SSG SSGb SNGb 1 hit 72.0 82.0 71.7 81.8 84.4 2 hits 3 hits Efficiency Losses 0 hits 25.2 2.4 99.6 14.6 2.2 98.8 25.6 2.0 99.3 15.6 1.7 99.1 15.0 1.1 99.5 0.4 1.2 0.7 0.9 0.5 0.1 0.4 0.2 0.4 0.4 SSGb good charge collection radiation hardness testability Not matched 0.2 0.2 0.2 0.1 0.0 Not in Time 0.1 0.6 0.3 0.4 0.1 16

Radiation Hardness I-V characteristics of irradiated sensors flip-chipped to FE-chip CCE of ST2 after irradiation with 10 15 n/ cm 2 at 600 V 30 25 20 C1-01S-ST1-02 C1-01S-ST2-02 p-stop Current [µa] 15 10 5 p-spray 0 0 100 200 300 400 500 Bias Voltage [V] Measured after 0.5 10 15 n/cm -2 at -18 o C 17

Radiation Hardness... oxygenated silicon IV of prototype 2 single chips on oxygented silicon after irradiation with 8.9. 10 14 n eq cm -2 (55MeV protons) final design SSGb measured at -20 C, unbumped sensors measured via bias-grid 18

Performance in time efficiency: space resolution: non - irradiated 3000 e threshold efficiency = 99.1% 81.8% single hits 15.6% double hits 1.7% > 2 hits 0.4% out of time 10 15 n eq / cm 2 3000 e threshold efficiency = 98.4% 94.2% single hits 3.1% double hits 1.1% > 2 hits 1.2% out of time charge sharing confined to 5 µm between adjacent pixels fraction of 2 pixels clusters is ~ 15% at 0 0 before irradiation ~ 7.5% after 10 15 n eq /cm 2 space resolution flat top: 22 µm 23 µm double hit: 5 µm 6 µm sensors moderated p-spray after irrad 19

Performance... depletion depth the method 2000 depletion 0.2868 track entrance point from beam telescope computed depth of charge 1000 0-30 * non irradiated 0 0.1 0.2 0.3 depth (mm) depleted non depleted after 10 15 cm -2 the depletion depth is 190 µm @ 600 V, 105 µm @ 300 V particle 0 0 0.1 0.2 0.3 depth (mm) 2000 1000 2000 1000-30 * -30 * 1x10 15, 600 V 1x10 15, 300 V depletion 0.1879-600 V 1x10 15 depletion 0.1047-300 V 1x10 15 0 0 0.1 0.2 0.3 depth (mm) 20

performance... prediction prediction calculation of V depl with oxgenated silicon 1st-layer: φ eq = 6.6. 10 14 cm -2 in 10 years B-layer:φ eq = 3.5. 10 14 cm -2 per year at full luminosity for B-layer > 85% charged hadrons, for 1st-layer 70% charged hadrons standard scenario: 100 days beam per year, 14 days warm-up @ 17 C, 3 days @ 20 C V dep (250µm)[V] 1000 800 600 400 200 operation voltage:600v 1st Layer standard silicon oxygenated silicon 1000 800 600 400 200 V dep (200µm)[V] 2000 1500 1000 500 operation voltage:600v B-layer standard silicon oxygenated silicon 2000 1500 1000 500 0 1 2 3 4 5 6 7 8 9 10 Preliminary time [years] 0 1 2 3 4 5 6 7 8 9 10 Preliminary ATLAS-PIXEL-01-02 4.2.2000 time [years] 21

next step... production wafer 3 tiles per wafer SSG, 20 µm gap 6 single chips tile like design Test-&monitor structures 6 diodes (2 designs) 4 mini-chips further structures for process monitoring 22

Conclusions Pixel Design Ready Radiation Hardness Ensured FDR and PRR Passed Tender for Production now Start of Production July/August 2000 23