The CMOS Inverter. Lecture 3a Static properties (VTC and noise margins)

The CMOS Inverter Lecture 3a Static properties (VTC and noise margins)

Why so much about inverters? The current that any CMOS logic gate can deliver or sink can be calculated from equivalent inverter! VDD pmos pull-up network I DSP Inputs Y nmos pull-down network I DSN VSS 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 2

Important CMOS Inverter knowledge First of all, of course the MOSFET schematic But you will capture the inverter schematic in lab 1 Don t forget to tie the body to VDD and GND! vdd! vdd! gnd! gnd! 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 3

The voltage characteristic (VTC) VTC shows vs in steady-state, i.e. quasi-static DC with d /dt=d /dt 0! NMOS works for positive gate and drain voltages PMOS works for negative gate and drain voltages However, the PMOS has its origo in (, ) when connected to VDD as in the inverter NMOS PMOS 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 4

The voltage characteristic (VTC) First Switching task: to occurs calculate in the the green switching region where voltage both VMOSFETs SW, i.e the are input saturated! voltage Hence, let that I DSN separates =I SDP a one and a zero : V sw k V V V N DD TP TN kp 1 k k N P kn k 2 2 P V V V V V 2 2 IN TN DD IN TP (, ) 2016-09-06 0 0 V TN V SW +V TP MCC092 IC Design - Lecture 3: The Inverter 5

VTC robustness It is good to have some feeling for what happens to the VTC...... for different k N /k P but how to interpret the V sw equation? V V V DD TP TN P N k k P N V sw k V V V N DD TP TN kp 1 k k N P Rewrite as V sw V TN V V V kn 1 k DD TP TN P 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 5

The voltage characteristic (VTC) What if we make n- channel MOSFET wider? What happens to VTC? V SW increases or decreases? Decreases, see slide 5! V V V DD TP TN V V V DD TP TN 1 k N k P 0 0 V TN V SW +V TP 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 7

The voltage characteristic (VTC) Which VTC is NAND and which VTC is NOR? NAND NOR 0 0 V TN V SW +V TP 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 8

The voltage characteristic (VTC) Find VTC equations for blue regions where only one MOSFET is saturated! k V V V V V V V V N 2 2 OUT IN TP IN TN DD IN TP kp Only n-channel MOSFET saturated V V V OUT IN TP Saturation conditions V V V OUT IN TN k V V V V V V V V 0 0 P V TN V SW 2 2 OUT IN TN IN TN DD IN TP kn p-channel MOSFET saturated +V TP 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 9

The voltage characteristic (VTC) How about current flow? No current flow in red regions! short-circuit current I SC flows in blue/green regions n-channel MOSFET saturated k I V V 2 N 2 P I V V V 2 SC IN TN k 2 SC DD IN TP 0 0 V TN V SW p-channel MOSFET saturated +V TP 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 10

Noise Margins NOISE MARGIN Even large variations in input signal... make only small variations in output signal Define noise margins NMH=V OH,min -V IH,min NML=V IL,max -V OL,max V OH,min Valid 1 V OL,max 0 0 V IL,max V IH,min Valid 0 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 11

Noise Margins: how to define valid output regions? Find points where slope A V = -1! Yields numbers for V OH,min (V OH,min, V IL,max ) and (V OL,max, V IH,min ) so that values for NMH and NMH can be calculated! Valid 1 V OL,max 0 0 V IL,max V IH,min Valid 0 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 12

Noise Margins an example Find points where slope A V = -1! 1.2 V Yields numbers for 1.06 V (V OH,min, V IL,max )=(1.06, 0.5) (V OL,max, V IH,min )=(0.12, 0.7) Hence NMH=1.06 0.7 = 0.36 V NML= 0.5 0.12 = 0.38 V Valid 1 0.12 V 0 0 0.5 V 0.7 V 1.2 V Valid 0 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 13

Noise margins textbook illustration NOISE MARGIN 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 14

Butterfly diagram Find points where slope A V = -1! Valid 1 V OH,min Define noise margins NMH=V OH,min -V IH,min NML=V IL,max -V OL,max V IH,min NMH V IL,max NML V OL,max 0 0 V IL,max V IH,min Valid 0 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 15

Noise Margins skewed inverters NMH NML NML NMH 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 16

Matching MOSFET current characteristics Match the corresponding p-channel and n-channel MOSFET curves to each other! I DS Fig. 2.26. Graphical derivation of CMOS inverter DC characteristics 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 17

Matching MOSFET current characteristics Match the corresponding p-channel and n-channel MOSFET curves to each other! I DS I DS I DS I DS I DS Fig. 2.26. Graphical derivation of CMOS inverter DC characteristics 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 18

Summary CMOS inverter schematic Voltage transfer characteristics (VTC) How to calculate swiching voltage V SW Understand V SW dependence on k N /k P Understand switching current (I SC ) flow Noise margins NMH and NMH Butterfly diagram Match current curves 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 19

Butterfly diagram - example Calculate the noise margins from given values! 1.04 V Valid 1 NMH 0.72 V V IL,max NML V OL,max 0 0.18 V 0.48 V V IH,min Valid 0 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 20

Not valid VIN Prelab task: To calculate the noise margins from given equations assuming V TN =0.29 V and V TP =-0.27 V, and assuming k N =k P! 1. k N =k P yields switching voltage =V sw =V TN +DV/2 2. Please note noise margin formulas given in prelab 1: V OH,min = -DV/8 V OL,max =DV/8 V IH,min =V SW -DV/8 V IL,max =V SW +DV/8 V OH,min V IH,min V sw Prelab 1 DV= -V TN +V TP =1.2-0.27-0.29=0.64 V 0.29 V 0.27 V NMH Valid 1 3. All values needed for our calculations involves DV= -V TN +V TP V IL,max NML V OL,max 0 V IL,max V IH,min Valid 0 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 21

Lecture 3b The CMOS Inverter Dynamic properties

Definitions of rise and fall delays Delays are defined at the 50% level! fall delay t pdf rise delay t pdr 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 23

Definitions of rise and fall times Rise and fall times are defined between the 20% and 80% levels! Sometimes between 10% and 90% levels fall time t f rise time t r 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 24

Step-respons model 1. =LOW 2. =HIGH Square wave approximation ON OFF OFF ON C L V SS 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 25

Step-response model: rise delay 1. =LOW Equivalent circuit I DSAT,P Square wave approximation I DS,P I DSAT,P C L /2 pmos current flow Load capacitance is charged through p-mosfet t pdr D = /2 DQ I CL DV I DSAT, P DSAT, P OUT 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 26

Step-response model: fall delay 2. =HIGH Square wave approximation Equivalent circuit I DS,N I DSAT,N I DSAT,N C L /2 V SS nmos current flow Load capacitance is discharged through n-mosfet t pdr D = /2 DQ I CL DV I DSAT, N DSAT, N OUT 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 27

The Inverter an electrical model Replace MOSFETs with their equivalent electrical circuits! N I k V V V 2 2 DSP IN DD TP PMOS C GP I DSP C DP NMOS C GN I DSN C DN V SS V SS kn I V V 2 2 DSN IN TN Inverter input capacitance: CG=CGN+CGP; MOSFET gate capacitances add! Inverter parasitic output capacitance: CD=CDN+CDP. Drain caps also add! V SS 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 28

The Inverter an electrical model Since is either or V SS (GND) we can modify schematic accordingly k N k I I,max V V V 2 2 N 2 2 DSP DSP IN DD DD TP TP I DSP,max I DSP,max = 300 ua/um I DSP C G =C GN +C GP V SS V SS I DSN I DSN,max C D =C DN +C DP I DSN,max = 600 ua/um knk I I DSN,max V VTN V 22 N 2 2 DSN DD TN Inverter input capacitance: CG=CGN+CGP; MOSFET gate capacitances add! Inverter parasitic output capacitance: CD=CDN+CDP. Drain caps also add! V SS 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 29

Problem If I DSN,max is 600 ma/um in the 65 nm CMOS process from STMicroelectronics, what would be the effective kprime (k N =mc ox )? In this process = 1.2 V, V TN = 0.29 V, C ox = 20 ff/mm 2, and L eff = 60 nm. k I V V 2 2 N DSN,max DD TN Similarly, if I DSP,max is 300 ma/um in the 65 nm CMOS process from STMicroelectronics, what would be the effective kprime (k N =mc ox )? In this process = 1.2 V, V TN = -0.27 V, C ox = 20 ff/mm 2, and L eff = 60 nm. k I V V 2 2 N DSP,max DD TP Answer: kn =87 ma/v 2, kn =42 ma/v 2 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 30

Ramp response Spice It simulations is obvious that show a ramp that approximation for about equal would input give and a output better model edge rates the ramp However, response this delay is too is complicated about 40% longer for simple than analytical the step response analysis delay! 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 31

Ramp response For a It balanced is obvious design that a with ramp approximately approximation equal would input give and a better output model edge rates However, this is too (i.e. complicated equal rise and for fall simple times) analytical analysis Spice simulations show that the ramp response delay is about 40% longer than the step response delay! Add 40% to step response delay and prefactor 0.5 becomes 0.7 C V /2 C V V t pd t pd 0.7 0.7CL I I I L DD L DD DD DSAT DSAT DSAT Defining the effective resistance during charge/discharge as our ramp response delay model becomes t pd =0.7R eff C L! R eff V I DD DSAT 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 32

Effective resistances: 60 nm MOSFETs R N,eff =2 kw. mm R P,eff =4 kw. mm I DS N-channel device I DSAT,max = I DS P-channel device 600 ma/mm I DSAT,max = 300 ma/mm R N,eff = /I DSAT,max R P,eff=/I DSAT,max =1.2 V V DS =1.2 V V DS 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 33

Electrical ramp response model Replace constant-current sources with effective resistances R P,eff = 4 kw. mm R P,eff C G R N,eff C D V SS V SS R N,eff = 2 kw. mm V SS 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 34

Ramp input output response 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 35

Ramp input output trace 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 36

Electrical ramp response model Complicated to keep track of different rise and fall delays! Replace with average effective resistance! R P,eff = 4 kw. mm R P,eff Redraw schematic! R ave C G R N,eff C D V SS V SS R N,eff = 2 kw. mm V SS R ave R R N, eff P, eff 3 kw 2 mm 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 37

Electrical ramp response model Even better to resize p-channel device, i.e. to make it wider, so that R P,eff =R N,eff VDD Task: Calculate C G and C D! 2W W=2 mm R ave VIN V VOUT OUT W W=1 mm C G C D VSS V SS V SS V SS R ave R R N, eff P, eff 2 kw 2 mm Answer: Assuming L=60 nm and Cox =20 ff/mm2 we obtain CGN =1.2 ff and C GP =2.4 ff. Hence C G =3.6 ff. Concerning C D we assume C D =pc G =3.6 ff with p=1. 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 38

Electrical ramp response model 2W RN, eff RP, eff Reff 2 kw mm CG 3.6 ff / mm 2 0.7R C 0.7 2kW mm 3.6 ff / mm 5ps eff G In an ideal inverter the time constant tao is really a constant, and that is independent of W R eff W C G C D V SS V SS V SS 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 39

Electrical ramp response model 2W RN, eff RP, eff Reff 2 kw mm CG 3.6 ff / mm 2 0.7R C 0.7 2kW mm 3.6 ff / mm 5ps eff G In an ideal inverter the time constant tao is really a constant, and that is independent of W R eff W C G C D V SS V SS V SS 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 40

Inverter pair delay R eff C G Left-hand inverter sees a capacitive load C G! 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 41

Inverter pair delay R eff C D C G Right-hand inverter sees a driver with internal source resistance R eff and a parasitic capacitance C D! 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 42

Inverter pair delay R eff RC-circuit with delay RCxln2=0.7RC C D C G The propagation delay becomes effective resistance times load cap! 0.7R C C 0.7R C p 1 5 ps 2 10 ps eff D G eff G 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 43

Inverter FO4 delay X1 C G X1 X1 R eff C G X1 C D C G X1 C G The FO4 propagation delay becomes Reff CD CG Reff CG p 0.7 4 0.7 4 5 ps 5 25 ps 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 44

Inverter FO4 delay X1 X1 R eff X1 C D 4C G X1 The FO4 propagation delay becomes Reff CD CG Reff CG p 0.7 4 0.7 4 5 ps 5 25 ps 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 45

Summary We defined rise and fall delays at the 50% level ( /2) We defined rise and fall times between 20% and 80% levels We calculated propagation delay in response to a square-wave input signal assuming MOSFETs being saturated during delay We improved the delay model by adding 40% assuming a ramp input signal and assuming equal input and output edge rates We heard a bell ring and replaced saturation current sources by effective resistances We made the p-channel MOSFET twice as wide to compensate for lower hole mobility (i.e. to compensate for k P =k N /2). Both MOSFETs now have the same effective resistance of 2 kw. mm However, p-channel device now has twice the input capacitance of the n-channel MOSFET We have obtained an electrical two-port model of the inverter for delay calculations we know what this model looks like seen from the input port, and seen from the output port Finally, we calculated the FO4 delay, and we found the R eff C G product being independent of the inverter size (as long as we keep same ratio between W P and W N ) 2016-09-06 MCC092 IC Design - Lecture 3: The Inverter 46