ISSCC 2003 / SESSION 10 / HIGH SPEE BUILING BLOCKS / PAPER 10.3 10.3 A 2.5 to 10GHz Clock Multiplier Unit with 0.22ps RMS Jitter in a 0.18µm CMOS Technology Remco C.H. van de Beek 1, Cicero S. Vaucher 2, omine M.W. Leenaerts 2, Nenad Pavlovic 2, Ketan Mistry 3, Eric A.M. Klumperink 1, Bram Nauta 1 1 University of Twente, IC-esign Group, The Netherlands 2 Philips Research Laboratories Eindhoven, The Netherlands 3 University of Southampton, United Kingdom High-speed low-jitter serial optical transmitters rely on a highperformance clock multiplier unit (CMU) to convert a parallelinput clock signal into a serial-output clock signal. For SONET/SH compliant systems, the transmitter CMU typically consumes a large part of the power budget, as multi-ghz operation combined with sub-picosecond jitter is required. The trend in serial communication circuits is the increase in frequencies of the parallel input clock and of the serial output clock signals. At this moment, the state-of-the-art CMU implemented in a standard CMOS technology [1] operates with a parallel input signal of 622MHz and puts out a signal at 10GHz. It is anticipated, however, that next-generation serial transmitters will operate with parallel, or reference frequency, signals of the order of 2.5GHz and will require the CMU to produce output signals in the 10-40GHz range. A 10GHz CMU, implemented in 0.18µm CMOS is described, that works with reference frequencies in excess of 2.5GHz, with significantly better jitter and power dissipation performance than reported in CMOS [1]. The 2.5GHz reference is seen as a step towards the realization of OC-768 transmitters (40Gb/s) in CMOS. To achieve this high reference frequency, a fast linear Phase etector (P) in combination with a Frequency etector (F) is used. Figure 10.3.1 shows the top-level block diagram of the CMU with the new P and F. The speed of a conventional tri-state Phase Frequency etector (PF) is limited due to the internal reset loop needed to asynchronously reset the logical circuitry that generates the UP and N pulses for the Charge Pump (CP). ue to the absence of this slow reset loop in the proposed P, it can run at much higher frequencies. Simulations show a speed improvement of at least a factor 5, in a 0.18µm CMOS technology. To achieve low jitter operation, the detector generates CP signals, thus inheriting the favorable noise and spurious injection properties of CP-based PLLs. The operation of the P is illustrated in Fig. 10.3.2. It exploits the readily available quadrature signals of the last divider stage (ivi and ivq) to generate UP/N pulses using two ANgates. Note that the width of the UP pulse responds linearly to the time overlap of ivq and Ref. The width of the N pulse depends on the time-overlap of ivq and ivi. In lock, with coinciding rising edges of Ref and ivi, the UP pulse has the same width as the N pulse, in which case the CP current sources cancel, resulting in low output spurs. When in phase-lock, the UP/N signals have a duty-cycle of about 25%, so that a potential dead-zone in the transfer function of the P/CP combination is easily avoided. It is demonstrated that the locking position and the gain of the P/CP combination are insensitive to the quadrature accuracy of the ivi and ivq signals, and to the duty cycle of the reference signal. These properties do influence the extremes of the linear operation input range of the P, which for perfect conditions ranges from -π/2 to +π/2. is similar to the architecture presented in [2], with two ANgates added to generate CP compatible signals (UPF and NF). The F works reliably to much higher frequencies than the conventional PF architecture, as the F flip-flops have an output frequency that equals the difference between the reference frequency and the divided VCO frequency. Also, the flipflops need not be reset asynchronously, which makes their design easier and faster. A further strong point of the proposed detector is its inactivity when frequency lock has been achieved, eliminating the need for a lock detector. The P and F work in parallel without the F disturbing the loop when in phase-lock. The 2.5GHz reference frequency allowed by this P/F combination lowers the frequency division ratio of the loop as compared to that of a lower reference frequency PLL. This in turn will lower the close-in phase noise and the integrated output jitter. Because the optimum loop bandwidth increases due to the lower close-in phase noise, the loop filter capacitor sizes decrease, thus significantly reducing chip area. The CMU was realized in a standard 0.18µm 5M CMOS process with a substrate resistivity of 10Ω*cm no possibility of triple well isolation. The frequency dividers and logic elements of the IC are implemented using Current Mode Logic (CML) to ensure both low sensitivity to and low generation of supply and substrate noise. The CPs use low-voltage mirrors to enable rail-to-rail operation at the output node and to increase the CP output resistance. The 10GHz LC VCO is constructed around a negative Gmcell implemented as a cross-coupled NMOS differential pair. The VCO uses an inductor with a patterned ground shield to decrease substrate losses, achieving a measured Q of 17 at 10GHz [3]. The PLL loop bandwidth is optimized with respect to jitter performance, using noise simulations combined with VCO noise measurements. The IC draws 55mA from the 1.8V power supply (99mW), including the output buffer. The measured time-domain operation of the CMU is presented in Fig. 10.3.4. The 2.5GHz input signal is derived from a Marconi 2042 signal generator. The CMU jitter generation is measured with a HP3048A phase noise measurement setup in PLL-configuration. The phase noise spectrum of the 10GHz output signal is shown in Fig. 10.3.5. Integration of the phase noise spectrum using the integration limits defined for OC-192 SONET systems (50kHz to 80MHz) yields an rms-jitter of 0.8 O (equivalent to 2.2mUI rms), which is almost a factor 5 lower than the SONET recommendation of 10mUI rms. A usual rule-of-thumb can be used to predict a peak-to-peak jitter of 2.2ps (22mUI rms). The table in Fig. 10.3.6 summarizes the IC performance. Comparing to state-of-the-art [1] this design realized an approximate factor 3 improvement in peak jitter performance, and 2 to 3 times less power dissipation in a comparable technology. Figure 10.3.7 shows the chip micrograph. References [1] M.M. Green et al., OC-192 Transmitter in Standard 0.18µm CMOS, ISSCC ig. Tech. Papers, pp. 248-249, 2002. [2] A. Pottbäcker, U. Langmann and H.-U. Schreiber, A Si Bipolar Phase and Frequency etector IC for Clock Extraction up to 8Gb/s, IEEE Journal of Solid State Circuits, vol. 27, pp. 1747-1751, ec. 1992. [3]. Leenaerts and N. Pavlovic, esign of Wireless LAN Circuits in RF- CMOS, Workshop on Advances in Analog Circuit esign, 2002. Because of the limited pull-in range of the P, a frequency detector (F) as shown in Fig. 10.3.3 is added to ensure correct locking of the PLL over the entire tuning range of the VCO. The F
ISSCC 2003 / February 11, 2003 / Salon 9 / 9:30 AM &'( #$%&' #$ #% #$% &%'%(')* <%;%-%=>% :0;;%- 6-%@0%=>( %8%>85- & *+,-.% /0123,- /,-. /. #$ #$ % # % # & #$%?*9 4552 678%- 908208 :0;;%- ' ( '(Ω )*+ $$(%&' -,./A.7B=/)*13 -,./A7+=/)*13 )* -,. -,./,-0)*1-,./ /0-,.1-,./ +,() #$%&'(&) #$%&'(&) Figure 10.3.1: CMU architecture. Figure 10.3.2: P response. 10 #$ < < ),-. #% < ) /. &'( Figure 10.3.3: F implementation. Figure 10.3.4: Oscilloscope screendump of 2.5GHz input and 10GHz output. E,:>,:/)-.X,.@8H Z.F.-.@8./)-.X,.@8H \.89@?A?+H O*::.-/%.@.-7:*?@/LZ5KN O*::.-/%.@.-7:*?@/L>.7PQ:?Q>.7PN K,>>AH/U?A:7+. 49*>/K*'. ;?S.-/4?@=,C>:*?@ $$(2/%&' #II/%&' 10I[C/=:7@B7-B/45EK 1IV -C=W/.X,*Y/:?/1/>=/-C= />=/L=>.8/M/01/>=N 0I/U 1I2/J/1IG/CC $$/CR I0/CR/S*:9?,:/?,:>,:/T,FF.- Figure 10.3.5: Phase noise measurement results. Figure 10.3.6: CMU performance summary.
#$%&'()* 234 +&,-&./ 85 9 38 +011)*- 5&6&7)*- %5 9 38 Figure 10.3.7: Chip micrograph. 10
&'( #$%&' #$ #% #$% &%'%(')* <%;%-%=>% :0;;%- 6-%@0%=>( %8%>85- & *+,-.% /0123,- /,-. /. #$ #$ % # % # &?*9 4552 678%- 908208 :0;;%- ' ( '(Ω )*+ $$(%&' #$% #$%&'(&) #$%&'(&) Figure 10.3.1: CMU architecture.
-,./A.7B=/)*13 -,./A7+=/)*13 )* -,. -,./,-0)*1-,./ /0-,.1-,./ +,() Figure 10.3.2: P response.
#$ < < ),-. #% < ) /. &'( Figure 10.3.3: F implementation.
Figure 10.3.4: Oscilloscope screendump of 2.5GHz input and 10GHz output.
Figure 10.3.5: Phase noise measurement results.
E,:>,:/)-.X,.@8H Z.F.-.@8./)-.X,.@8H \.89@?A?+H O*::.-/%.@.-7:*?@/LZ5KN O*::.-/%.@.-7:*?@/L>.7PQ:?Q>.7PN K,>>AH/U?A:7+. 49*>/K*'. ;?S.-/4?@=,C>:*?@ $$(2/%&' #II/%&' 10I[C/=:7@B7-B/45EK 1IV -C=W/.X,*Y/:?/1/>=/-C= />=/L=>.8/M/01/>=N 0I/U 1I2/J/1IG/CC $$/CR I0/CR/S*:9?,:/?,:>,:/T,FF.- Figure 10.3.6: CMU performance summary.
#$%&'()* 234 +&,-&./ 85 9 38 +011)*- 5&6&7)*- %5 9 38 Figure 10.3.7: Chip micrograph.