Sensitive Gate Silicon Controlled Rectifiers Reverse Blocking Thyristors Designed for high volume, low cost, industrial and consumer applications such as motor control; process control; temperature, light and speed control; CDI (Capacitive Discharge Ignition); and small engines. Features Small Size Passivated Die for Reliability and Uniformity Low Level Triggering and olding Characteristics Epoxy Meets UL 9 V0 @ 25 in ESD Ratings: uman Body Model, 3B 8000 V Machine Model, C 00 V These are PbFree Devices SCRs 12 MPERES RMS 600 800 VOLTS G K MRKING DIGRMS MXIMUM RTINGS (T J = 25 C unless otherwise noted) Rating Symbol Value Unit Peak Repetitive OffState Voltage (Note 1) (T J = 0 to 1 C, Sine Wave, 50 z to V DRM, V RRM V 60 z) MCR12DSM 600 MCR12DSN 800 OnState RMS Current (180 Conduction ngles; T C = 75 C) verage OnState Current (180 Conduction ngles; T C = 75 C) Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave 60 z, T J = 1 C) I T(RMS) 12 I T(V) 7.6 I TSM 0 1 2 3 1 2 3 DPK CSE 369C STYLE IPK CSE 369D STYLE YWW R1 2DSxG YWW R1 2DSxG Circuit Fusing Consideration (t = 8.3 msec) I 2 t 1 2 sec Forward Peak Gate Power (Pulse Width sec, T C = 75 C) Forward verage Gate Power (t = 8.3 msec, T C = 75 C) P GM 5.0 W P G(V) 0.5 W Y WW R12DSx G = Year = Work Week = Device Code x= M or N = PbFree Package Forward Peak Gate Current (Pulse Width sec, T C = 75 C) I GM 2.0 Operating Range T J 0 to 1 C Storage Temperature Range T stg 0 to 150 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. V DRM and V RRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the device are exceeded. 1 2 3 PIN SSIGNMENT Cathode node Gate node ORDERING INFORMTION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Semiconductor Components Industries, LLC, 2013 June, 2013 Rev. 7 1 Publication Order Number: MCR12DSM/D
TERML CRCTERISTICS Thermal Resistance, JunctiontoCase Thermal Resistance Junctiontombient Thermal Resistance Junctiontombient (Note 2) Characteristic Symbol Max Unit Maximum Lead Temperature for Soldering Purposes (Note 3) T L 260 C R JC R J R J 2.2 88 80 C/W ELECTRICL CRCTERISTICS (T J = 25 C unless otherwise noted) Characteristics Symbol Min Typ Max Unit OFF CRCTERISTICS Peak Repetitive Forward or Reverse Blocking Current (Note ) (V K = Rated V DRM or V RRM ; R GK = K ) T J = 25 C T J = 1 C ON CRCTERISTICS Peak Reverse Gate Blocking Voltage, (I GR = ) V GRM 12.5 18 V Peak Reverse Gate Blocking Current, (V GR = V) I GRM 1.2 Peak Forward OnState Voltage (Note 5), (I TM = 20 ) V TM 1.3 1.9 V Gate Trigger Current (Continuous dc) (Note 6) (V D = 12 V, R L = 0 ) T J = 25 C T J = 0 C Gate Trigger Voltage (Continuous dc) (Note 6) (V D = 12 V, R L = 0 ) T J = 25 C T J = 0 C T J = 1 C olding Current (V D = 12 V, Initiating Current = 200 m, R GK = 1 k ) T J = 25 C T J = 0 C Latching Current (V D = 12 V, I G = 2.0 m, R GK = 1 k ) T J = 25 C T J = 0 C TurnOn Time (Source Voltage = 12 V, R S = K, I T = 16 (pk), R GK = K ) (V D = Rated V DRM, Rise Time = 20 ns, Pulse Width = s) DYNMIC CRCTERISTICS Critical Rate of Rise of OffState Voltage (V D = 0.67 x Rated V DRM, Exponential Waveform, R GK = K, T J = 1 C) I DRM, I RRM I GT 5.0 V GT 0.5 0.2 I 0.5 I L 0.5 tgt dv/dt 12 0.65 500 200 300 1.5 2.0 5.0 2.0 Critical Rate of Rise of OnState Current di/dt / s (I PK = 50, P W = 0 sec, dig/dt = 1 / sec, I GT = m) 50 0 2. These ratings are applicable when surface mounted on the minimum pad sizes recommended. 3. 1/8 from case for seconds.. Ratings apply for negative gate voltage or R GK = k. Devices shall not have a positive gate voltage concurrently with a negative voltage on the anode. Devices should not be tested with a constant current source for forward and reverse blocking capability such that the voltage applied exceeds the rated blocking voltage. 5. Pulse Test: Pulse Width 2.0 msec, Duty Cycle 2%. 6. R GK current not included in measurement. V m m s V/ s 2
Voltage Current Characteristic of SCR + Current node + Symbol V DRM I DRM V RRM I RRM V TM I Parameter Peak Repetitive Off State Forward Voltage Peak Forward Blocking Current Peak Repetitive Off State Reverse Voltage Peak Reverse Blocking Current Peak On State Voltage olding Current I RRM at V RRM on state Reverse Blocking Region (off state) Reverse valanche Region V TM I + Voltage I DRM at V DRM Forward Blocking Region (off state) node T C, MXIMUM LLOWBLE CSE TEMPERTURE ( C) 1 5 0 95 90 85 80 dc 180 (V), VERGE POWER DISSIPTION (WTTS) 75 = Conduction 2.0 ngle = 30 60 90 120 70 0 0 2.0 3.0.0 5.0 7.0 8.0 0 2.0 3.0.0 5.0 7.0 8.0 I T(V), VERGE ON-STTE CURRENT (MPS) I T(V), VERGE ON-STTE CURRENT (MPS) P 16 1 12 8.0.0 = Conduction ngle = 30 60 90 120 180 dc Figure 1. verage Current Derating Figure 2. OnState Power Dissipation 3
I I MCR12DSM, MCR12DSN, INSTNTNEOUS ON-STTE CURRENT (MPS) T 0 0 TYPICL @ T J = 25 C MXIMUM @ T J = 1 C MXIMUM @ T J = 25 C r (t), TRNSIENT TERML RESISTNCE (NORMLIZED) Z JC(t) = R JC(t) r(t) 0.01 2.0 3.0.0 5.0 0 00 K V T, INSTNTNEOUS ON-STTE VOLTGE (VOLTS) t, TIME (ms) Figure 3. OnState Characteristics Figure. Transient Thermal Response 00 I GT, GTE TRIGGER CURRENT ( ) 0-0 R GK = K GTE OPEN V GT, GTE TRIGGER VOLTGE (VOLTS) -25-5.0 20 35 50 65 80 95 1-0 -25-5.0 20 35 50 65 80 95 1 T J, JUNCTION TEMPERTURE ( C) T J, JUNCTION TEMPERTURE ( C) Figure 5. Typical Gate Trigger Current versus Figure 6. Typical Gate Trigger Voltage versus R GK = K R GK = K I, OLDING CURRENT (m), LTCING CURRENT (m) L -0-25 - 5.0 20 35 50 65 80 95 1-0 -25-5.0 20 35 50 65 80 95 1 T J, JUNCTION TEMPERTURE ( C) T J, JUNCTION TEMPERTURE ( C) Figure 7. Typical olding Current versus Figure 8. Typical Latching Current versus
I MCR12DSM, MCR12DSN T J = 25 C 00, OLDING CURRENT (m) 8.0.0 2.0 I GT = 25 I GT = STTIC dv/dt (V/ s) 0 70 C 90 C T J = 1 C 0 0 00 K 0 00 Figure 9. olding Current versus GateCathode Resistance Figure. Exponential Static dv/dt versus GateCathode Resistance and Junction Temperature 00 00 V T J = 1 C 00 V D = 800 V T J = 1 C STTIC dv/dt (V/ s) 0 600 V V PK = 800 V STTIC dv/dt (V/ s) 0 I GT = 25 I GT = 0 00 0 00 Figure 11. Exponential Static dv/dt versus GateCathode Resistance and Peak Voltage Figure 12. Exponential Static dv/dt versus GateCathode Resistance and Gate Trigger Current Sensitivity ORDERING INFORMTION MCR12DSMTG Device Package Type Package Shipping DPK (PbFree) 369C 2500 / Tape & Reel MCR12DSN1G IPK (PbFree) 369D 75 Units / Rail MCR12DSNTG DPK (PbFree) 369C 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 5
PCKGE DIMENSIONS DPK (SINGLE GUGE) CSE 369C ISSUE D L3 L b2 e E b3 1 2 3 b D B DETIL c 0.005 (3) M C C c2 L2 GUGE PLNE L L1 DETIL ROTTED 90 CW 1 C Z SETING PLNE NOTES: 1. DIMENSIONING ND TOLERNCING PER SME Y1.5M, 199. 2. CONTROLLING DIMENSION: INCES. 3. TERML PD CONTOUR OPTIONL WITIN DI- MENSIONS b3, L3 and Z.. DIMENSIONS D ND E DO NOT INCLUDE MOLD FLS, PROTRUSIONS, OR BURRS. MOLD FLS, PROTRUSIONS, OR GTE BURRS SLL NOT EXCEED 0.006 INCES PER SIDE. 5. DIMENSIONS D ND E RE DETERMINED T TE OUTERMOST EXTREMES OF TE PLSTIC BODY. 6. DTUMS ND B RE DETERMINED T DTUM PLNE. INCES MILLIMETERS DIM MIN MX MIN MX 0.086 0.09 2.18 2.38 1 0.000 0.005 0.00 3 b 0.025 0.035 0.63 0.89 b2 0.030 0.05 0.76 1.1 b3 80 0.215.57 5.6 c 0.018 0.02 0.6 0.61 c2 0.018 0.02 0.6 0.61 D 0.235 0.25 5.97 6.22 E 0.250 0.265 6.35 6.73 e 0.090 BSC 2.29 BSC 0.370 0. 9.0.1 L 0.055 0.070 1.0 1.78 L1 0.8 REF 2.7 REF L2 0.020 BSC 0.51 BSC L3 0.035 0.050 0.89 1.27 L 0.00 1 Z 55 3.93 SOLDERING FOOTPRINT* STYLE : PIN 1. CTODE 2. NODE 3. GTE. NODE 6.20 0.2 2.58 0.2 3.00 18 5.80 0.228 1.60 0.063 6.17 0.23 SCLE 3:1 mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6
PCKGE DIMENSIONS IPK CSE 369D ISSUE C V B R C E NOTES: 1. DIMENSIONING ND TOLERNCING PER NSI Y1.5M, 1982. 2. CONTROLLING DIMENSION: INC. S T SETING PLNE F 1 2 3 G K D 3 PL J 3 (0.005) M T Z INCES MILLIMETERS DIM MIN MX MIN MX 0.235 0.25 5.97 6.35 B 0.250 0.265 6.35 6.73 C 0.086 0.09 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.6 0.58 F 0.037 0.05 0.9 1.1 G 0.090 BSC 2.29 BSC 0.03 0.00 0.87 1 J 0.018 0.023 0.6 0.58 K 0.350 0.380 8.89 9.65 R 80 0.215.5 5.5 S 0.025 0.00 0.63 1 V 0.035 0.050 0.89 1.27 Z 55 3.93 STYLE : PIN 1. CTODE 2. NODE 3. GTE. NODE ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of SCILLC s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patentmarking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 US Phone: 3036752175 or 80033860 Toll Free US/Canada Fax: 3036752176 or 80033867 Toll Free US/Canada Email: orderlit@onsemi.com N. merican Technical Support: 8002829855 Toll Free US/Canada Europe, Middle East and frica Technical Support: Phone: 21 33 790 29 Japan Customer Focus Center Phone: 813581750 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MCR12DSM/D