Feaures and Benefis Supply volage 6 o 48 V True average oupu curren conrol 3.0 A maximum oupu over operaing emperaure range Cycle-by-cycle curren limi Inegraed MOSFET swich Dimming via direc logic inpu or power supply volage Inernal conrol loop compensaion Undervolage lockou (UVLO) and hermal shudown proecion Low power shudown (1 μa ypical) Robus proecion agains: Adjacen pin-o-pin shor Pin-o-GND shor Componen open/shor fauls Package 8-pin SOICN wih exposed hermal pad (suffix LJ): No o scale Descripion The A6211 is a single IC swiching regulaor ha provides consan-curren oupu o drive high-power LEDs. I inegraes a high-side N-channel DMOS swich for DC-o-DC sep- down (buck) conversion. A rue average curren is oupu using a cycle-by-cycle, conrolled on-ime mehod. Oupu curren is user-selecable by an exernal curren sense resisor. Oupu volage is auomaically adjused o drive various numbers of LEDs in a single sring. This ensures he opimal sysem efficiency. LED dimming is accomplished by a direc logic inpu pulse widh modulaion (PWM) signal a he enable pin. The device is provided in a compac 8-pin narrow SOIC package (suffix LJ) wih exposed pad for enhanced hermal dissipaion. I is lead (Pb) free, wih 100% mae in leadframe plaing. Applicaions: General Illuminaion Scanners and muli-funcion priners (ligh bars) Archiecural lighing Indusrial Lighing Display case lighing / MR16 Typical Applicaion Circui (6 o 48 V) GND EN C1 Enable/PWM Dimming (100 Hz o 2 khz) R1 1 2 3 4 VIN TON EN CS 8 SW A6211 7 BOOT 6 PAD GND VCC 5 C5 D1 L1 LED+... LED RSENSE A6211-DS, Rev. 1
Selecion Guide Par Number Operaing Ambien Temperaure, T A Package Packing A6211GLJTR-T 40ºC o 105ºC 8-pin SOICN wih exposed hermal pad 3000 pieces per 13-in reel Absolue Maximum Raings Characerisic Symbol Noes Raing Uni Supply Volage 0.3 o 50 V Boosrap Drive Volage V BOOT 0.3 o + 8 V Swiching Volage V SW 1.5 o + 0.3 V Linear Regulaor Terminal V CC VCC o GND 0.3 o 14 V Enable and TON Volage V EN, V TON 0.3 o + 0.3 V Curren Sense Volage V CS 0.3 o 7 V Operaing Ambien Temperaure T A G emperaure range 40 o 105 ºC Maximum Juncion Temperaure T J (max) 150 ºC Sorage Temperaure T sg 55 o 150 ºC Thermal Characerisics*may require deraing a maximum condiions, see applicaion secion for opimizaion Characerisic Symbol Tes Condiions* Value Uni Package Thermal Resisance (Juncion o Ambien) On 4-layer PCB based on JEDEC sandard 35 ºC/W R θja On 2-layer generic es PCB wih 0.8 in. 2 of copper area each side 62 ºC/W Package Thermal Resisance R (Juncion o Pad) θjp 2 ºC/W *Addiional hermal informaion available on he Allegro websie. Pin-ou Diagram VIN TON 1 2 8 7 SW BOOT PAD EN CS 3 4 6 5 GND VCC Terminal Lis Table Number Name Funcion 1 VIN Supply volage inpu erminals 2 TON Regulaor on-ime seing resisor erminal 3 EN Logic inpu for Enable and PWM dimming 4 CS Drive oupu curren sense feedback 5 VCC Inernal linear regulaor oupu 6 GND Ground erminal 7 BOOT DMOS gae driver boosrap erminal 8 SW Swiched oupu erminals PAD Exposed pad for enhanced hermal dissipaion; connec o GND 2
Funcional Block Diagram CVCC CBOOT L1 LED Sring VCC BOOT SW D1 VIN V REG 5.3 V V CC UVLO Average R ON TON On-Time Curren Generaor On-Time Timer Off-Time Timer Gae Drive UVLO Shudown Level Shif EN C COMP V IL = 0.4 V V IH = 1.8 V + IC and Driver Conrol Logic Curren Limi Off-Time Timer + I LIM Buck Swich Curren Sense 0.2 V + + V CC UVLO Thermal Shudown CS PAD GND RSENSE 3
ELECTRICAL CHARACTERISTICS Valid a = 24 V, for T A = 40 C o 105 C, ypical values a T A = 25 C; unless oherwise noed Characerisics Symbol Tes Condiions Min. Typ. Max. Uni Inpu Supply Volage T A = 25 C 6 48 V Undervolage Lockou Threshold V UVLO increasing 5.3 V Undervolage Lockou Hyseresis V UVLO_HYS decreasing 150 mv VIN Pin Supply Curren I IN V CS = 0.5 V, EN = high 5 ma VIN Pin Shudown Curren I INSD EN shored o GND 1 10 μa Buck Swich Curren Limi Threshold I SWLIM 3.0 4.0 5.0 A Buck Swich On-Resisance R DS(on) V BOOT = + 4.3 V, T A = 25 C, I SW = 1 A 0.25 0.4 Ω BOOT Undervolage Lockou Threshold V BOOTUV V BOOT o V SW increasing 1.7 2.9 4.3 V BOOT Undervolage Lockou Hyseresis V BOTUVHYS V BOOT o V SW decreasing 370 mv Swiching Minimum Off-Time OFFmin V CS = 0 V 110 150 ns Swiching Minimum On-TIme ONmin 110 150 ns Seleced On-Time ON = 24 V, = 12 V, R ON = 137 kω 800 1000 1200 ns Regulaion Comparaor and Error Amplifier Load Curren Sense Regulaion Threshold V CSREG V CS decreasing, SW urns on 187.5 200 210 mv Load Curren Sense Bias Curren I CSBIAS V CS = 0.2 V, EN = low 0.9 μa Inernal Linear Regulaor VCC Regulaed Oupu V CC 0 ma < I CC < 5 ma, > 6 V 5.0 5.3 5.6 V VCC Curren Limi* I CCLIM = 24 V, V CC = 0 V 5 20 ma Enable Inpu Logic High Volage V IH V EN increasing 1.8 V Logic Low Volage V IL V EN decreasing 0.4 V EN Pin Pull-down Resisance R ENPD V EN = 5 V 100 kω Maximum PWM Dimming Off-Time PWML conrol, and inernal references are powered-on 10 17 ms Measured while EN = low, during dimming (exceeding PWML resuls in shudown) Thermal Shudown Thermal Shudown Threshold T SD 165 C Thermal Shudown Hyseresis T SDHYS 25 C *The inernal linear regulaor is no designed o drive an exernal load 4
Characerisic Performance C1,C2 C1,C2 V EN V EN Panel 1A. = 19 V Panel 1B. = 24 V C1,C2 V EN Panel 1C. = 30 V Figure 1. Sarup waveforms from off-sae a various inpu volages; noe ha he rise ime of he LED curren depends on inpu/oupu volages, inducor value, and swiching frequency Operaing condiions: LED volage = 15 V, LED curren = 1.3 A, R 1 = 63.4 kω (frequency = 1 MHz in seady sae), = 19 V (panel 1A), 24 V (panel 1B) and 30 V (panel 1C) Oscilloscope seings: CH1 (Red) = (10 V/div), CH2 (Blue) = (10 V/div), CH3 (Green) = (500 ma/div), CH4 (Yellow) = Enable (5 V/div), ime scale = 50 μs/div 5
C1,C2 V EN Panel 2A. Duy cycle = 50% and ime scale = 1 ms/div C1,C2 V EN Panel 2B. Duy cycle = 2% and ime scale = 50 μs/div Figure 2. PWM operaion a various duy cycles; noe ha here is no sarup delay during PWM dimming operaion Operaing condiions: a 200 Hz, = 24 V, = 15 V, R1 = 63.4 kω, duy cycle = 50% (panel 2A) and 2% (panel 2B) CH1 (Red) = (10 V/div), CH2 (Blue) = (10 V/div), CH3 (Green) = (500 ma/div), CH4 (Yellow) = Enable (5 V/div), ime scale = 1 ms/div (panel 2A) and 50 μs/div (panel 2B) 6
95 95 Efficiency, (%) 90 85 80 = 24 V, = 15 V = 12 V, = 5.5 V = 12 V, = 3.5 V Efficiency, (%) 90 85 80 f SW = 500 khz f SW = 2 MHz f SW = 1 MHz 75 75 70 0 0.5 1.0 1.5 2.0 2.5 3.0 LED Curren, (A) 70 0 0.5 1.0 1.5 2.0 2.5 3.0 LED Curren, (A) Figure 3. Efficiency versus LED Curren a various LED volages Operaing condiions: f SW = 1 MHz Figure 4. Efficiency versus LED Curren a various swiching frequencies Operaing condiions: = 12 V, = 5.5 V 1 LED Curren (A) 0.1 0.01 = 3 A = 2 A = 1.4 A 0.001 0.1 1 10 100 Duy Cycle (%) Figure 5. Average LED Curren versus PWM dimming percenage Operaing condiions: = 12 V, = 3.5 V, f SW = 1 MHz, f PWM = 200 Hz, L = 10 μh 7
Funcional Descripion The A6211 is a buck regulaor designed for driving a high-curren LED sring. I uilizes average curren mode conrol o mainain consan LED curren and consisen brighness. The LED curren level is easily programmable by selecion of an exernal sense resisor, wih a value deermined as follows: = V CSREG / R SENSE where V CSREG = 0.2 V ypical. Swiching Frequency The A6211 operaes in fixed on-ime mode during swiching. The on-ime (and hence swiching frequency) is programmed using an exernal resisor conneced beween he VIN and TON pins, as 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100 120 140 160 180 200 220 240 260 R TON (kω) Figure 6. Swiching Frequency versus R TON Resisance fsw (MHz) During SW on-ime: i RIPPLE = [( ) / L] ON = [( ) / L] T D where D = ON / T. During SW off-ime: i RIPPLE = [( V D ) / L] OFF = [( V D ) / L] T (1 D) Therefore (simplified equaion for Oupu Volage): = D V D (1 D) If V D <<, hen D. More precisely: = ( I av R DS(on) ) D V D (1 D) R L I av where R L is he resisance of he inducor. C IN VIN MOS A6211 SW L given by he following equaion: ON = k (R ON + R INT ) ( / ) f SW = 1 / [ k (R ON + R INT )] where k = 0.0139, wih f SW in MHz, ON in μs, and R ON and R INT (inernal resisance, 5 kω) in kω (see figure 6). Enable and Dimming The IC is acivaed when a logic high signal is applied o he EN (enable) pin. The buck converer ramps up he LED curren o a arge level se by RSENSE. When he EN pin is forced from high o low, he buck converer is urned off, bu he IC remains in sandby mode for up o 10 ms. If EN goes high again wihin his period, he LED curren is urned on immediaely. Acive dimming of he LED is achieved by sending a PWM (pulse-widh modulaion) signal o he EN pin. The resuling LED brighness is proporional o he duy cycle ( T ON / Period ) of he PWM signal. A pracical range for PWM dimming frequency is beween 100 Hz ( Period = 10 ms) and 2 khz. A a 200 Hz PWM frequency, he dimming duy cycle can be varied from 100% down o 1% or lower. If EN is low for more han 17 ms, he IC eners shudown mode o reduce power consumpion. The nex high signal on EN will iniialize a full sarup sequence, which includes a sarup delay of approximaely 130 μs. This sarup delay is no presen during PWM operaion. The EN pin is high-volage oleran and can be direcly conneced o a power supply. However, if EN is higher han he volage V SW 0 V D i L i(max) i av i RIPPLE D i L RSENSE i(min) ON OFF Figure 7. Simplified buck conroller equaions, and reference circui and waveforms T 8
a any ime, a series resisor (1 kω) is required o limi he curren flowing ino he EN pin. This series resisor is no necessary if EN is driven from a logic inpu. PWM Dimming Raio The brighness of he LED sring can be reduced by adjusing he PWM duy cycle a he EN pin as follows: Dimming raio = PWM on-ime / PWM period For example, by selecing a PWM period of 5 ms (200 Hz PWM frequency) and a PWM on-ime of 50 μs, a dimming raio of 1% can be achieved. In an acual applicaion, he minimum dimming raio is deermined by various sysem parameers, including:,, inducance, LED curren, swiching frequency, and PWM frequency. As a general guideline, he minimum PWM on-ime should be kep a 50 μs or longer. A shorer PWM on-ime is accepable under more favorable operaing condiions. Oupu Volage and Duy Cycle Figure 7 provides simplified equaions for approximaing oupu volage. Essenially, he oupu volage of a buck converer is approximaely given as: = D V D1 (1 D ) D, if V D1 << D = ON / ( ON + OFF ) where D is he duy cycle, and V D1 is he forward drop of he Schoky diode D1 (ypically under 0.5 V). Minimum and Maximum Oupu Volages For a given inpu volage, he maximum oupu volage depends on he swiching frequency and minimum OFF. For example, if OFF (min) = 150 ns and f SW = 1 MHz, hen he maximum duy cycle is 85%. So for a 24 V inpu, he maximum oupu is 20.3 V. This means up o 6 LEDs can be operaed in series, assuming V f = 3.3 V or less for each LED. The minimum oupu volage depends on minimum ON and swiching frequency. For example, if he minimum ON = 150 ns and f SW = 1 MHz, hen he minimum duy cycle is 15%. Tha means wih = 24 V, he minimum = 3.2 V (one LED). To a lesser degree, he oupu volage is also affeced by oher facors such as LED curren, on-resisance of he high-side swich, DCR of he inducor, and forward drop of he low-side diode. The more precise equaion is shown in figure 7. As a general rule, swiching a lower frequencies allows a wider range of, and hence more flexible LED configuraions. This is shown in figure 8. Figure 8 shows how he minimum and maximum oupu volages vary wih LED curren (assuming R DS(on) = 0.4 Ω, inducor DCR = 0.1 Ω, and diode V f = 0.6 V). If he required oupu volage is lower han ha permied by he minimum ON, he conroller will auomaically exend he OFF, in order o mainain he correc duy cycle. This means ha he swiching frequency will drop lower when necessary, while he LED curren is kep in regulaion a all imes. VOUT ( V ) 24 22 20 18 (max) (V) 16 14 12 10 8 6 (min) (V) 4 2 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 fsw (MHz) VOUT ( V ) 9 8 7 6 (max) (V) 5 4 3 2 1 (min) (V) 0 0 0.5 1.0 1.5 2.0 2.5 3.0 iled (A) Figure 8. Minimum and Maximum Oupu Volage versus Swiching Frequency ( = 24 V, = 2 A, minimum ON and OFF = 150 ns) Figure 9. Minimum and Maximum Oupu Volage versus curren ( = 9 V, f SW = 1 MHz, minimum ON and OFF = 150 ns) 9
Thermal Budgeing The A6211 is capable of supplying a 3 A curren hrough is high-side swich. However, depending on he duy cycle, he conducion loss in he high-side swich may cause he package o overhea. Therefore care mus be aken o ensure he oal power loss of package is wihin budge. For example, if he maximum emperaure rise allowed is T = 50 K a he device case surface, hen he maximum power dissipaion of he IC is 1.4 W. Assuming he maximum R DS(on) = 0.4 Ω and a duy cycle of 85%, hen he maximum LED curren is limied o 2 A approximaely. A a lower duy cycle, he LED curren can be higher. Faul Handling The A6211 is designed o handle he following fauls: Pin-o-ground shor Pin-o-neighboring pin shor Pin open Exernal componen open or shor Oupu shor o GND The waveform in figure 10 illusraes how he A6211 responds in he case in which he curren sense resisor or he CS pin is shored o GND. Noe ha he SW pin overcurren proecion is ripped a around 3.75 A, and he par shus down immediaely. The par hen goes hrough sarup rery afer approximaely 380 μs of cool-down period. As anoher example, he waveform in figure 11 shows he faul case where exernal Schoky diode D1 is missing or open. As LED curren builds up, a larger-han-normal negaive volage is developed a he SW node during off-ime. This volage rips he missing Schoky deecion funcion of he IC. The IC hen shus down immediaely, and wais for a cool-down period before rery. Componen Selecions The inducor is ofen he mos criical componen in a buck converer. Follow he procedure below o derive he correc parameers for he inducor: 1. Deermine he sauraion curren of he inducor. This can be done by simply adding 20% o he average LED curren: i SAT 1.2. 2. Deermine he ripple curren ampliude (peak-o-peak value). As a general rule, ripple curren should be kep beween 10% and 30% of he average LED curren: 0.1 < i RIPPLE(pk-pk) / < 0.3. 3. Calculae he inducance based on he following equaions: L = ( ) D T / i RIPPLE, and D = ( + V D1 ) / ( + V D1 ), where D is he duy cycle, T is he period 1/ f SW, and V D1 is he forward volage drop of he Schoky diode D1 (see figure 7). C1 V SW C1 V EN Negaive volage developed a SW pin during off-ime C2 V SW C2 Figure 10. A6211 overcurren proecion ripped in he case of a faul caused by he sense resisor pin shored o ground; shows swich node, V SW (ch1, 10 V/div.), oupu volage, (ch2, 10 V/div.), LED curren, (ch3, 1 A/div.), = 100 μs/div. Figure 11. Sarup waveform wih a missing Schoky diode; shows Enable, V EN (ch1, 5 V/div.), swich node, V SW (ch2, 5 V/div.), oupu volage, (ch3, 5 V/div.), LED curren, (ch4, 500 ma/div.), = 100 μs/div. 10
Inducor Selecion Char The char in figure 12 summarizes he relaionship beween LED curren, swiching frequency, and inducor value. Based on his char: Assuming LED curren = 2 A and f SW =1 MHz, hen he minimum inducance required is L = 10 μh in order o keep he ripple curren a 30% or lower. (Noe: = / 2 is he wors case for ripple curren). If he swiching frequency is lower, hen eiher a larger inducance mus be used, or he ripple curren requiremen has o be relaxed. Addiional Noes on Ripple Curren For sabiliy, pick he inducor and swiching frequency o ensure he lowes inducor ripple curren percenage is a leas 12.5% during wors case (a he lowes ). There is no hard limi on he highes ripple curren percenage allowed. A 60% ripple curren is sill accepable, as long as boh he inducor and LEDs can handle he peak curren (average curren 1.3 in his case). However, care mus be aken o ensure he valley of he inducor ripple curren never drops o zero a he highes inpu volage (which implies a 200% ripple curren). In general, allowing a higher ripple curren percenage enables lower-inducance inducors o be used, which resuls in smaller size and lower cos. The only down-side is he core loss of he inducor increases wih larger ripple currens. Bu his is ypically a small facor. If lower ripple curren is required for he LED sring, one soluion is o add a small capacior (such as 2.2 μf) across he LED Swiching Frequency, f SW (MHz) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 L=47 μh L=15 μh L=22 μh L=33 μh L=10 μh 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 LED Curren, I LED (A) Figure 12. Inducance selecion based on I LED and f SW ; = 24 V, = 12 V, ripple curren = 30% SW L1 LED+ I ripple SW L1 LED+ I ripple D1 D1... C1... CS CS V ripple LED V ripple LED R SENSE R SENSE Wihou oupu capacior: Ripple curren hrough LED sring is proporional o ripple volage a CS pin. Wih a small capacior across LED sring: Ripple curren hrough LED sring is reduced, while ripple volage a CS pin remains high. Figure 13. Ripple curren and volage, wih and wihou shun capacior 11
sring from LED+ o LED. In his case, he inducor ripple curren remains high while he LED ripple curren is grealy reduced. Oupu Filer Capacior The A6211 is designed o operae wihou an oupu filer capacior, in order o save cos. Adding a large oupu capacior is no recommended. In some applicaions, i may be required o add a small filer capacior (up o several μf) across he LED sring (beween LED+ and LED-) o reduce oupu ripple volage and curren. I is imporan o noe ha: The effeciveness of his filer capacior depends on many facors, such as: swiching frequency, inducors used, PCB layou, LED volage and curren, and so forh. The addiion of his filer capacior inroduces a longer delay in LED curren during PWM dimming operaion. Therefore he maximum PWM dimming raio is reduced. The filer capacior should NOT be conneced beween LED+ and GND. Doing so may creae insabiliy because he conrol loop mus deec a cerain amoun of ripple curren a he CS pin for regulaion. C1,C2 C1,C2 V EN V EN Panel 14A. Operaion wihou using any oupu capacior across he LED sring Panel 14B. Operaion wih a 0.68 μf ceramic capacior conneced across he LED sring Figure 14. Waveforms showing he effecs of adding a small filer capacior across he LED sring Operaing condiions: a 200 Hz, = 24 V, = 15 V, f SW = 500 khz, L = 10 μh, duy cycle = 50% CH1 (Red) = (10 V/div), CH2 (Blue) = (10 V/div), CH3 (Green) = (500 ma/div), CH4 (Yellow) = Enable (5 V/div), ime scale = 1 ms/div 12
Applicaion Circui The applicaion circui in figure 15 shows a design for driving a 15 V LED sring a 1.3 A (se by R SENSE ). The swiching frequency is 500 khz, as se by R1. A 0.68 μf ceramic capacior is added across he LED sring o reduce he ripple curren hrough he LEDs (as shown in figure 14B). = 24 o 48 V GND EN C1 47 μf 50 V C2 4.7uF 50V R1 140 kω 1 2 3 4 VIN TON EN CS A6211 SW BOOT GND PAD VCC 8 7 6 5 0.1 μf L1 10 μh / 2 A D1 60 V / 2 A 0.68 μf 50 V LED+... LED sring ( 15 V) C5 0.1 μf LED R SENSE 0.15 Ω Figure 15. Applicaion circui diagram Suggesed Componens Symbol Par Number Manufacurer C1 EMZA500ADA470MF80G Unied Chemi-Con C2 UMK316BJ475KL-T Taiyo Yuden L1 NR8040T100M Taiyo Yuden D1 B250A-13-F Diodes, Inc. R SENSE RL1632R-R150-F Susumu 13
Componen Placemen and PCB Layou Guidelines PCB layou is criical in designing any swiching regulaor. A good layou reduces emied noise from he swiching device, and ensures beer hermal performance and higher efficiency. The following guidelines help o obain a high qualiy PCB layou. Figure 16 shows an example for componens placemen. Figure 17 shows he hree criical curren loops ha should be minimized and conneced by relaively wide races. 1) When he upper FET (inegraed inside he A6211) is on, curren flows from he inpu supply/capaciors, hrough he upper FET, ino he load via he oupu inducor, and back o ground as shown in loop 1. This loop should have relaively wide races. Ideally his connecion is made on boh he op (componen) layer and via he ground plane. 2) When he upper FET is off, free-wheeling curren flows from ground hrough he asynchronous diode D1, ino he load via he oupu inducor, and back o ground as shown in loop 2. This loop should also be minimized and have relaively wide races. Ideally his connecion is made on boh he op (componen) layer and via he ground plane. 3) The highes di/d occurs a he insan he upper FET urns on and he asynchronous diode D1 undergoes reverse recovery as shown in loop 3. The ceramic inpu capaciors C2 mus deliver his high insananeous curren. C1 (elecrolyic capacior) should no be oo far off C2. Therefore, he loop from he ceramic inpu capacior hrough he upper FET and asynchronous diode o ground should be minimized. Ideally his connecion is made on boh he op (componen) layer and via he ground plane. 4) The volage on he SW node (pin 8) ransiions from 0 V o very quickly and may cause noise issues. I is bes o place he asynchronous diode and oupu inducor close o he A6211 o minimize he size of he SW polygon. Keep sensiive analog signals (CS, and R1 of swiching frequency seing) away from he SW polygon. 6) For accurae curren sensing, he LED curren sense resisor R SENSE should be placed close o he IC. 7) Place he boo srap capacior near he BOOT node (pin 7) and keep he rouing o his capacior shor. 8) When rouing he inpu and oupu capaciors (C1, C2, and if used), use muliple vias o he ground plane and place he vias as close as possible o he A6211 pads. 9) To minimize PCB losses and improve sysem efficiency, he inpu (VIN) and oupu (VOUT) races should be wide and duplicaed on muliple layers, if possible. Loop 1 Loop 3 SW Loop 2 L1 C IN D1 C OUT LED Figure 16. Example layou for he A6211 evaluaion board Figure 17. Three differen curren loops in a buck converer 14
10) Connecion o he LED array should be kep shor. Excessively long wires can cause ringing or oscillaion. When he LED array is separaed from he converer board and an oupu capacior is used, he capacior should be placed on he converer board o reduce he effec of sray inducance from long wires. Thermal Dissipaion The amoun of hea ha can pass from he silicon of he A6211 o he surrounding ambien environmen depends on he hermal resisance of he srucures conneced o he A6211. The hermal resisance, R θja, is a measure of he emperaure rise creaed by power dissipaion and is usually measured in degrees Celsius per wa ( C/W). The emperaure rise, ΔT, is calculaed from he power dissipaed, P D, and he hermal resisance, R θja, as: ΔT = P D R θja A hermal resisance from silicon o ambien, R θja, of approximaely 35 C/W can be achieved by mouning he A6211 on a sandard FR4 double-sided prined circui board (PCB) wih a copper area of a few square inches on each side of he board under he A6211. Addiional improvemens in he range of 20% may be achieved by opimizing he PCB design. Opimizing Thermal Layou The feaures of he prined circui board, including hea conducion and adjacen hermal sources such as oher componens, have a very significan effec on he hermal performance of he device. To opimize hermal performance, he following should be aken ino accoun: The device exposed hermal pad should be conneced o as much copper area as is available. Copper hickness should be as high as possible (for example, 2 oz. or greaer for higher power applicaions). The greaer he quaniy of hermal vias, he beer he dissipaion. If he expense of vias is a concern, sudies have shown ha concenraing he vias direcly under he device in a igh paern, as shown in figure 18, has he greaes effec. Addiional exposed copper area on he opposie side of he board should be conneced by means of he hermal vias. The copper should cover as much area as possible. Oher hermal sources should be placed as remoe from he device as possible Place as many vias as possible o he ground plane around he anode of he asynchronous diode. Signal races LJ package fooprin 0.7 mm 0.7 mm LJ package exposed hermal pad Top-layer exposed copper Ø0.3 mm via Figure 18. Suggesed PCB layou for hermal opimizaion (maximum available boom-layer copper recommended) 15
Package LJ, 8-Pin Narrow SOIC wih Exposed Thermal Pad 8 4.90 ±0.10 8 0 0.65 8 1.27 0.25 0.17 1.75 2.41 NOM A B 3.90 ±0.10 6.00 ±0.20 1.04 REF 2.41 5.60 8X 0.10 C 1 2 3.30 NOM Branded Face SEATING PLANE 1.70 MAX 0.51 0.31 0.15 0.00 1.27 BSC C SEATING PLANE GAUGE PLANE A Terminal #1 mark area B 1.27 0.40 0.25 BSC C 1 2 3.30 PCB Layou Reference View For Reference Only; no for ooling use (reference MS-012BA) Dimensions in millimeers Dimensions exclusive of mold flash, gae burrs, and dambar prorusions Exac case and lead configuraion a supplier discreion wihin limis shown Exposed hermal pad (boom surface); dimensions may vary wih device C Reference land paern layou (reference IPC7351 SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all adjacen pads; adjus as necessary o mee applicaion process requiremens and PCB layou olerances; when mouning on a mulilayer PCB, hermal vias a he exposed hermal pad land can improve hermal dissipaion (reference EIA/JEDEC Sandard JESD51-5) 16
Revision Hisory Revision Revision Dae Descripion of Revision Rev. 1 Ocober 21, 2013 Updae applicaions informaion Copyrigh 2010-2013, reserves he righ o make, from ime o ime, such de par ures from he deail spec i fi ca ions as may be required o permi improvemens in he per for mance, reliabiliy, or manufacurabiliy of is producs. Before placing an order, he user is cauioned o verify ha he informaion being relied upon is curren. Allegro s producs are no o be used in any devices or sysems, including bu no limied o life suppor devices or sysems, in which a failure of Allegro s produc can reasonably be expeced o cause bodily harm. The in for ma ion in clud ed herein is believed o be ac cu rae and reliable. How ev er, assumes no responsibiliy for is use; nor for any in fringe men of paens or oher righs of hird paries which may resul from is use. For he laes version of his documen, visi our websie: www.allegromicro.com 17