Daashee, Version 2.0, July 2009 ISOFACE TM Coreless Transformer Isolaed Digial Oupu 8 Channel 1.2A High-Side Swich Power Managemen & Drives N e v e r s o p h i n k i n g.
Revision Hisory: 2009-07-28 Version 2.0 Previous Version: V1.0 V2.0 Final Daashee Ediion 2009-07-28 Published by Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg, Germany Infineon Technologies AG 2009. All Righs Reserved. Aenion please! The informaion herein is given o describe cerain componens and shall no be considered as a guaranee of characerisics. Terms of delivery and righs o echnical change reserved. We hereby disclaim any and all warranies, including bu no limied o warranies of non-infringemen, regarding circuis, descripions and chars saed herein. Informaion For furher informaion on echnology, delivery erms and condiions and prices please conac your neares Infineon Technologies Office (www.infineon.com). Warnings Due o echnical requiremens componens may conain dangerous subsances. For informaion on he ypes in quesion please conac your neares Infineon Technologies Office. Infineon Technologies Componens may only be used in life-suppor devices or sysems wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem, or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body, or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.
Coreless Transformer Isolaed Digial Oupu 8 Channel 1.2A High-Side Swich Produc Highlighs Coreless ransformer isolaed daa inerface Galvanic isolaion 8 High-side oupu swiches 1,2A µc compaible 8-bi parallel peripheral Isolaed reurn pah for DIAG signal Feaures Inerface 3.3/5V CMOS operaion compaible Parallel inerface Direc conrol mode High common mode ransien immuniy Shor circui proecion Maximum curren inernally limied Overload proecion Overvolage proecion (including load dump) Undervolage shudown wih auoresar and hyseresis Swiching inducive loads Common oupu disable pin Thermal shudown wih resar Thermal independence of separae channels Common diagnosic oupu for overemperaure ESD proecion Loss of GNDbb and loss of V bb proecion Reverse Oupu Volage proecion RoHS complian Typical Applicaion Isolaed swich for indusrial applicaions (PLC) All ypes of resisive, inducive and capaciive loads µc compaible power swich for 24V DC applicaions Driver for solenoid, relays and resisive loads Descripion The is a galvanically isolaed 8 bi daa inerface in PG-DSO-36 package ha provides 8 fully proeced high-side power swiches ha are able o handle currens up o 1.2A. An 8 bi parallel µc compaible inerface allows o connec he IC direcly o a µc sysem. The inpu inerface suppors also a direc conrol mode and is designed o operae wih 3.3/5V CMOS compaible levels. The daa ransfer from inpu o oupu side is realized by he inegraed Coreless Transformer Technology. Typical Applicaion VCC VCC Vbb Vbb VCCP1.x AD0 WR P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 DIS CS WR D0 D1 D2 D3 D4 D5 D6 D7 Conrol Uni Parallel Inerface CT DIAG Conrol & Proecio n Uni OUT0 OUT1 µc (i.e C166) DIAG OUT7 GND GNDCC GNDbb Type On-sae Resisance Package 200mΩ PG-DSO-36 Daashee 3 Version 2.0, 2009-07-28
Pin Configuraion and Funcionaliy 1 Pin Configuraion and Funcionaliy 1.1 Pin Configuraion Vbb Pin Symbol Funcion 1 N.C. No conneced N.C. VCC 1 2 TAB 36 35 OUT0 OUT0 2 VCC Posiive 3.3/5V logic supply 3 DIS Oupu disable 4 CS Chip selec 5 WR Parallel wrie 6 D0 Daa inpu bi0 7 D1 Daa inpu bi1 8 D2 Daa inpu bi2 9 D3 Daa inpu bi3 10 D4 Daa inpu bi4 DIS 3 CS 4 WR 5 D0 6 D1 7 D2 8 D3 9 D4 10 D5 11 D6 12 34 33 32 31 30 29 28 27 26 25 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 OUT5 OUT5 11 D5 Daa inpu bi5 12 D6 Daa inpu bi6 13 D7 Daa inpu bi7 14 DIAG Common diagnosic oupu for overemperaure 15 GNDCC Inpu logic ground D7 13 DIAG 14 GNDCC 15 N.C. 16 N.C. N.C. 17 18 TAB 24 23 22 21 20 19 OUT6 OUT6 OUT7 OUT7 N.C. GNDbb 16 N.C. No conneced Vbb 17 N.C. No conneced Figure 1 Power SO-36 (430mil) 18 N.C. No conneced. 19 GNDbb Oupu driver ground 20 N.C No conneced 21 OUT7 High-side oupu of channel 7 22 OUT7 High-side oupu of channel 7 23 OUT6 High-side oupu of channel 6 24 OUT6 High-side oupu of channel 6 25 OUT5 High-side oupu of channel 5 26 OUT5 High-side oupu of channel 5 27 OUT4 High-side oupu of channel 4 28 OUT4 High-side oupu of channel 4 29 OUT3 High-side oupu of channel 3 30 OUT3 High-side oupu of channel 3 31 OUT2 High-side oupu of channel 2 32 OUT2 High-side oupu of channel 2 33 OUT1 High-side oupu of channel 1 34 OUT1 High-side oupu of channel 1 35 OUT0 High-side oupu of channel 0 36 OUT0 High-side oupu of channel 0 TAB Vbb Posiive driver power supply volage Daashee 4 Version 2.0, 2009-07-28
Pin Configuraion and Funcionaliy 1.2 Pin Funcionaliy VCC (Posiive 3.3/5V logic supply) The VCC supplies he inpu inerface ha is galvanically isolaed from he oupu driver sage. The inpu inerface can be supplied wih 3.3/5V. DIS (Oupu disable) The high-side oupus OUT0...OUT7 can be immediaely swiched off by means of he low acive pin DIS ha is an asynchronous signal. The inpu regisers are also rese by he DIS signal. The Oupu remains swiched off afer low-high ransiion of DIS signal, ill new informaion is wrien ino he inpu regiser. Curren Sink o GNDCC. driver ha is supplied by Vbb. OUT0... OUT7 (High side oupu channel 0... 7) The oupu high side channels are inernally conneced o Vbb and conrolled by he corresponding daa inpu pins D0... D7 in parallel mode. TAB (Vbb, Posiive supply for oupu driver) The heaslug is conneced o he posiive supply por of he oupu inerface. CS (Chip selec) The sysem microconroller selecs he by means of he low acive pin CS o acivae he parallel inerface. By connecing he CS pin and WR pin o ground he parallel direc conrol is acivaed. Curren Source o VCC. WR (Parallel wrie) In parallel mode daa a he inpu pins (D0... D7) are lached by means of he rising edge of he low acive signal WR (wrie). Curren Source o VCC. D0... D7 (Daa inpu bi0... bi7) The presen daa can be lached on he rising edge of he wrie signal WR. D0... D7 conrol he corresponding oupu channels OUT0...OUT7. By connecing CS and WR o ground, he signals a D0... D7 direcly conrol he oupus. Curren Sink o GNDCC. DIAG (Common diagnosic oupu for overemperaure) The low acive DIAG signal conains he OR-wired informaion of he separaed overemperaure deecion unis for each channel.the oupu pin DIAG provides an open drain funcionaliy. A curren source is also conneced o he pin DIAG. In normal operaion he signal DIAG is high. When overemperaure or Vbb below ON-Limi is deeced he signal DIAG changes o low. GNDCC (Ground for VCC domain) This pin acs as he ground reference for he inpu inerface ha is supplied by VCC. GNDbb (Oupu driver ground domain) This pin acs as he ground reference for he oupu Daashee 5 Version 2.0, 2009-07-28
Blockdiagram 2 Blockdiagram CS WR D0 D1 D2 D3 D4 D5 D6 D7 Undervolage Shudown wih Resar < D0 - D7 > Parallel Inpu Inerface Logic Serial o Parallel Undervolage Shudown wih Resar o Logic Channel 1-6 Logic Charge Pump Level shifer Recifier High-side Channel 0 o Logic Channel 1-6 Common Diagnosic Oupu Logic Charge Pump Level Shifer Recifier High-side Channel 7 Volage Source Overvolage Proecion Limiaion of Unclamped Inducive Load Curren Limiaion Overload Proecion Temperaure Sensor from Temperaure Sensor Channel 1-6 Channel 1... 6 Limiaion of Unclamped Inducive Load Curren Limiaion Overload Proecion Temperaure Sensor Vbb Vbb GNDbb OUT0 OUT7 Galvanic Isolaion VCC GNDCC DIS DIAG Parallel o Serial Direc Mode Conrol VCC 100µA CT Gae Proecion Gae Proecion OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 Figure 2 Blockdiagram Daashee 6 Version 2.0, 2009-07-28
Funcional Descripion 3 Funcional Descripion 3.1 Inroducion The ISOFACE includes 8 high-side power swiches ha are conrolled by means of he inegraed parallel inerface. The inerface is 8bi µc compaible. Furhermore a direc conrol mode can be seleced ha allows he direc conrol of he oupus OUT0...OUT7 by means of he inpus D0...D7 wihou any addiional logic signal. The IC can replace 8 opocouplers and he 8 high-side swiches in convenional I/O-Applicaions as a galvanic isolaion is implemened by means of he inegraed coreless ransformer echnology. The µc compaible inerfaces allow a direc connecion o he pors of a microconroller wihou he need for oher componens. Each of he 8 high-side power swiches is proeced agains shor o Vbb, overload, overemperaure and agains overvolage by an acive zener clamp. The diagnosic logic on he power chip recognizes he overemperaure informaion of each power ransisor The informaion is send via he inernal coreless ransformer o he pin DIAG a he inpu inerface. 3.2 Power Supply The IC conains 2 galvanic isolaed volage domains ha are independen from each oher. The inpu inerface is supplied a VCC and he oupu sage is supplied a Vbb. The differen volage domains can be swiched on a differen ime. The oupu sage is only enabled once he inpu sage eners a sable sae. 3.3 Oupu Sage Each channel conains a high-side verical power FET ha is proeced by embedded proecion funcions. The coninuous curren for each channel is 1.2A (all channels ON). 3.3.1 Oupu Sage Conrol Each oupu is independenly conrolled by an oupu lach and a common rese line via he pin DIS ha disables all eigh oupus and rese he laches. The parallel inpu daa is ransferred o he inpu laches wih a high-o-low ransiion of he signal WR (wrie) while he CS is logic low. A low-o-high ransiion of CS ransfers hen he daa of he inpu laches o he oupu buffer. 3.3.2 Power Transisor Overvolage Proecion Each of he eigh oupu sages has i own zener clamp ha causes a volage limiaion a he power ransisor when solenoid loads are swiched off. V ON is hen clamped o 47V (min.). Figure 3 Vz GNDbb Vbb OUTx V ON Vbb Inducive and overvolage oupu clamp (each channel) Energy is sored in he load inducance during an inducive load swich-off. 2 E L = 1 2 L I L Figure 4 V bb Dx E bb Vbb OUTx GNDbb E AS Z L L R L E Load Inducive load swich-off energy dissipaion (each channel) While demagneizing he load inducance, he energy dissipaion in he DMOS is E AS = E bb + E L E R = V ON( CL) i L ()d wih an approximae soluion for R L > 0Ω: I L L I E AS --------------- ( V 2 R bb + V ON( CL) ) 1 L R = ln + ------------------------ L L E L E R V ON( CL) 3.3.3 Power Transisor Overcurren Proecion The oupus are provided wih a curren limiaion ha eners a repeiive swiched mode afer an iniial peak Daashee 7 Version 2.0, 2009-07-28
Funcional Descripion curren has been exceeded. The iniial peak shor circui curren limi is se o I L(SCp). During he repeiive mode shor circui curren he limi is se o I L(SCr). If his operaion leads o an overemperaure condiion, a second proecion level (T j > 135 C) will change he oupu ino a low duy cycle PWM (selecive hermal shudown wih resar) o preven criical chip emperaures. IN IN VOUT I L Normal operaion Oupu shor o GND I L(SCp) IL(SCr) VOUT DIAG T J DIAG Figure 7 Shor circui in on-sae, shu down down by overemperaure, resar by cooling Figure 5 Overemperaure deecion The following figures show he iming for a urn on ino shor circui and a shor circui in on-sae. Heaing up of he chip may require several milliseconds, depending on exernal condiions. IN VOUT 3.4 Common Diagnosic Oupu The overemperaure deecion informaion are ORwired in he common diagnosic oupu block. The informaion is send via he inegraed coreless ransformer o he inpu inerface. The oupu sage a pin DIAG has an open drain funcionaliy combined wih a curren source. DIAG VCC 100µA CT Common Diagnosic Oupu Oupu shor o GND I L I L(SCp) IL(SCr) Figure 8 Common diagnosic oupu DIAG Figure 6 Turn on ino shor circui, shu down by overemperaure, resar by cooling Daashee 8 Version 2.0, 2009-07-28
Funcional Descripion 3.5 Parallel Inerface 3.5.2 uc Conrol Mode The conains a parallel inerface ha can be direcly conrolled by he microconroller oupu pors. The parallel inerface can also be swiched over o a direc conrol ha allows direc changes of he oupus OUT0... OUT7 by means of he corresponding inpus D0... D7 wihou addiional logic signals. To acivae he parallel direc conrol mode pin CS and pin WR have o be conneced boh o ground. 3.5.1 Parallel Inerface Signal Descripion AD0 WR P0 P1 P2 P3 P4 P5 P6 P7 CS WR D0 D1 D2 D3 D4 D5 D6 D7 Oupu lines CS - Chip selec. The sysem microconroller selecs he by means of he CS pin. Whenever he pin is in a logic low sae, daa can be ransferred from he µc. CS High o low ransiion: µc (i.e C166) IC1 DIAG Parallel Inerface Parallel inpu daa can be wrien in from hen on CS Low o high ransiion: Figure 9 Number of adressed ICs = n Number of necessary conrol and daa pors = 9 n Individual ICs are adressed by he chip selec Parallel bus configuraion The daa in he inpu laches is ransferred o he oupu buffer WR - Wrie. The sysem conroller enables he wrie procedure in he by means of he signal WR. A logic low sae signal a pin WR wries he inpu daa ino he inpu laches when he CS pin is in a logic low sae. WR Logic low level: 3.5.3 Direc Conrol Mode Beside he use of he parallel µc compaible inerface a parallel direc conrol mode can be choosen. In his mode he oupu OUT0...OUT7 can be direcly conrolled via he inpus D0...D7 wihou he need for addiional logic signals. To acivae his mode pin CS and WR need o be conneced o ground.. VCC Parallel inpu daa a he pins D0 - D7 is wrien ino he inpu laches WR Logic high level: The parallel inpu daa is lached in he inpu laches. Any changes a he pins D0 - D7 afer he low-o-high ransiion of WR do no affec he inpu laches. D0... D7 - Parallel inpu. Parallel daa bis are fed ino he pins D0... D7. The daa is wrien ino he inpu laches when WR is logic low. Conroller VCC P0 P1 P2 P3 P4 P5 P6 P7 VCC CS WR D0 D1 D2 D3 D4 D5 D6 D7 DIAG Parallel Inerface IC1 Oupu lines Figure 10 Parallel Direc Conrol Daashee 9 Version 2.0, 2009-07-28
Funcional Descripion 3.6 Parallel Inerface Timing CS CSWR WHCS CSD WR WRPW DS DH DATA D0 - D7 on/off OUTPUT OUT0 - OUT7 Figure 11 Parallel inpu - oupu iming diagram 3.7 Transmission Failure Deecion There is a failure deecion uni inegraed o ensure also a sable funcionaliy during he inegraed coreless ransformer ransmission. This uni decides weher he ransmied daa is valid or no. If four imes serial daa coming in from he inernal regisers is no acceped, he oupu sages are swiched off unil he nex valid daa is received. Daashee 10 Version 2.0, 2009-07-28
4 Elecrical Characerisics Elecrical Characerisics Noe: All volages a pins 2 o 14 are measured wih respec o ground GNDCC (pin 15). All volages a pin 20 o pin 36 and TAB are measured wih respec o ground GNDbb (pin 19). The volage levels are valid if oher raings are no violaed. The wo volage domains V CC and V bb are inernally galvanic isolaed. 4.1 Absolue Maximum Raings Noe: Absolue maximum raings are defined as raings, which when being exceeded may lead o desrucion of he inegraed circui. For he same reason make sure, ha any capacior ha will be conneced o pin 2 (VCC) and TAB (Vbb) is discharged before assembling he applicaion circui. Supply volages higher han V bb(az) require an exernal curren limi for he GNDbb pin, e.g. wih a 15Ω resisor in GNDbb connecion. Operaing a absolue maximum raings can lead o a reduced lifeime. Parameer Symbol Limi Values Uni a T j = -40... 135 C, unless oherwise specified min. max. Supply volage inpu inerface (VCC) V CC -0.5 6.5 V Supply volage oupu inerface (Vbb) V bb -1 1) 45 Coninuos volage a daa inpus (D0... D7) V Dx -0.5 6.5 Coninuos volage a pin CS V CS -0.5 6.5 Coninuos volage a pin WR V WR -0.5 6.5 Coninuos volage a pin DIS V DIS -0.5 6.5 Coninuos volage a pin DIAG V DIAG -0.5 6.5 Load curren (shor-circui curren) I L self limied A Reverse curren hrough GNDbb 1) I GNDbb -1.6 Operaing Temperaure T j -25 inernal limied C Sorage Temperaure T sg -50 150 2) Power Dissipaion P o 3.3 W Inducive load swich-off energy dissipaion single E AS J pulse, T j = 125 C, I L = 1.2A one channel acive 5 all channel simulaneously acive (each channel) 0.5 Load dump proecion 3) V loaddump =V A + V S V Loaddump V V IN = low or high d = 400ms, R I = 2Ω, R L = 27Ω, V A = 13.5V d = 350ms, R I = 2Ω, R L = 57Ω, V A = 27V V V Elecrosaic discharge volage (Human Body Model) kv according o JESD22-A114-B ESD 2 Elecrosaic discharge volage (Charge Device Model) kv according o ESD STM5.3.1-1999 ESD 1 Coninuos reverse drain curren 1)3), each channel I S 4 A 1) defined by P o 2) Device on 50mm*50mm*1.5mm epoxy PCB FR4 wih 6cm² (one layer, 70µm hick) copper area for drain connecion. PCB is verical wihou blown air. 3) no subjec o producion es, specified by design 4) V Loaddump is seup wihou he DUT conneced o he generaor per ISO7637-1 and DIN40839 90 117 Daashee 11 Version 2.0, 2009-07-28
Elecrical Characerisics 4.2 Thermal Characerisics Parameer a T j = -25... 125 C, V bb =15...30V, V CC =3.0...5.5V, unless oherwise specified Symbol Limi Values Uni Tes Condiion min. yp. max. Thermal resisance juncion - case R hjc 1.5 K/W Thermal resisance @ min. fooprin R h(ja) 50 Thermal resisance @ 6cm² cooling area 1) R h(ja) 38 1) Device on 50mm*50mm*1.5mm epoxy PCB FR4 wih 6cm² (one layer, 70µm hick) copper area for drain connecion. PCB is verical wihou blown air. 4.3 Load Swiching Capabiliies and Characerisics Parameer a T j = -25... 125 C, V bb =15...30V, V CC =3.0...5.5V, unless oherwise specified On-sae resisance, I L = 0.5A, each channel T j = 25 C T j = 125 C wo parallel channels, T j = 25 C: 1) four parallel channels, T j = 25 C: 1) Nominal load curren Device on PCB 38K/W, T a = 85 C, T j < 125 C 1) one channel: wo parallel channels: 1) four parallel channels: 1) Turn-on ime o 90% V R L = 47Ω, V Dx = 0 o 5V OUT 2) Turn-off ime o 10% V OUT 2) R L = 47Ω, V Dx = 5 o 0V Slew rae on 10 o 30% V OUT R L = 47Ω, V bb = 15V Slew rae off 70 o 40% V OUT R L = 47Ω, V bb = 15V 1) no subjec o producion es, specified by design Symbol Limi Values Uni Tes Condiion min. yp. max. R ON 150 270 75 38 I L(NOM) 1.4 2.2 4.4 2) The urn-on and urn-off ime includes he swiching ime of he high-side swich and he ransmission ime via he coreless ransformer in normal operaing mode. During a failure on he coreless ransformer ransmission urn-on or urn-off ime can increase by up o 50µs. 200 320 100 50 mω on 64 120 µs off 89 170 dv/d on 1 2 V/µs -dv/d off 1 2 A 4.4 Operaing Parameers Parameer a T j = -25... 125 C, V bb =15...30V, V CC =3.0...5.5V, unless oherwise specified Symbol Limi Values Uni Tes Condiion min. yp. max. Common mode ransien immuniy 1) V ISO /d -25-25 kv/µs V ISO = 200V Magneic field immuniy 1) H IM 100 A/m IEC61000-4-8 Daashee 12 Version 2.0, 2009-07-28
Elecrical Characerisics Volage domain V bb (Oupu inerface) Volage domain V CC (Inpu inerface) Operaing volage V bb 11 35 V Undervolage shudown V bb(under) 7 10.5 Undervolage resar V bb(u_rs) 11 Undervolage hyseresis V bb(under) 0.5 Undervolage curren I bb(uvlo) 1 2.5 ma V bb < 7V Operaing curren I GNDL 10 14 ma All Channels ON - no load Leakage oupu curren (included in I bb(off) ) V Dx = low, each channel I L(off) 5 30 µa Operaing volage V CC 3.0 5.5 V Undervolage shudown V CC(under) 2.5 2.9 Undervolage resar V CC(u_rs) 3 Undervolage hyseresis V CC(under) 0.1 Undervolage curren I CC(uvlo) 1 2 ma V cc < 2.5V Operaing curren I CC(on) 4.5 6 ma 1) no subjec o producion es Daashee 13 Version 2.0, 2009-07-28
Elecrical Characerisics 4.5 Oupu Proecion Funcions 1) Parameer a T j = -25... 125 C, V bb =15...30V, V CC =3.0...5.5V, unless oherwise specified Iniial peak shor circui curren limi, each channel T j = -25 C, V bb = 30V, m = 700µs T j = 25 C T j = 125 C wo parallel channels: 3) four parallel channels: 3) Repeiive shor circui curren limi 3) T j = T j (see iming diagrams) each channel: wo parallel channels: 3) four parallel channels: 3) Symbol Limi Values Uni Tes Condiion I L(SCp) I L(SCr) min. yp. max. 1) Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninous repeiive operaion. 1.4 3.0 4.5 wice he curren of one channel four imes he curren of one channel Oupu clamp (inducive load swich off) V ON(CL) 47 53 60 V a V OUT = V bb - V ON(CL) Overvolage proecion V bb(az) 47 Thermal overload rip emperaure 2)3) 2) Higher operaing emperaure a normal funcion for each channel available 3) no subjec o producion es, specified by design 2.2 2.2 2.2 T j 135 C Thermal hyseresis 3) T j 10 K A 4.6 Diagnosic Characerisics a pin DIAG Parameer a T j = -25... 125 C, V bb =15...30V, V CC =3.0...5.5V, unless oherwise specified Common diagnosic sink curren (overemperaure of any channel) T j = 135 C Symbol Limi Values Uni Tes Condiion min. yp. max. I diagsink 5 ma V diagon < 0.25xVCC Common diagnosic source curren I diagsource 100 µa Daashee 14 Version 2.0, 2009-07-28
Elecrical Characerisics 4.7 Inpu Inerface Parameer a T j = -25... 125 C, V bb =15...30V, V CC =3.0...5.5V, unless oherwise specified Inpu low sae volage (D0... D7, DIS, CS, WR) Inpu high sae volage (D0... D7, DIS, CS, WR) Inpu volage hyseresis (D0... D7, DIS, CS, WR) Inpu pull down curren (D0... D7, DIS) Inpu pull up curren (CS, WR) Oupu disable ime (ransiion DIS o logic low) 1)2) Normal operaion Turn-off ime o 10% V OUT R L = 47Ω Oupu disable ime (ransiion DIS o logic low) Disurbed operaion Turn-off ime o 10% V OUT R L = 47Ω 1)2)3) Symbol Limi Values Uni Tes Condiion min. yp. max. V IL -0.3 0.3 x V CC V IH 0.7 x V CC + V CC 0.3 V IHys 100 mv I Idown 100 µa -I Iup 100 DIS --- 85 170 µs DIS --- --- 230 1) The ime includes he urn-on/off ime of he high-side swich and he ransmission ime via he coreless ransformer. 2) If Pin DIS is se o low he oupus are se o low; afer DIS se o high a new wrie cycle is necessary o se he oupu again. 3) The parameer is no subjec o producion es - verified by design/characerizaion V 4.8 Parallel Inerface Inpu Timing Parameer a T j = -25... 125 C, V bb =15...30V, V CC =3.0...5.5V, unless oherwise specified Symbol Limi Values Uni Tes Condiion min. yp. max. WR pulse widh WRPW 20 ns Daa seup ime before WR DS 20 Daa hold ime afer WR DH 10 Chip selec valid o WR CSWR 0 WR logic high o CS logic high WHCS 10 Delay o nex CS cycle CSD 10 Daashee 15 Version 2.0, 2009-07-28
Elecrical Characerisics 4.9 Reverse Volage Parameer a T j = -25... 125 C, V bb =15...30V, V CC =3.0...5.5V, unless oherwise specified Reverse volage R GND = 0 Ω R GND = 150 Ω 1)2) Diode forward on volage IF = 1.25A, V Dx = low, each channel Symbol Limi Values Uni Tes Condiion min. yp. max. -V bb 1 45 -V ON 1.2 V 1) defined by P o 2) no subjec o producion es, specified by design 4.10 Isolaion and Safey-Relaed Specificaion Parameer Value Uni Condiions Measured from inpu erminals o oupu erminals, unless oherwise specified Raed dielecric isolaion volage V ISO 500 V AC 1) 1 - minue duraion Shor erm emporary overvolage 1250 V 5s acc. DIN EN60664-1 1) Minimum exernal air gap (clearance) 2.6 mm shores disance hrough air. Minimum exernal racking (creepage) 2.6 mm shores disance pah along body. Minimum Inernal Gap 0.01 mm Insulaion disance hrough insulaion 1) The parameer is no subjec o producion es, verified by characerizaion; Producion Tes wih 1100V, 100ms duraion 4.11 Reliabiliy For Qualificaion Repor please conac your local Infineon Technologies office! Daashee 16 Version 2.0, 2009-07-28
Elecrical Characerisics Daashee 17 Version 2.0, 2009-07-28
Elecrical Characerisics Daashee 18 Version 2.0, 2009-07-28
Package Oulines 5 Package Oulines PG-DSO-36 (Plasic Dual Small Ouline Package) 1.1 ±0.1 +0.1 0 ±0.1 3.25 3.5 MAX. 11 ±0.15 1) 2.8 B +0.07-0.02 0.25 ±3 5 0.25 0.65 +0.13 15.74 ±0.1 (Heaslug) 36x 0.25 M 0.1 C ABC 1.3 6.3 (Mold) 14.2 ±0.3 Heaslug 0.95 ±0.15 0.25 B Boom View Index Marking 36 19 19 36 3.2 ±0.1 (Meal) 5.9 ±0.1 (Meal) 1 x 45 1 18 15.9 ±0.1 (Mold) 1) A 10 1 13.7-0.2 (Meal) Heaslug Figure 12 PG-DSO-36 1) Does no include plasic or meal prorusion of 0.15 max. per side gps09181_1 Daashee 19 Version 2.0, 2009-07-28
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