FEATURES Member of the Texas Instruments Widebus Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes Operates From 1.65 V to 3.6 V Max t pd of 4.4 ns at 3.3 V ±12-mA Output Drive at 3.3 V Outputs Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 ma Per JESD 17 ESD Protection Exceeds JESD 22-2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) DESCRIPTION/ORDERING INFORMATION This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V V CC operation. The SN74ALVCHR16601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123I SEPTEMBER 1997 REVISED SEPTEMBER 2004 DGG, DGV, OR DL PACKAGE (TOP VIEW) OEAB LEAB A1 GND A2 A3 V CC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 V CC A16 A17 GND A18 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CLKENAB CLKAB B1 GND B2 B3 V CC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 V CC B16 B17 GND B18 CLKBA CLKENBA ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN74ALVCHR16601DL SSOP - DL ALVCHR16601 Tape and reel SN74ALVCHR16601LR -40 C to 85 C TSSOP - DGG Tape and reel SN74ALVCHR16601GR ALVCHR16601 TVSOP - DGV Tape and reel SN74ALVCHR16601VR VR601 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at /sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, UBT are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1997 2004, Texas Instruments Incorporated
SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123I SEPTEMBER 1997 REVISED SEPTEMBER 2004 DESCRIPTION/ORDERING INFORMATION (CONTINUED) Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA. The outputs include equivalent 26-Ω series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. FUNCTION TABLE (1) INPUTS CLKENAB OEAB LEAB CLKAB A OUTPUT B X H X X X Z X L H X L L X L H X H H H L L X X B 0 (2) L L L L L L L L H H L L L L or H X B 0 (2) (1) A-to-B data flow is shown; B-to-A flow is similar, but uses OEBA, LEBA, CLKBA, and CLKENBA. (2) Output level before the indicated steady-state input conditions were established 2
SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123I SEPTEMBER 1997 REVISED SEPTEMBER 2004 LOGIC DIAGRAM (POSITIVE LOGIC) OEAB 1 CLKENAB 56 CLKAB 55 LEAB 2 LEBA 28 CLKBA 30 CLKENBA 29 OEBA 27 A1 3 CE CE 1D C1 CLK 54 B1 1D C1 CLK To 17 Other Channels ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range -0.5 4.6 V V I Input voltage range Except I/O ports (2) -0.5 4.6 V I/O ports (2)(3) -0.5 V CC + 0.5 V V O Output voltage range (2)(3) -0.5 V CC + 0.5 V I IK Input clamp current V I < 0-50 ma I OK Output clamp current V O < 0-50 ma I O Continuous output current ±50 ma Continuous current through each V CC or GND ±100 ma DGG package 64 θ JA Package thermal impedance (4) DGV package 48 C/W DL package 56 T stg Storage temperature range -65 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) This value is limited to 4.6 V maximum. (4) The package thermal impedance is calculated in accordance with JESD 51-7. 3
SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123I SEPTEMBER 1997 REVISED SEPTEMBER 2004 RECOMMENDED OPERATING CONDITIONS (1) MIN MAX UNIT V CC Supply voltage 1.65 3.6 V V CC = 1.65 V to 1.95 V 0.65 V CC V IH High-level input voltage V CC = 2.3 V to 2.7 V 1.7 V V CC = 2.7 V to 3.6 V 2 V CC = 1.65 V to 1.95 V 0.35 V CC V IL Low-level input voltage V CC = 2.3 V to 2.7 V 0.7 V V CC = 2.7 V to 3.6 V 0.8 V I Input voltage 0 V CC V V O Output voltage 0 V CC V V CC = 1.65 V -2 V CC = 2.3 V -6 I OH High-level output current ma V CC = 2.7 V -8 V CC = 3 V -12 V CC = 1.65 V 2 V CC = 2.3 V 6 I OL Low-level output current ma V CC = 2.7 V 8 V CC = 3 V 12 t/ v Input transition rise or fall rate 10 ns/v T A Operating free-air temperature -40 85 C (1) All unused control inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4
SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123I SEPTEMBER 1997 REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V CC MIN TYP (1) MAX UNIT I OH = -100 µa 1.65 V to 3.6 V V CC - 0.2 I OH = -2 ma 1.65 V 1.2 I OH = -4 ma 2.3 V 1.9 V OH 2.3 V 1.7 V I OH = -6 ma 3 V 2.4 I OH = -8 ma 2.7 V 2 I OH = -12 ma 3 V 2 I OL = 100 µa 1.65 V to 3.6 V 0.2 I OL = 2 ma 1.65 V 0.45 I OL = 4 ma 2.3 V 0.4 V OL 2.3 V 0.55 V I OL = 6 ma 3 V 0.55 I OL = 8 ma 2.7 V 0.6 I OL = 12 ma 3 V 0.8 I I V I = V CC or GND 3.6 V ±5 µa V I = 0.58 V 25 1.65 V V I = 1.07 V -25 V I = 0.7 V 45 2.3 V I I(hold) V I = 1.7 V -45 µa V I = 0.8 V 75 3 V V I = 2 V -75 V I = 0 to 3.6 V (2) 3.6 V ±500 I OZ (3) V O = V CC or GND 3.6 V ±10 µa I CC V I = V CC or GND, I O = 0 3.6 V 40 µa I CC One input at V CC - 0.6 V, Other inputs at V CC or GND 3 V to 3.6 V 750 µa C i Control inputs V I = V CC or GND 3.3 V 4 pf C io A or B ports V O = V CC or GND 3.3 V 8 pf (1) All typical values are at V CC = 3.3 V, T A = 25 C. (2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. (3) For I/O ports, the parameter I OZ includes the input leakage current. 5
SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123I SEPTEMBER 1997 REVISED SEPTEMBER 2004 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) V CC = 2.5 V V CC = 3.3 V V CC = 1.8 V V CC = 2.7 V ± 0.2 V ± 0.3 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX f clock Clock frequency (1) 150 150 150 MHz LE high (1) 3.3 3.3 3.3 t w Pulse duration ns CLK high or low (1) 3.3 3.3 3.3 Data before CLK (1) 2.3 2.4 2.1 CLK high (1) 2 1.6 1.6 t su Setup time Data before LE ns CLK low (1) 1.3 1.2 1.1 CLKEN before CLK (1) 2 2 1.7 Data after CLK (1) 0.7 0.7 0.8 CLK high (1) 1.3 1.6 1.4 t h Hold time Data after LE ns CLK low (1) 1.7 2 1.7 CLKEN after CLK (1) 0.3 0.5 0.6 (1) This information was not available at the time of publication. SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER OPERATING CHARACTERISTICS T A = 25 C V CC = 2.5 V V CC = 3.3 V FROM TO V CC = 1.8 V V CC = 2.7 V ± 0.2 V ± 0.3 V (INPUT) (OUTPUT) MIN TYP MIN MAX MIN MAX MIN MAX f max (1) 150 150 150 MHz A or B (1) 1 4.8 5.1 1 4.4 t pd LEAB or LEBA B or A (1) 1 5.5 5.8 1 5.1 ns CLKAB or CLKBA (1) 1.2 5.9 6.3 1.4 5.4 t en OEAB or OEBA B or A (1) 1.1 6.3 6.6 1.1 5.6 ns t dis OEAB or OEBA B or A (1) 1 4.2 5.1 1.6 4.7 ns (1) This information was not available at the time of publication. V CC = 1.8 V V CC = 2.5 V V CC = 3.3 V PARAMETER TEST CONDITIONS UNIT TYP TYP TYP Outputs enabled (1) Power dissipation 56 63 C pd C L = 0, f = 10 MHz pf capacitance Outputs disabled (1) 12 13 (1) This information was not available at the time of publication. UNIT 6
PARAMETER MEASUREMENT INFORMATION SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123I SEPTEMBER 1997 REVISED SEPTEMBER 2004 From Output Under Test C L (see Note A) R L R L S1 V LOAD Open GND TEST t pd t PLZ /t PZL t PHZ /t PZH S1 Open V LOAD GND LOAD CIRCUIT V CC V I INPUT t r /t f V M V LOAD C L R L V 1.8 V 2.5 V ± 0.2 V 2.7 V 3 V ± 0.3 V V CC V CC 2.7 V 2.7 V 2 ns 2 ns 2.5 ns 2.5 ns VCC/2 V CC /2 1.5 V 1.5 V 2 V CC 2 V CC 6 V 6 V 30 pf 30 pf 50 pf 50 pf 1 kω 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V t w Timing Input t su V M t h V I 0 V Input V M VOLTAGE WAVEFORMS PULSE DURATION V M V I 0 V Data Input V M V M VOLTAGE WAVEFORMS SETUP AND HOLD TIMES V I 0 V Output Control (low-level enabling) t PZL V M V M t PLZ V I 0 V Input V M V M V I 0 V Output Waveform 1 S1 at V LOAD (see Note B) V M V OL + V V LOAD /2 V OL Output t PLH V M V M t PHL V OH V OL Output Waveform 2 S1 at GND (see Note B) t PZH V M t PHZ V OH V V OH 0 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z O = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. t PLZ and t PHZ are the same as t dis. F. t PZL and t PZH are the same as t en. G. t PLH and t PHL are the same as t pd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 7
PACKAGE OPTION ADDENDUM 27-Sep-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty 74ALVCHR16601DLG4 ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) 74ALVCHR16601GRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) 74ALVCHR16601GRG4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) 74ALVCHR16601LRG4 ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) 74ALVCHR16601VRE4 ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) 74ALVCHR16601VRG4 ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) SN74ALVCHR16601DL ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) SN74ALVCHR16601GR ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) SN74ALVCHR16601LR ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) SN74ALVCHR16601VR ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http:///productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) SN74ALVCHR16601GR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 SN74ALVCHR16601LR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 SN74ALVCHR16601VR TVSOP DGV 56 2000 330.0 24.4 6.8 11.7 1.6 12.0 24.0 Q1 W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVCHR16601GR TSSOP DGG 56 2000 346.0 346.0 41.0 SN74ALVCHR16601LR SSOP DL 56 1000 346.0 346.0 49.0 SN74ALVCHR16601VR TVSOP DGV 56 2000 346.0 346.0 41.0 Pack Materials-Page 2
MECHANICAL DATA MTSS003D JANUARY 1995 REVISED JANUARY 1998 DGG (R-PDSO-G**) 48 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,50 0,27 0,17 0,08 M 48 25 6,20 8,30 6,00 7,90 0,15 NOM Gage Plane 1 A 24 0 8 0,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/ F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MECHANICAL DATA MSSO001C JANUARY 1995 REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 0.005 (0,13) M 48 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 A 24 0 8 0.040 (1,02) 0.020 (0,51) 0.110 (2,79) MAX 0.008 (0,20) MIN Seating Plane 0.004 (0,10) DIM PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) 4040048/ E 12/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-118 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MECHANICAL DATA MPDS006C FEBRUARY 1996 REVISED AUGUST 2000 DGV (R-PDSO-G**) 24 PINS SHOWN PLASTIC SMALL-OUTLINE 0,40 0,23 0,13 0,07 M 24 13 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 1 12 A 0 8 0,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,08 DIM PINS ** 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins MO-153 14/16/20/56 Pins MO-194 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan SN74ALVCHR16601DL ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) SN74ALVCHR16601GR ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) SN74ALVCHR16601LR ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) SN74ALVCHR16601VR ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) Device Marking (4/5) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCHR16601 CU NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCHR16601 CU NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCHR16601 CU NIPDAU Level-1-260C-UNLIM -40 to 85 VR601 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http:///productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1
PACKAGE OPTION ADDENDUM 10-Jun-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74ALVCHR16601GR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 SN74ALVCHR16601LR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 SN74ALVCHR16601VR TVSOP DGV 56 2000 330.0 24.4 6.8 11.7 1.6 12.0 24.0 Q1 Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVCHR16601GR TSSOP DGG 56 2000 367.0 367.0 45.0 SN74ALVCHR16601LR SSOP DL 56 1000 367.0 367.0 55.0 SN74ALVCHR16601VR TVSOP DGV 56 2000 367.0 367.0 45.0 Pack Materials-Page 2
MECHANICAL DATA MPDS006C FEBRUARY 1996 REVISED AUGUST 2000 DGV (R-PDSO-G**) 24 PINS SHOWN PLASTIC SMALL-OUTLINE 0,40 0,23 0,13 0,07 M 24 13 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 1 12 A 0 8 0,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,08 DIM PINS ** 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins MO-153 14/16/20/56 Pins MO-194 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCALE 1.200 DGG0056A PACKAGE OUTLINE TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE C 8.3 TYP 7.9 SEATING PLANE A 1 PIN 1 ID AREA 56 54X 0.5 0.1 C 14.1 13.9 NOTE 3 2X 13.5 28 B 6.2 6.0 29 56X 0.27 0.17 0.08 C A B 1.2 MAX (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0-8 0.75 0.50 DETAIL A TYPICAL 0.15 0.05 4222167/A 07/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153.
DGG0056A EXAMPLE BOARD LAYOUT TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R 0.05) TYP SYMM 28 29 (7.5) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND NON SOLDER MASK DEFINED SOLDER MASK DEFINED SOLDER MASK DETAILS 4222167/A 07/2015 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
DGG0056A EXAMPLE STENCIL DESIGN TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) 56X (0.3) 1 SYMM 56 54X (0.5) (R 0.05) TYP SYMM 28 29 (7.5) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4222167/A 07/2015 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design.
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