Agilent HCPL-/HCPL-. Amp Output Current IGBT Gate Drive Optocoupler Data Sheet Functional Diagram N/C ANODE CATHODE N/C SHIELD HCPL-/HCPL- V CC N.C. V O V EE Description The HCPL-/HCPL- family of devices consists of a GaAsP LED optically coupled to an integrated circuit with a power output stage. These optocouplers are ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the LED OFF ON Truth Table V O LOW HIGH output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving small or medium power IGBTs. For IGBTs with higher ratings, the HCPL- (. A) or HCPL- (. A) optocouplers can be used. Features. A minimum peak output current High speed response:. µs maximum propagation delay over temperature range Ultra high CMR: minimum kv/µs at V CM = kv Bootstrappable supply current: maximum ma Wide operating temperature range: C to C Wide V CC operating range: V to V over temp. range Available in DIP and SO package Safety approvals: UL approval, V rms for minute. CSA approval. IEC/EN/DIN EN -- approval V IORM = V peak (HCPL- ) Applications Isolated IGBT/Power MOSFET gate drive AC and brushless DC motor drives Inverters for home appliances Industrial inverters Switch Mode Power Supplies (SMPS) A. µf bypass capacitor must be connected between pins V CC and V EE. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
UR Ordering Information Specify part number followed by option number (if desired). Example: HCPL-#XXXX No option = Standard DIP package, per tube. = Gull Wing Surface Mount Option, per tube. = Tape and Reel Packaging Option. = IEC/EN/DIN EN --, V IORM = V PEAK. XXXE = Lead Free Option. HCPL-#XXXX No option = SOIC- surface mount in tube, per tube. = Tape and Reel Packaging Option. = IEC/EN/DIN EN --, V IORM = V PEAK. XXXE = Lead Free Option. Remarks: The notation # is used for existing products, while (new) products launched since th July and lead free option will use - Package Outline Drawings HCPL- Standard DIP Package 9. ±. (. ±.). ±. (. ±.) TYPE NUMBER A XXXXZ OPTION CODE* DATE CODE. ±. (. ±.) YYWW UL RECOGNITION.9 (.) MAX.. ±. (. ±.). (.) MAX.. (.) MAX. TYP.. +. -. (. +.) -.).9 (.) MIN.. (.) MIN.. ±. (. ±.). (.) MAX.. ±. (. ±.) DIMENSIONS IN MILLIMETERS AND (INCHES). * MARKING CODE LETTER FOR OPTION NUMBERS "V" = OPTION OPTION NUMBERS AND NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.
HCPL- Gull Wing Surface Mount Option Outline Drawing LAND PATTERN RECOMMENDATION 9. ±. (. ±.). (.). ±. (. ±.).9 (.). (.). (.).9 (.) MAX.. (.) MAX.. ±. (. ±.) 9. ±. (. ±.). ±. (. ±.). +. -. (. +.) -.). ±. (. ±.).. ±. (.) (. ±.) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).. ±. (. ±.) NOM. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. HCPL- Small Outline SO- Package LAND PATTERN RECOMMENDATION.9 ±. (. ±.) PIN ONE XXX YWW. ±. (. ±.). (.) BSC.99 ±. (. ±.) TYPE NUMBER (LAST DIGITS) DATE CODE. (.).9 (.).9 (.9) *. ±. (. ±.) X. (.). ±. (. ±.). (.) ~. ±. (.9 ±.) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH). ±. (. ±.) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES) MAX.. (.) MIN.. ±. (. ±.) NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.
Solder Reflow Temperature Profile TEMPERATURE ( C) ROOM TEMPERATURE PREHEATING RATE C + C/. C/SEC. REFLOW HEATING RATE. C ±. C/SEC. C C C C + C/. C. C ±. C/SEC. PREHEATING TIME C, 9 + SEC. PEAK TEMP. C SEC. SEC. SEC. PEAK TEMP. C SOLDERING TIME C PEAK TEMP. C TIGHT TYPICAL LOOSE Regulatory Information The HCPL-/HCPL- have been approved by the following organizations: IEC/EN/DIN EN -- Approved under: IEC --:99 + A: EN --: + A: DIN EN -- (VDE Teil ):- (Option only) Recommended Pb-Free IR Profile TEMPERATURE T p +/- C T L C RAMP-UP C/SEC. MAX. T smax - C T smin t s PREHEAT to SEC. t p t L TIME (SECONDS) TIME WITHIN C of ACTUAL PEAK TEMPERATURE - SEC. RAMP-DOWN C/SEC. MAX. to SEC. UL Approval under UL, component recognition program up to V ISO = V rms. File E. CSA Approval under CSA Component Acceptance Notice #, File CA. t C to PEAK TIME NOTES: THE TIME FROM C to PEAK TEMPERATURE = MINUTES MAX. T smax = C, T smin = C IEC/EN/DIN EN -- Insulation Characteristics (HCPL- Option ) Description Symbol Characteristic Unit Installation classification per DIN VDE /.9, Table for rated mains voltage V rms for rated mains voltage V rms for rated mains voltage V rms * Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section IEC/EN/ DIN EN -- for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to the following figure for dependence of P S and I S on ambient temperature. I - IV I - III I-II Climatic Classification // Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b* V IORM x.=v PR, % Production Test with V PR V peak t m = sec, Partial discharge < pc Input to Output Test Voltage, Method a* V IORM x.=v PR, Type and Sample Test, t m = sec, V PR 9 V peak Partial discharge < pc Highest Allowable Overvoltage V IOTM V peak (Transient Overvoltage t ini = sec) Safety-limiting values - maximum values allowed in the event of a failure. Case Temperature T S C Input Current** I S,INPUT ma Output Power** P S, OUTPUT mw Insulation Resistance at T S, V IO = V R S > 9 Ω
OUTPUT POWER P S, INPUT CURRENT I S P S (mw) I S (ma) T S CASE TEMPERATURE C Insulation and Safety Related Specifications Parameter Symbol HCPL- HCPL- Units Conditions Minimum External Air Gap L()..9 mm Measured from input terminals (Clearance) to output terminals, shortest distance through air. Minimum External Tracking L().. mm Measured from input terminals (Creepage) to output terminals, shortest distance path along body. Minimum Internal Plastic Gap.. mm Through insulation distance (Internal Clearance) conductor to conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance CTI > > V DIN IEC /VDE Part (Comparative Tracking Index) Isolation Group IIIa IIIa Material Group (DIN VDE, /9, Table ) Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S - C Operating Temperature T A - C Average Input Current I F(AVG) ma Peak Transient Input Current (< µs pulse I F(TRAN). A width, pps) Reverse Input Voltage V R V High Peak Output Current I OH(PEAK). A Low Peak Output Current I OL(PEAK). A Supply Voltage V CC -V EE -. V Output Voltage V O(PEAK) -. V CC V Output Power Dissipation P O mw Input Power Dissipation P I mw Lead Solder Temperature C for sec.,. mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings section
Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Power Supply V CC -V EE V Input Current (ON) I F(ON) ma Input Voltage (OFF) V F(OFF) -.. V Operating Temperature T A - C Electrical Specifications (DC) Over recommended operating conditions unless otherwise specified. Test Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note High Level Output Current I OH. A Vo = V CC -.. Vo = V CC - Low Level Output Current I OL.. A Vo = V EE +... Vo = V EE + High Level Output Voltage V OH V CC - V CC -. V Io = - ma, Low Level Output Voltage V OL. V Io = ma High Level Supply Current I CCH. ma Io = ma, Low Level Supply Current I CCL. ma Io = ma Threshold Input Current I FLH ma Io = ma, 9, Low to High Vo> V Threshold Input Voltage V FHL. V High to Low Input Forward Voltage V F... V I F = ma Temperature Coefficient of DV F /DT A. mv/ C Input Forward Voltage Input Reverse Breakdown BV R V I R = µa Voltage Input Capacitance C IN pf f = MHz, V F = V
Switching Specifications (AC) Over recommended operating conditions unless otherwise specified. Test Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note Propagation Delay Time to t PLH... µs Rg = Ω,,, High Output Level Cg = nf,,, Propagation Delay Time to t PHL... µs f = khz,, Low Output Level Duty Cycle = %, Propagation Delay PDD -.. µs I Difference Between Any F = ma, V Two Parts or Channels CC = V Rise Time t R ns Fall Time t F ns Output High Level Common CM H kv/µs T A = C, Mode Transient Immunity V CM = kv Output Low Level Common CM L kv/µs Mode Transient Immunity Package Characteristics Test Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note Input-Output Momentary V ISO V rms T A = C,,9 Withstand Voltage RH<% for Input-Output Resistance R I-O Ω V I-O = V 9 Input-Output Capacitance C I-O. pf Freq= MHz Notes:. Derate linearly above C free air temperature at a rate of. ma/ C.. Maximum pulse width = µs, maximum duty cycle =.%. This value is intended to allow for component tolerances for designs with I O peak minimum =. A. See Application section for additional details on limiting I OL peak.. Derate linearly above C, free air temperature at the rate of. mw/ C.. Input power dissipation does not require derating.. Maximum pulse width = µs, maximum duty cycle =.%.. In this test, V OH is measured with a DC load current. When driving capacitive load V OH will approach V CC as I OH approaches zero amps.. Maximum pulse width = ms, maximum duty cycle = %.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for second (leakage detection current limit I I-O µa). This test is performed before % production test for partial discharge (method B) shown in the IEC/EN/DIN EN -- Insulation Characteristics Table, if applicable. 9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.. PDD is the difference between t PHL and t PLH between any two parts or channels under the same test conditions.. Common mode transient immunity in the high state is the maximum tolerable dvcm/dt of the common mode pulse V CM to assure that the output will remain in the high state (i.e. Vo >. V).. Common mode transient immunity in a low state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a low state (i.e. Vo <. V).. This load condition approximates the gate load of a V/ A IGBT.. The power supply current increases when operating frequency and Qg of the driven IGBT increases.
(V OH -V CC ) HIGH OUTPUT VOLTAGE DROP V -. -. -. -. -. - - T A TEMPERATURE C I OH OUTPUT HIGH CURRENT A...... - - T A TEMPERATURE C (V OH -V CC ) OUTPUT HIGH VOLTAGE DROP V - - - - - -.. V OH I OH OUTPUT HIGH CURRENT A. Figure. V OH vs. Temperature. Figure. I OH vs. Temperature. Figure. V OH vs. I OH... V OL OUTPUT LOW VOLTAGE V.....9 - - I OL OUTPUT LOW CURRENT A...... - - V OL OUTPUT LOW VOLTAGE V T A TEMPERATURE C T A TEMPERATURE C I OL OUTPUT LOW CURRENT ma Figure. V OL vs. Temperature. Figure. I OL vs. Temperature. Figure. V OL vs. I OL. I CC SUPPLY CURRENT ma....... - - T A TEMPERATURE C I CC L I CC H I CC SUPPLY CURRENT ma...... I CC L I CC H V CC SUPPLY VOLTAGE V I FLH LOW TO HIGH CURRENT THRESHOLD ma..... - - T A TEMPERATURE C Figure. I CC vs. Temperature. Figure. I CC vs. V CC. Figure 9. I FLH vs. Temperature.
T P PROPAGATION DELAY ns T PLH T PHL T P PROPAGATION DELAY ns 9 T P PROPAGATION DELAY ns - - T PLH T PHL V CC SUPPLY VOLTAGE V I F FORWARD LED CURRENT ma T A TEMPERATURE C Figure. Propagation Delay vs. V CC. Figure. Propagation Delay vs. I F. Figure. Propagation Delay vs. Temperature. T P PROPAGATION DELAY ns T PLH T PHL T P PROPAGATION DELAY ns T PLH T PHL V O OUTPUT VOLTAGE V - Rg SERIES LOAD RESISTANCE Ω Cg LOAD CAPACITANCE nf I F FORWARD LED CURRENT ma Figure. Propagation Delay vs. Rg. Figure. Propagation Delay vs. Cg. Figure. Transfer Characteristics. I F FORWARD CURRENT ma.... V F FORWARD VOLTAGE V Figure. Input Current vs. Forward Voltage. 9
KHz % DUTY CYCLE I F = to ma Ω +. µf + V O Ω V CC = to V I F t r t f 9% % nf V OUT % t PLH t PHL Figure. Propagation Delay Test Circuit and Waveforms. V CM V I F A + B. µf V + O V CC = V V V O t δv V CM δt = t V OH SWITCH AT A: I F = ma V O V OL + V CM = V SWITCH AT B: I F = ma Figure. CMR Test Circuit and Waveforms.
Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the HCPL-/HCPL- has a very low maximum V OL specification of. V. Minimizing Rg and the lead inductance from the HCPL-/HCPL- to the IGBT gate and emitter (possibly by mounting the HCPL-/HCPL- on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 9. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL-/HCPL- input as this can result in unwanted coupling of transient signals into the input of HCPL-/ HCPL- and degrade performance. (If the IGBT drain must be routed near the HCPL-/HCPL- input, then the LED should be reverse biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-/ HCPL-.) + V Ω HCPL-/HCPL-. µf V CC = V + + HVDC Rg CONTROL INPUT Q -PHASE AC XXX OPEN COLLECTOR Q - HVDC Figure 9. Recommended LED Drive and Application Circuit for HCPL-/HCPL-.
Selecting the Gate Resistor (Rg) Step : Calculate R g minimum from the I OL peak specification. The IGBT and Rg in Figure 9 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-/HCPL-. Rg V CC V OL I OLPEAK = V V.A = Ω Esw ENERGY PER SWITCHING CYCLE µj........ Qg = nc Qg = nc Qg = nc Qg = nc Rg GATE RESISTANCE Ω The V OL value of V in the previous equation is the V OL at the peak current of.a. (See Figure ). Step : Check the HCPL-/HCPL- power dissipation and increase Rg if necessary. The HCPL-/HCPL- total power dissipation (P T ) is equal to the sum of the emitter power (P E ) and the output power (P O ). P T = P E + P O P E = I F V F Duty Cycle P O = P O(BIAS) + P O(SWITCHING) = I CC V CC + E SW (Rg,Qg) f = (I CCBIAS + K ICC Qg f) V CC + E SW (Rg,Qg) f where K ICC Qg f is the increase in I CC due to switching and K ICC is a constant of. ma/(nc*khz). For the circuit in Figure 9 with I F (worst case) = ma, Rg = Ω, Max Duty Cycle = %, Qg = nc, f = khz and T AMAX = C: P E = ma. V. = mw P O = ( ma + (. ma/(nc khz)) khz nc) V +. µj khz = mw < mw (P O(MAX) @ C) The value of ma for I CC in the previous equation is the max. I CC over entire operating temperature range. Since P O for this case is less than P O(MAX), Rg = Ω is alright for the power dissipation. Figure. Energy Dissipated in the HCPL- and for Each IGBT Switching Cycle. LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure. The HCPL-/HCPL- improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and opto-coupler pins - as shown in Figure. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off) during common mode transients. For example, the recommended application circuit (Figure 9), can achieve kv/µs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections.
C LEDO C LEDP C LEDP C LEDO C LEDN C LEDN SHIELD Figure. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers. Figure. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers. + V + V SAT C LEDP I LEDP C LEDN. µf + V CC = V Rg SHIELD * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING dv CM /dt. + V CM Figure. Equivalent Circuit for Figure During Common Mode Transient. + V + V C LEDP C LEDP Q C LEDN C LEDN I LEDN SHIELD SHIELD Figure. Not Recommended Open Collector Drive Circuit. Figure. Recommended LED Drive Circuit for Ultra-High CMR IPM Dead Time and Propagation Delay Specifications.
CMR with the LED On (CMR H ) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of ma provides adequate margin over the maximum I FLH of ma to achieve kv/µs CMR. CMR with the LED Off (CMR L ) A high CMR LED drive circuit must keep the LED off (V F V F(OFF) ) during common mode transients. For example, during a -dv CM /dt transient in Figure, the current flowing through C LEDP also flows through the R SAT and V SAT of the logic gate. As long as the low state voltage developed across the logic gate is less than V F(OFF) the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure, can not keep the LED off during a +dv CM /dt transient, since all the current flowing through C LEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMR performance. The alternative drive circuit which like the recommended application circuit (Figure 9), does achieve ultra high CMR performance by shunting the LED in the off state. IPM Dead Time and Propagation Delay Specifications The HCPL-/HCPL- includes a Propagation Delay Difference (PDD) specification intended to help designers minimize dead time in their power inverter designs. Dead time is the time high and low side power transistors are off. Any overlap in Ql and Q conduction will result in large currents flowing through the power devices from the highvoltage to the low-voltage motor rails. To minimize dead time in a given design, the turn on of LED should be delayed (relative to the turn off of LED) so that under worst-case conditions, transistor Q has just turned off when transistor Q turns on, as shown in Figure. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDD max, which is specified to be ns over the operating temperature range of - to C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specification as shown in Figure. The maximum dead time for the HCPL-/HCPL- is µs (=. µs - (-. µs)) over the operating temperature range of C to C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs.
I LED V OUT Q ON Q OFF V OUT Q OFF Q ON I LED t PHL MAX tplh MIN PDD* MAX = (t PHL - t PLH ) MAX = t PHL MAX - t PLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure. Minimum LED Skew for Zero Dead Time. I LED V OUT Q ON Q OFF V OUT Q OFF Q ON I LED t PHL MIN t PHL MAX t PLH MIN t PLH MAX (t PHL- t PLH ) MAX PDD* MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (t PHL MAX - t PHL MIN ) + (t PLH MAX - t PLH MIN ) = (t PHL MAX - t PLH MIN ) (t PHL MIN - t PLH MAX ) = PDD* MAX PDD* MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure. Waveforms for Dead Time.
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