MHz Differential Twisted-Pair Drivers EL7, EL7 The EL7 and EL7 are single and triple bandwidth amplifiers with an output in differential form. They are primarily targeted for applications such as driving twisted-pair lines in component video applications. The input signal is single-ended and the outputs are always differential. On the EL7 and EL7, two feedback inputs provide the user with the ability to set the gain of each device (stable at minimum gain of one). For a fixed gain of two, please see EL7 and EL7. The output common mode level for each channel is set by the associated V pin, which have a -db bandwidth of over MHz. Generally, these pins are grounded but can be tied to any voltage reference. All outputs are short circuit protected to withstand temporary overload condition. The EL7 and EL7 are specified for operation over the full - C to +8 C temperature range. Features Fully differential outputs and feedback Input range ±.V typ. MHz db bandwidth 8V/µs slew rate Low distortion at MHz Single V or dual ±V supplies 9mA maximum output current Low power - 8mA per channel Pb-free available (RoHS compliant) Applications Twisted-pair driver Differential line driver VGA over twisted-pair ADSL/HDSL driver Single-ended to differential amplification Transmission of analog signals in a noisy environment Pinouts EL7 (8 LD SOIC) TOP VIEW EL7 (8 LD QSOP) TOP VIEW FBP 8 OUT+ NC 8 OUT IN+ + - 7 6 VS- VS+ INP INN + - 7 FBP 6 FBN FBN OUT- OUTB NC VSP INP 6 VSN INN 7 OUT NC 8 + FBP 9 - FBN INP INN NC + - 9 OUTB 8 OUT 7 FBP 6 FBN EN OUTB August 8, FN77.8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. -888-INTERSIL or -888-68-77 Copyright Intersil Americas Inc. -6,,. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
EL7, EL7 Pin Descriptions EL7 EL7 PIN NAME PIN FUNCTION FBP Feedback from non-inverting output IN+ Non-inverting input Reference input, sets common-mode output voltage FBN Feedback from inverting output OUT- Inverting output 6 VS+ Positive supply 7 VS- Negative supply 8 OUT+ Non-inverting output 7,, 7 FBP, FBP, FBP Feedback from non-inverting output, 6, INP, INP, INP Non-inverting inputs, 8,,, Reference input, sets common-mode output voltage, 7, INN, INN, INN Inverting inputs, note that on EL7, this pin is also the pin 6,, 6 FBN, FBN, FBN Feedback from inverting output, 9, OUTB, OUTB, OUTB Inverting outputs VSP Positive supply VSN Negative supply 8,, 8 OUT, OUT, OUT Non-inverting outputs,, 9, NC No connects, grounded for best crosstalk performance EN ENABLE Ordering Information PART NUMBER (Notes,, ) PART MARKING PACKAGE (Pb-free) PKG. DWG. # EL7ISZ 7ISZ 8 Ld SOIC M8.E EL7IUZ EL7IUZ 8 Ld QSOP M8. NOTES:. Add -T* suffix for tape and reel. Please refer to TB7 for details on reel specifications.. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-.. For Moisture Sensitivity Level (MSL), please see device information page for EL7, EL7. For more information on MSL please see tech brief TB6. FN77.8 August 8,
EL7, EL7 Absolute Maximum Ratings (T A = + C) Supply Voltage (V S + to V S -).................................... V Supply Voltage Rate-of-rise (dv/dt)........................... V/µs Input Voltage (IN+, IN- to V S +, V S -)............. V S - -.V to V S + +.V Differential Input Voltage (IN+ to IN-).......................... ±.8V Maximum Output Current.................................. ±6mA Thermal Information Operating Junction Temperature............................+ C Ambient Operating Temperature.....................- C to +8 C Storage Temperature Range........................-6 C to + C Power Dissipation...................................... See Curves Pb-Free Reflow Profile............................... see link below http://www.intersil.com/pbfree/pb-freereflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S + = +V, V S - = -V, T A = + C, V IN = V, R LD = kω, =, = OPEN, C LD =.7pF, Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITIONS AC PERFORMANCE MIN (Note ) TYP MAX (Note ) BW -db Bandwidth A V =, C LD =.7pF MHz A V =, =, C LD =.7pF 6 MHz A V =, =, C LD =.7pF MHz BW ±.db Bandwidth A V =, C LD =.7pF MHz SR Slew Rate (EL7) V OUT = V P-P, % to 8% 6 8 V/µs Slew Rate (EL7) V OUT = V P-P, % to 8% 7 V/µs t STL Settling Time to.% V OUT = V P-P ns t OVR Output Overdrive Recovery Time ns GBWP Gain Bandwidth Product MHz V BW (-db) V -db Bandwidth A V =, C LD =.7pF MHz V SR+ V Slew Rate - Rise V OUT = V P-P, % to 8% 9 V/µs V SR- V Slew Rate - Fall V OUT = V P-P, % to 8% V/µs V N Input Voltage Noise at khz 6 nv/ Hz I N Input Current Noise at khz pa/ Hz HD Second Harmonic Distortion V OUT = V P-P, MHz -9 dbc V OUT = V P-P, MHz -9 dbc HD Third Harmonic Distortion V OUT = V P-P, MHz -77 dbc V OUT = V P-P, MHz -7 dbc dg Differential Gain at.8mhz R L = Ω, A V =. % dθ Differential Phase at.8mhz R L = Ω, A V =. e S Channel Separation at f = MHz 9 db INPUT CHARACTERISTICS V OS Input Referred Offset Voltage ±. ± mv I IN Input Bias Current (V IN +, V IN -) - -6 - µa I Input Bias Current (V ).. µa R IN Differential Input Resistance kω C IN Differential Input Capacitance pf DMIR Differential Mode Input Range ±. ±. ±. V CMIR+ Common Mode Positive Input Range at V IN +, V IN - Tested only for EL7.. V UNIT FN77.8 August 8,
EL7, EL7 Electrical Specifications V S + = +V, V S - = -V, T A = + C, V IN = V, R LD = kω, =, = OPEN, C LD =.7pF, Unless Otherwise Specified. (Continued) PARAMETER DESCRIPTION CONDITIONS CMIR- Common Mode Negative Input Range at V IN +, V IN - Tested only for EL7 -. -. V V IN + Positive Reference Input Voltage Range (EL7) V IN + = V IN - = V. ±.8 V V IN - Negative Reference Input Voltage Range (EL7) V IN + = V IN - = V -. - V V OS Output Offset Relative to V (EL7) ±6 ± mv CMRR Input Common Mode Rejection Ratio (EL7) V IN = ±.V 7 8 db Gain Gain Accuracy V IN = (EL7).98.996. V V IN = (EL7).978.99.8 V OUTPUT CHARACTERISTICS V OUT Output Voltage Swing R L = Ω to GND (EL7) ±. V R L = Ω to GND (EL7) ±.6 ±.9 V I OUT (Max) Maximum Output Current R L = Ω, V IN = ±. (EL7) ±7 ±9 ± ma R L = Ω, V IN = ±. (EL7) ± ±7 ±9 ma R OUT Output Impedance mω SUPPLY MIN (Note ) V SUPPLY Supply Operating Range V S + to V S -.7 V I S(ON) Power Supply Current - Per Channel 6.8 7. 8. ma I S(OFF) + Positive Power Supply Current - Disabled (EL7) EN pin tied to.8v.7 µa I S(OFF) - Negative Power Supply Current - Disabled (EL7) - - µa PSRR Power Supply Rejection Ratio V S from ±.V to ±.V (EL7) 7 8 db V S from ±.V to ±.V (EL7) 6 8 db ENABLE (EL7 ONLY) t EN Enable Time ns t DS Disable Time.9 µs V IH EN Pin Voltage for Power-Up V S + -. V V IL EN Pin Voltage for Shutdown V S + -. V I IH-EN EN Pin Input Current High At V EN = V µa I IL-EN EN Pin Input Current Low At V EN = V - -8 µa NOTE:. Parameters with MIN and/or MAX limits are % tested at + C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TYP MAX (Note ) UNIT FN77.8 August 8,
Connection Diagrams -V C L FBP OUT 8 OUT INP INP VSN VSP 7 6 R LD kω FN77.8 August 8, INP INN INP INN INP INN R SP Ω R SN Ω R SR Ω R SP Ω R SN Ω R SR Ω R S Ω R SP Ω R S Ω R SN Ω R SR Ω FBN OUTB FIGURE. EL7 NC INP INN OUT 8 FBP 7 FBN 6 OUTB 6 7 8 NC INP INN VSP VSN OUT FBP 9 NC FBN INP INN OUTB 9 OUT 8 FBP 7 NC FBn 6 EN OUTB ENABLE FIGURE. EL7 +V +V -V C L C L OUTB C LB C L C LB R LD kω R LD kω C L R LD kω C LB EL7, EL7
Typical Performance Curves EL7, EL7 A V =, R LD = kω, C LD =.7pF R LD = kω, C LD =.7pF MAGNITUDE (db) - - - - - V OP-P = mv V OP-P = V P-P NORMALIZED MAGNITUDE (db) - - - - - A V = A V = A V = A V = -6 M M M G -6 M M M G FIGURE. FREQUENCY RESPONSE FIGURE. FREQUENCY RESPONSE FOR VARIOUS GAIN NORMALIZED GAIN (db) A V =, C LD =.7pF - - - - - R LD = kω R LD = Ω R LD = Ω -6 M M M G FIGURE. FREQUENCY RESPONSE vs R LD MAGNITUDE (db) A V =, R LD = kω C LD = 6pF C LD = pf C LD = pf - C LD = 9pF - C LD =.7pF - - - M M M G FIGURE 6. FREQUENCY RESPONSE vs C LD A V =, R LD = kω, C LD =.7pF A V =, = kω, C LD =.7pF 9 9 NORMALIZED GAIN (db) 8 7 6 = Ω = kω = Ω NORMALIZED GAIN (db) 8 7 6 R LD = Ω R LD = kω R LD = Ω M M M M M M M M FIGURE 7. FREQUENCY RESPONSE FIGURE 8. FREQUENCY RESPONSE vs R LD 6 FN77.8 August 8,
EL7, EL7 Typical Performance Curves (Continued) MAGNITUDE (db) - - - - - k M M M IMPEDANCE (Ω). k k M M M FIGURE 9. FREQUENCY RESPONSE - V FIGURE. OUTPUT IMPEDANCE vs FREQUENCY PSRR (db) - - - - PSRR- - -6 PSRR+ -7-8 -9 k k k M M M FIGURE. PSRR vs FREQUENCY CMRR (db) 9 8 7 6 k M M M G FIGURE. CMRR vs FREQUENCY k - VOLTAGE NOISE (nv/ Hz), CURRENT NOISE (pa/ Hz) E N I N GAIN (db) - - -6-7 -8-9 CH <=> CH, CH <=> CH CH <=> CH k k k M M FIGURE. VOLTAGE AND CURRENT NOISE vs FREQUENCY - k M M M G FIGURE. CHANNEL ISOLATION vs FREQUENCY 7 FN77.8 August 8,
EL7, EL7 Typical Performance Curves (Continued) V S = ±V, A V =, R LD = kω - V S = ±V, A V =, R LD = kω - DISTORTION (db) - -6-6 -7-7 -8-8 -9-9 HD (f = MHz) HD (f = MHz) HD (f = MHz) HD (f = MHz) DISTORTION (db) - -6-6 -7-7 -8-8 -9 HD (f = MHz) HD (f = MHz) HD (f = MHz) HD (f = MHz) -......... V OP-P, DM (V) -9 6 7 8 9 V OP-P, DM (V) FIGURE. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE FIGURE 6. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE V S = ±V, A V =, V OP-P, DM = V - V S = ±V, A V =, V OP-P, DM = V - DISTORTION (db) - -6-6 -7-7 -8-8 -9-9 HD (f = MHz) HD (f = MHz) HD (f = MHz) HD (f = MHz) DISTORTION (db) - -6-7 -8-9 HD (f = MHz) HD (f = MHz) HD (f = MHz) HD (f = MHz) - 6 7 8 9-6 7 8 9 R LD (Ω) R LD (Ω) FIGURE 7. HARMONIC DISTORTION vs R LD FIGURE 8. HARMONIC DISTORTION vs R LD - V S = ±V, R LD = kω, V OP-P, DM = V for A V =, V OP-P, DM = V for A V = - HD (A V = ) DISTORTION (db) -6-7 -8 HD (A V = ) HD (A V = ) HD (A V = ) mv/div -9-6 FREQUENCY (MHz) ns/div FIGURE 9. HARMONIC DISTORTION vs FREQUENCY FIGURE. SMALL SIGNAL TRANSIENT RESPONSE 8 FN77.8 August 8,
EL7, EL7 Typical Performance Curves (Continued) M = ns, CH = mv/div, CH = V/DIV.V/DIV CH CH ns/div ns/div FIGURE. LARGE SIGNAL TRANSIENT RESPONSE FIGURE. ENABLED RESPONSE CH CH M = ns, CH = mv/div, CH = V/DIV POWER DISSIPATION (W) JEDEC JESD- LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD...8.6...W 6mW SO8 θ JA = +6 C/W QSOP8 θ JA =+99 C/W ns/div 7 8 AMBIENT TEMPERATURE ( C) FIGURE. DISABLED RESPONSE FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD. POWER DISSIPATION (W)...8.6...66W 99mW SO8 θ JA = + C/W QSOP8 θ JA = +79 C/W 7 8 AMBIENT TEMPERATURE ( C) FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 9 FN77.8 August 8,
EL7, EL7 Simplified Schematic V S + R R R R R 7 R 8 IN+ IN- FBP FBN V B OUT+ R CD R CD C C V B OUT- R 9 R C C R R 6 V S - Description of Operation and Application Information Product Description The EL7 and EL7 are wide bandwidth, low power and single-ended to differential output amplifiers. The EL7 is a single channel differential amplifier. Since the I N - pin and pin are tied together internally, the EL7 can be used as a single-ended to differential converter. The EL7 is a triple channel differential amplifier. The EL7 has a separate I N - pin and pin for each channel. It can be used as a single/differential ended to differential converter. The EL7 and EL7 are internally compensated for closed loop gain of + or greater. Connected in gain of and driving a kω differential load, the EL7 and EL7 have a -db bandwidth of MHz. Driving a Ω differential load at gain of, the bandwidth is about MHz. The EL7 is available with a power-down feature to reduce the power while the amplifier is disabled. Input, Output, and Supply Voltage Range The EL7 and EL7 have been designed to operate with a single supply voltage of V to V or split supplies with its total voltage from V to V. The amplifiers have an input common mode voltage range from -.V to.v for ±V supply. The differential mode input range (DMIR) between the two inputs is from -.V to +.V. The input voltage range at the pin is from -.V to.8v. If the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal to become distorted. The output of the EL7 and EL7 can swing from -.9V to +.9V at kω differential load at ±V supply. As the load resistance becomes lower, the output swing is reduced. Differential and Common Mode Gain Settings For EL7, since the I N - pin and pin are bound together as the pin in an 8 Ld package, the signal at the pin is part of the common mode signal and also part of the differential mode signal. For the true balance differential outputs, the pin must be tied to the same bias level as the I N + pin. For a ±V supply, just tie the pin to GND if the I N + pin is biased at V with a Ω or 7Ω termination resistor. For a single supply application, if the I N + is biased to half of the rail, the pin should be biased to half of the rail also. The gain setting for EL7 is expressed in Equation : V ODM = + V IN + + --------------------------- V OCM = V = V V ODM V IN + = + ---------- (EQ. Where: V = V = = The EL7 has a separate I N - pin and pin. It can be used as a single/differential ended to differential converter. The voltage applied at pin can set the output common mode voltage and the gain is one. The gain setting for EL7 is expressed in Equation : = V OCM V V ODM ( V IN + V IN - ) + = + --------------------------- FN77.8 August 8,
EL7, EL7 V ODM = ( V IN + V IN - ) + ---------- (EQ. Where: = = V IN + V IN - V FBP IN+ IN- FBN FIGURE 6. V O + Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +, no feedback resistor is required. Just short the OUT+ pin to the FBP pin and the OUTpin to the FBN pin. For gains greater than +, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, has some maximum value that should not be exceeded for optimum performance. If a large value of must be used, a small capacitor in the few Pico farad range in parallel with can help to reduce the ringing and peaking at the expense of reducing the bandwidth. The bandwidth of the EL7 and EL7 depends on the load and the feedback network. and appear in parallel with the load for gains other than +. As this combination gets smaller, the bandwidth falls off. Consequently, also has a minimum value that should not be exceeded for optimum bandwidth performance. For gain of +, = is optimum. For the gains other than +, optimum response is obtained with between Ω to kω. The EL7 and EL7 have a gain bandwidth product of MHz for R LD = kω. For gains, their bandwidth can be predicted by Equation : Gain BW = MHz (EQ. ) Driving Capacitive Loads and Cables The EL7 and EL7 can drive differential capacitor in parallel with kω differential load with less than db of peaking at gain of +. If less peaking is desired in applications, a small series resistor (usually between Ω to Ω) can be V O - placed in series with each output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than, the gain resistor can then be chosen to make up for any gain loss, which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. Disable/Power-Down (for EL7 only) The EL7 can be disabled and its outputs placed in a high impedance state. The turn-off time is about.9µs and the turn-on time is about ns. When disabled, the amplifier's supply current is reduced to.7µa for I S + and µa for I S - typically, thereby effectively eliminating the power consumption. The amplifier's power-down can be controlled by standard CMOS signal levels at the ENABLE pin. The applied logic signal is relative to the V S + pin. Letting the EN pin float or applying a signal that is less than.v below V S + will enable the amplifier. The amplifier will be disabled when the signal at the EN pin is above V S + -.V. Output Drive Capability The EL7 and EL7 have internal short circuit protection. Its typical short circuit current is ±9mA for EL7 and ±7mA for EL7. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±6mA. This limit is set by the design of the internal metal interconnections. Power Dissipation With the high output drive capability of the EL7 and EL7, it is possible to exceed the + C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation : T JMAX T AMAX PD MAX = -------------------------------------------- (EQ. ) Where: Θ JA T JMAX = Maximum junction temperature T AMAX = Maximum ambient temperature θ JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply FN77.8 August 8,
EL7, EL7 voltage, plus the power in the IC due to the load, or as represented in Equation : PD i V STOT I SMAX ( VSTOT ΔV O ) ΔV O = + ----------- R LD Where: V STOT = Total supply voltage = V S + - V S - I SMAX = Maximum quiescent supply current per channel ΔV O = Maximum differential output voltage of the application R LD = Differential load resistance I LOAD = Load current i = Number of channels By setting the two PD MAX equations equal to each other, we can solve the output current and R LOAD to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well Typical Applications (EQ. ) bypassed to reduce the risk of oscillation. For normal single supply operation, where the V S - pin is connected to the ground plane, a single.7µf tantalum capacitor in parallel with a.µf ceramic capacitor from V S + to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the V S - pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided, if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. As the signal is transmitted through a cable, the high frequency signal will be attenuated. One way to compensate this loss is to boost the high frequency gain at the receiver side. R T EL7/ EL7 TWISTED PAIR Z O = Ω IN+ FBP IN+ IN- FBN IN- EL7/ EL7 V O R R FIGURE 7. TWISTED PAIR CABLE RECEIVER FN77.8 August 8,
EL7, EL7 GAIN (db) FBP R T 7 C I N + I N - V O + C L FBN V O - f L f H FREQUENCY DC Gain = + ---------- f L ------------------------ π C C ( HF)Gain = + -------------------------- C f H ---------------------------- πc C C FIGURE 8. TRANSMIT EQUALIZER FN77.8 August 8,
Package Outline Drawing M8.E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev, 8/9 EL7, EL7.9 ±. A DETAIL "A". ±. B 6. ±..9 ±. PIN NO. ID MARK.7. ±.76 (.) x ± TOP VIEW. MCAB SIDE VIEW B.7 MAX. ±..7 ±.7 SIDE VIEW A. GAUGE PLANE C SEATING PLANE. C.6 ±. (.7) (.6) DETAIL "A" (.) NOTES:. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. (.).... 6. Dimensioning and tolerancing conform to AMSE Y.m-99. Unless otherwise specified, tolerance : Decimal ±. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed.mm per side. The pin # identifier may be either a mold or mark feature. Reference to JEDEC MS-. TYPICAL RECOMMENDED LAND PATTERN FN77.8 August 8,
EL7, EL7 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP) N INDEX AREA e D B.7(.7) M C A M E -B- -A- -C- SEATING PLANE A B S H.(.) M B A NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y.M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.mm (.6 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm (. inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be.mm (. inch) total in excess of B dimension at maximum material condition.. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. α GAUGE PLANE.(.).. A M h x L C M8. 8 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (. WIDE BODY) INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A..69..7 - A.... - A -.6 -. - B.8... 9 C.7..8. - D.86.9 9.8. E..7.8.98 e. BSC.6 BSC - H.8..8 6.9 - h.99.96.6.9 L.6...7 6 N 8 8 7 α 8 8 - Rev. 6/ For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN77.8 August 8,