EL570, EL570 Data Sheet FN709.7 00MHz Differential Twisted-Pair Drivers The EL570 and EL570 are single and triple high bandwidth amplifiers with a fixed gain of. They are primarily targeted for applications such as driving twisted-pair lines in component video applications. The inputs signal can be in either singleended or differential form but the outputs are always in differential form. The output common mode level for each channel is set by the associated V REF pin, which have a -db bandwidth of over 70MHz. Generally, these pins are grounded but can be tied to any voltage reference. All outputs are short circuit protected to withstand temporary overload condition. The EL570 and EL570 are specified for operation over the full -0 C to +85 C temperature range. Pinouts EL570 (8 LD SOIC, MSOP) TOP VIEW EL570 ( LD QSOP) TOP VIEW Features Fully differential inputs and outputs Differential input range ±.V typ. 00MHz db bandwidth at fixed gain of 00V/µs slew rate Single 5V or dual ±5V supplies 50mA maximum output current Low power - 7.mA per channel Pb-free plus anneal available (RoHS compliant) Applications Twisted-pair drivers Differential line drivers VGA over twisted-pairs ADSL/HDSL drivers Single ended to differential amplification Transmission of analog signals in a noisy environment + - 8 7 6 IN+ EN IN- OUT+ VS- VS+ EN INP INN + - OUT OUTB NC REF 5 OUT- REF NC 5 VSP 0 VSN INP 6 9 NC INN REF 7 8 + - 8 OUT 7 OUTB NC 9 6 NC INP 0 INN REF + - 5 OUT OUTB NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. -888-INTERSIL or -888-68-77 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 00, 00, 00, 006, 007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL570, EL570 Ordering Information PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # EL570IS 570IS - 8 Ld SOIC (50 mil) MDP007 EL570IS-T7 570IS 7 8 Ld SOIC (50 mil) MDP007 EL570IS-T 570IS 8 Ld SOIC (50 mil) MDP007 EL570ISZ (Note) 570ISZ - 8 Ld SOIC (50 mil) (Pb-free) MDP007 EL570ISZ-T7 (Note) 570ISZ 7 8 Ld SOIC (50 mil) (Pb-free) MDP007 EL570ISZ-T (Note) 570ISZ 8 Ld SOIC (50 mil) (Pb-free) MDP007 EL570IY g - 8 Ld MSOP (.0mm) MDP00 EL570IY-T7 g 7 8 Ld MSOP (.0mm) MDP00 EL570IY-T g 8 Ld MSOP (.0mm) MDP00 EL570IYZ (Note) BAAVA - 8 Ld MSOP (.0mm) (Pb-free) MDP00 EL570IYZ-T7 (Note) BAAVA 7 8 Ld MSOP (.0mm) (Pb-free) MDP00 EL570IYZ-T (Note) BAAVA 8 Ld MSOP (.0mm) (Pb-free) MDP00 EL570IU EL570IU - Ld QSOP (50 mil) MDP000 EL570IU-T7 EL570IU 7 Ld QSOP (50 mil) MDP000 EL570IU-T EL570IU Ld QSOP (50 mil) MDP000 EL570IUZ (Note) EL570IUZ - Ld QSOP (50 mil) (Pb-free) MDP000 EL570IUZ-T7 (Note) EL570IUZ 7 Ld QSOP (50 mil) (Pb-free) MDP000 EL570IUZ-T (Note) EL570IUZ Ld QSOP (50 mil) (Pb-free) MDP000 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 00% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-00. FN709.7
EL570, EL570 Absolute Maximum Ratings (T A = +5 C) Supply Voltage (V S + to V S -)...........................6V Maximum Output Current............................ ±60mA Storage Temperature Range..................-65 C to +50 C Thermal Information Operating Junction Temperature...................... +5 C Recommended Operating Temperature..........-0 C to +85 C Pb-free reflow profile..........................see link below http://www.intersil.com/pbfree/pb-freereflow.asp CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S + = +5V, V S - = -5V, T A = +5 C, V IN = 0V, A V =, R LD = 00Ω, C LD = pf, Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW -db Bandwidth 00 MHz BW ± 0.dB Bandwidth MHz SR Slew Rate V OUT = V P-P, 0% to 80% 800 00 V/µs T STL Settling Time to 0.% V OUT = V P-P 0 ns T OVR Output Overdrive Recovery time 0 ns V REF BW (-db) V REF -db Bandwidth A V =, C LD =.7pF 70 MHz V REF SR+ V REF Slew Rate - Rise V OUT = V P-P, 0% to 80% 5 V/µs V REF SR- V REF Slew Rate - Fall V OUT = V P-P, 0% to 80% 65 V/µs V N Input Voltage Noise f = 0kHz 8 nv/ Hz HD Second Harmonic Distortion V OUT = V P-P, MHz -79 dbc HD Second Harmonic Distortion V OUT = V P-P, 0MHz -65 dbc HD Third Harmonic Distortion V OUT = V P-P, MHz -6 dbc HD Third Harmonic Distortion V OUT = V P-P, 0MHz - dbc dg Differential Gain at.58mhz R LD = 00Ω, A V = 0. % dθ Differential Phase at.58mhz R LD = 00Ω, A V = 0.8 e S Channel Separation - For EL570 only at f = MHz 85 db INPUT CHARACTERISTICS V OS Input Referred Offset Voltage ±6 ±5 mv I IN Input Bias Current (V IN, V INB ) -0-6 - µa I REF Input Bias Current at REF Pin V REF = +.V 0.5.5 µa V REF = -.V - 0 + µa Gain Gain Accuracy V IN = ±V.98.0 V R IN Differential Input Resistance 00 kω C IN Differential Input Capacitance pf DMIR Differential Mode Input Range ±. ±. V CMIR+ CMIR- Common Mode Positive Input Range at V IN +, V IN - Common Mode Negative Input Range at V IN +, V IN -.. V -.5 -. V FN709.7
EL570, EL570 Electrical Specifications V S + = +5V, V S - = -5V, T A = +5 C, V IN = 0V, A V =, R LD = 00Ω, C LD = pf, Unless Otherwise Specified. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT V REFIN Reference Input Voltage Range - Positive V IN + = V IN - = 0V..8 V Reference Input Voltage Range - Negative -. - V V REFOS Output Offset Relative to V REF -0 60 +0 mv CMRR Input Common Mode Rejection Ratio V IN = ±.5V 65 8 db OUTPUT CHARACTERISTICS V OUT Positive Output Voltage Swing R LD = 00Ω..6 V Negative Output Voltage Swing -. - V I OUT (Max) Maximum Output Current R L = 0Ω (EL570) ±50 ±80 ma R L = 0Ω (EL570) ±70 ±85 ma R OUT Output Impedance 60 mω SUPPLY V SUPPLY Supply Operating Range V S + to V S -.75 V I S(ON) Power Supply Current - Per channel 6 7. 8. ma I S(OFF) + Positive Power Supply Current - Disabled EN pin tied to.8v (EL570) 60 80 00 µa I S(OFF) - Negative Power Supply Current - Disabled -50-0 -90 µa I S(OFF) + Positive Power Supply Current - Disabled EN pin tied to.8v (EL570) 0.5 5 µa I S(OFF) - Negative Power Supply Current - Disabled -50-0 -90 µa PSRR Power Supply Rejection Ratio V S from ±.5V to ±5.5V (EL570) 70 8 db V S from ±.5V to ±5.5V (EL570) 65 8 db ENABLE t EN Enable Time 00 ns t DS Disable Time µs V IH EN Pin Voltage for Power-up V S + -.5 V IL EN Pin Voltage for Shut-down V S + - 0.5 V V I IH-EN EN Pin Input Current High - per channel At V EN = 5V 0 50 µa I IL-EN EN Pin Input Current Low - per channel At V EN = 0V -6 - µa Pin Descriptions EL570 EL570 PIN NAME PIN FUNCTION, 6, 0 IN+, INP,, Non-inverting inputs EN Enable, 7, IN-, INN,, Inverting inputs, 8, REF,, Reference input, sets common-mode output voltage 5, 7, OUT-, OUTB, B, B Inverting outputs 6 VS+, VSP Positive supply 7 0 VS-, VSN Negative supply 8 5, 8, OUT+, OUT,, Non-inverting outputs 5, 9,, 6, 9, NC No connects, grounded for best crosstalk performance FN709.7
Connection Diagrams EL570 INP EN R S INP EN OUT VSN 8 7-5V R RT LOADP 5 FN709.7 INP INN REF INP INN REF INP INN REF R SP R SN R SR R SP R SN INN REF ENABLE R SR R S R SP R S R SN 5 6 7 8 9 R SR INN REF EN INP INN REF NC INP INN REF NC 0 INP INN REF VSP 6 OUTB 5 EL570 OUT OUTB NC VSP VSN 0 NC 9 OUT 8 OUTB 7 NC 6 OUT 5 OUTB NC +5V +5V -5V R RT LOADN R RT R RTB R RT R RTB R RT R RTB LD LDB LD LDB LD LDB EL570, EL570
EL570, EL570 Typical Performance Curves GAIN (db) V S = ±5V, A V =, R LD = 00Ω, C LD = pf C LD = pf, V ODP-P = 00mV 0 0 9 9 8 8 R LD = kω 7 7 6 6 R LD = 500Ω V OP-P = 00mV 5 5 R LD = 00Ω R LD = 00Ω V OP-P = V 0 0 00K M 0M 00M G 00K M 0M 00M G FREQUENCY (Hz) FREQUENCY (Hz) V OP-P = V GAIN (db) FIGURE. FREQUENCY RESPONSE FIGURE. SMALL SIGNAL FREQUENCY RESPONSE vs R LD GAIN (db) V S = ±5V, R LD = 00Ω, V ODP-P = 00mV 0 C LD = 75pF 9 8 C LD = 0pF 7 6 5 C LD = 0pF C LD = 0pF 00K M 0M 00M G FREQUENCY (Hz) GAIN (db) 0 - - - - -5-6 M V REF = 00mV P-P V REF = V P-P 0M 00M FREQUENCY (Hz) FIGURE. SMALL SIGNAL FREQUENCY RESPONSE vs C LD FIGURE. FREQUENCY RESPONSE vs V REF V INCM + - 00Ω V ODM V OCM 00Ω PSRR (db) 0-0 -0-0 -0-50 -60-70 -80-90 00K PSRR- PSRR+ M 0M 00M FREQUENCY (Hz) COMMON MODE REJECTION (db) -0-0 -0-0 -50 V OCM /V INCM -60-70 V ODM /V INCM -80-90 00K M 0M 00M FREQUENCY (Hz) FIGURE 5. POWER SUPPLY REJECTION RATIO vs FREQUENCY FIGURE 6. COMMON MODE REJECTION vs FREQUENCY 6 FN709.7
EL570, EL570 Typical Performance Curves (Continued) V IN - + 00Ω R T R V ODM V CM 00Ω 0 000 BALANCE ERROR (db) -0-0 -0-0 -50 V OCM /V ODM VOLTAGE NOISE (nv/ Hz) 00-60 00K M 0M 00M FREQUENCY (Hz) FIGURE 7. DIFFERENTIAL MODE OUTPUT BALANCE ERROR vs FREQUENCY 0 0 00 K 0K 00K M 0M FREQENCY (Hz) FIGURE 8. INPUT VOLTAGE NOISE vs FREQUENCY CHANNEL ISOLATION (db) -0-50 -60-70 -80 CH<=>CH CH<=>CH CH<=>CH CH<=>CH -90 CH<=>CH -00 CH<=>CH -0 00K M 0M 00M FREQENCY (Hz) FIGURE 9. CHANNEL ISOLATION vs FREQUENCY BW (MHz) R LD = 00Ω 0 05 00 95 90 85 80 5 6 7 8 9 0 V S (V) FIGURE 0. BANDWIDTH vs SUPPLY VOLTAGE I S (ma) 7.78 7.76 7.7 I S + 7.7 7.7 I S - 7.68 7.66 7.6 7.6 7.6 7.58 5 6 7 8 9 0 V S (V) FIGURE. SUPPLY CURRENT vs SUPPLY VOLTAGE DISTORTION (db) V S = ±5V, R LD = 00Ω, V OP-P = V -0-0 HD -50-60 HD -70-80 -90 0 6 8 0 6 8 0 FREQUENCY (MHz) FIGURE. HARMONIC DISTORTION vs FREQUENCY 7 FN709.7
EL570, EL570 Typical Performance Curves (Continued) 0.5V/DIV 500mV/DIV 0ns/DIV FIGURE. V COM TRANSIENT RESPONSE 0ns/DIV FIGURE. LARGE SIGNAL TRANSIENT RESPONSE 00mV/DIV 0ns/DIV FIGURE 5. SMALL SIGNAL TRANSIENT RESPONSE FIGURE 6. DISABLED RESPONSE JEDEC JESD5- LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD. POWER DISSIPATION (W) 0.8 0.6 0. 0. 870mW 65mW 86mW MSOP8 θ JA =06 C/W QSOP θ JA =5 C/W SO8 θ JA =60 C/W 0 0 5 50 75 85 00 5 50 AMBIENT TEMPERATURE ( C) FIGURE 7. ENABLED RESPONSE FIGURE 8. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 8 FN709.7
EL570, EL570 Typical Performance Curves (Continued) JEDEC JESD5-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD. POWER DISSIPATION (W). 0.8 0.6 0. 0..6W 909mW 870mW MSOP8/0 θ JA =5 C/W QSOP θ JA =88 C/W SO8 θ JA =0 C/W 0 0 5 50 75 85 00 5 50 AMBIENT TEMPERATURE ( C) FIGURE 9. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Simplified Schematic 00Ω V S + R R R R R 7 R 8 IN+ IN- FBP FBN V B OUT+ R CD R CD REF C C V B OUT- R 9 R 0 C C R 5 R 6 V S - 00Ω Description of Operation and Application Information Product Description The EL570 and EL570 are wide bandwidth, low power and single/differential ended to differential output amplifiers. They have a fixed gain of. The EL570 is a single channel differential amplifier. The EL570 is a triple channel differential amplifier. The EL570 and EL570 have a -db bandwidth of 00MHz while driving a 00Ω differential load. The EL570 and EL570 are available with a power down feature to reduce the power while the amplifiers are disabled. 00Ω Input, Output and Supply Voltage Range The EL570 and EL570 have been designed to operate with a single supply voltage of 5V to 0V or a split supplies with its total voltage from 5V to 0V. The amplifiers have an input common mode voltage range from -.5V to.v for ±5V supply. The differential mode input range (DMIR) between the two inputs is from -.V to +.V. The input voltage range at the REF pin is from -.V to.8v. If the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal distorted. The output of the EL570 and EL570 can swing from -.V to.6v at 00Ω differential load at ±5V supply. As the load resistance becomes lower, the output swing is reduced. 9 FN709.7
EL570, EL570 Differential and Common Mode Gain Settings As shown at the simplified schematic, since the feedback resistors RF and the gain resistor are integrated with 00Ω and 00Ω, the EL570 and EL570 have a fixed gain of. The common mode gain is always one. Driving Capacitive Loads and Cables The EL570 and EL570 can drive 75pF differential capacitor in parallel with 00Ω differential load with less than.5db of peaking. If less peaking is desired in applications, a small series resistor (usually between 5Ω to ) can be placed in series with each output to eliminate most peaking. However, this will reduce the gain slightly. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier s output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. Disable/Power-Down The EL570 and EL570 can be disabled and placed their outputs in a high impedance state. The turn off time is about µs and the turn on time is about 00ns. When disabled, the amplifier s supply current is reduced to µa for I S + and 0µA for I S - typically, thereby effectively eliminating the power consumption. The amplifier s power down can be controlled by standard CMOS signal levels at the ENABLE pin. The applied logic signal is relative to V S + pin. Letting the EN pin float or applying a signal that is less than.5v below V S + will enable the amplifier. The amplifier will be disabled when the signal at EN pin is above V S + -0.5V. Output Drive Capability The EL570 and EL570 have internal short circuit protection. Its typical short circuit current is ±80mA. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±60mA. This limit is set by the design of the internal metal interconnect. Power Dissipation With the high output drive capability of the EL570 and EL570 it is possible to exceed the 5 C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX T AMAX PD MAX = -------------------------------------------- Θ JA Where: T JMAX = Maximum junction temperature T AMAX = Maximum ambient temperature θ JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: ΔV O PD = i V S I SMAX + V S ----------- R LD Where: V S = Total supply voltage I SMAX = Maximum quiescent supply current per channel ΔV O = Maximum differential output voltage of the application R LD = Differential load resistance I LOAD = Load current i = Number of channels By setting the two PD MAX equations equal to each other, we can solve the output current and R LOAD to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the V S - pin is connected to the ground plane, a single.7µf tantalum capacitor in parallel with a 0.µF ceramic capacitor from V S + to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the V S - pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier s inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. 0 FN709.7
EL570, EL570 Typical Applications 0Ω IN+ IN- EL570/ EL570 50 50 Z O = 00Ω V FB V IN V INB V REF EL57/ EL57 V OUT FIGURE 0. TWISTED PAIR DRIVER 0Ω IN+ + EL570/ EL570 IN- - V FB V IN V INB EL57/ EL57 V OUT V REF FIGURE. DUAL COAXIAL CABLE DRIVER 0V V IN IN+ EL570/ EL570 IN- FIGURE. SINGLE SUPPLY TWISTED PAIR DRIVER FN709.7
EL570, EL570 IN+ EL570/ EL570 IN- EL57/ EL57 EL57 FIGURE. DUAL SIGNAL TRANSMISSION CIRCUIT FN709.7
EL570, EL570 Small Outline Package Family (SO) A D h X 5 N (N/)+ E E PIN # I.D. MARK c A SEE DETAIL X B 0.00 M C A B (N/) L C e H A SEATING PLANE GAUGE PLANE 0.00 0.00 C 0.00 M C A B b A DETAIL X L ± MDP007 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SO6 SO6 (0.00 ) SO0 SO SO8 SYMBOL SO-8 SO- (0.50 ) (SOL-6) (SOL-0) (SOL-) (SOL-8) TOLERANCE NOTES A 0.068 0.068 0.068 0.0 0.0 0.0 0.0 MAX - A 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.00 - A 0.057 0.057 0.057 0.09 0.09 0.09 0.09 ±0.00 - b 0.07 0.07 0.07 0.07 0.07 0.07 0.07 ±0.00 - c 0.009 0.009 0.009 0.0 0.0 0.0 0.0 ±0.00 - D 0.9 0. 0.90 0.06 0.50 0.606 0.70 ±0.00, E 0.6 0.6 0.6 0.06 0.06 0.06 0.06 ±0.008 - E 0.5 0.5 0.5 0.95 0.95 0.95 0.95 ±0.00, e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.05 0.05 0.05 0.00 0.00 0.00 0.00 ±0.009 - L 0.0 0.0 0.0 0.056 0.056 0.056 0.056 Basic - h 0.0 0.0 0.0 0.00 0.00 0.00 0.00 Reference - N 8 6 6 0 8 Reference - Rev. M /07 NOTES:. Plastic or metal protrusions of 0.006 maximum per side are not included.. Plastic interlead protrusions of 0.00 maximum per side are not included.. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.5M-99 FN709.7
EL570, EL570 Quarter Size Outline Plastic Packages Family (QSOP) A N D (N/)+ MDP000 QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP6 QSOP QSOP8 TOLERANCE NOTES E E PIN # I.D. MARK A 0.068 0.068 0.068 Max. - A 0.006 0.006 0.006 ±0.00 - A 0.056 0.056 0.056 ±0.00 - b 0.00 0.00 0.00 ±0.00 - B 0.00 C A B (N/) c 0.008 0.008 0.008 ±0.00 - D 0.9 0. 0.90 ±0.00, E 0.6 0.6 0.6 ±0.008 - C SEATING PLANE 0.00 C e 0.007 C A B b H E 0.5 0.5 0.5 ±0.00, e 0.05 0.05 0.05 Basic - L 0.05 0.05 0.05 ±0.009 - L 0.0 0.0 0.0 Basic - N 6 8 Reference - c L SEE DETAIL "X" A Rev. F /07 NOTES:. Plastic or metal protrusions of 0.006 maximum per side are not included.. Plastic interlead protrusions of 0.00 maximum per side are not included.. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.5M-99. A GAUGE PLANE 0.00 A DETAIL X L ± FN709.7
EL570, EL570 Mini SO Package Family (MSOP) 0.5 M C A B A D (N/)+ N MDP00 MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL MSOP8 MSOP0 TOLERANCE NOTES A.0.0 Max. - A 0.0 0.0 ±0.05 - E E PIN # I.D. A 0.86 0.86 ±0.09 - b 0. 0. +0.07/-0.08 - c 0.8 0.8 ±0.05 - B (N/) D.00.00 ±0.0, E.90.90 ±0.5 - E.00.00 ±0.0, C e H e 0.65 0.50 Basic - L 0.55 0.55 ±0.5 - SEATING PLANE 0.0 C N LEADS c L b SEE DETAIL "X" 0.08 M C A B A L 0.95 0.95 Basic - N 8 0 Reference - Rev. D /07 NOTES:. Plastic or metal protrusions of 0.5mm maximum per side are not included.. Plastic interlead protrusions of 0.5mm maximum per side are not included.. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.5M-99. A GAUGE PLANE 0.5 A L DETAIL X ± All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 5 FN709.7