Japanese Journal of Applied Physics Vol. 45, No. 4B, 26, pp. 311 315 #26 The Japan ociety of Applied Physics Hot Carrier Reliability tudy in Body-Tied Fin-Type Field Effect Transistors Jin-Woo HAN, Choong-Ho LEE 1, onggun PARK 1 and Yang-Kyu CHOI ivision of Electrical Engineering epartment of Electrical Engineering and Computer cience, Korea Advanced Institute of cience and Technology, 373-1 Guseong-dong, Yuseong-gu, aejeon, 35-71, Republic of Korea 1 emiconductor R& Center, amsung Electronics Co., Ltd., an #24, Nongseo-ri, Kiheung-yup, Youngin, Kyunggi-do, 499-711, Republic of Korea (Received eptember 15, 25; accepted ecember 28, 25; published online April 25, 26) Hot-carrier effects in body-tied fin-type field effect transistors (FinFETs) are investigated. As the gate bias increases, coupling effects of two gates facing each other suppress the lateral channel electric field more effectively at double gate metal oxide FETs (MOFETs) than at single gate MOFETs. In double gate FinFETs, this effect is even further enhanced when the fin width is narrowed. The substrate current produced by an impact ionization process becomes large as fin width increases. In the generalized substrate current model, the maximum substrate current bias condition is approximately = :5. However, in the double-gate FinFETs, it was ð V T Þ= :3. There are two competing stress conditions: the maximum substrate current condition, and the maximum gate current condition. evice degradation is compared for various fin widths after both type of stress. It was found that the maximum substrate current stress condition degraded the device more significantly. The narrow fin is more immune to both stress biases than the wide fin. Thus, the narrow fin is appropriate for further device scaling and reliability. The supply voltage which corresponds to a 1-years lifetime was 1.31 V for the worst hot-carrier stress case. [OI: 1.1143/JJAP.45.311] KEYWOR: body-tied FinFET, hot-carrier effect, reliability, impact ionization, substrate current, device lifetime 1. Introduction A fin-type field effect transistor (FinFET) offers the superior scalability of complementary metal oxide semiconductor (CMO) with a conventional fabrication process. 1,2) In previous fully-depleted FinFETs fabricated on silicon-on-insulator (OI) wafers, the major difficulty was finding the worst hot-carrier stress condition, because a substrate current could not be measured due to its floating body. 3) In this study, the substrate current and multiplication factor, which indicate device degradation, were measured and analyzed for body-tied FinFETs fabricated on a bulk wafer. Two competing conditions degrade device reliability. The maximum substrate current stress condition ( = :5) is responsible for trap generation at i io 2 interface, and the maximum gate current stress condition ( = 1) induces trapped charges inside a gate oxide. 4) In this study, body-tied FinFETs were stressed at the maximum substrate bias condition and the maximum gate current bias condition, and the worst case stress bias condition was analyzed for various fin widths. Then, the hot-carrier lifetime was predicted by considering fin width scaling, because the fin width is a crucial parameter governing short-channel effects. This study gives us insight to investigate the hot-carrier reliability and superior scalability of FinFETs. (a) 2. Results and iscussion Body-tied FinFETs were fabricated on a bulk substrate. The fin body was directly tied to the substrate, and it was possible to measure I UB. In order to investigate the dependence of fin width ( ) on hot-carrier effects, the gate oxide thickness ( ) and gate length ( ) were fixed at 1.7 and 1 nm, respectively, and was varied from 2 to 1 nm. The details for the fabrication process used in this study have been reported in ref. 2, and the EM photographs of cross-sections of body-tied FinFETs have been reported in ref. 5. E-mail address: jinu77@nobelab.kaist.ac.kr 311 Undamaged region (b) amaged region Fig. 1. chematic for (a) the body-tied FinFET and (b) a cross-sectional view of a body-tied FinFET. Energetic electrons from impact ionization move toward a gate, and holes generated are swept toward the grounded substrate as substrate current. chematics for the impact ionization process in the bodytied FinFETs are shown in Fig. 1. Energetic carriers under a high electric field at the FinFETs cause impact ionization and generate electron hole pairs. The electrons generated
ubstrate Current [na/µm] 2 16 12 8 4 =2.5V = 3nm = 7nm = 5nm..5 1. 1.5 2. 2.5 Voltage, Multiplication Factor [I UB /I ] 1-1 1-2 1-3 1-4 =2.5V = 3nm = 7nm = 5nm..5 1. 1.5 2. 2.5 Voltage Fig. 2. Bell-shaped substrate currents are large for wide fin widths, which is undesirable in terms of hot-carrier degradation. inject into the gate oxide and result in gate oxide damage (interface traps and/or oxide traps), while created holes are swept toward the grounded substrate as substrate current. As a result of the impact ionization, the substrate current can be used to count the hot-carriers created. Typical bell-shaped substrate currents are measured for various fin widths as shown in Fig. 2. Bell-shaped substrate currents are always large for wide fin, which is undesirable in terms of hotcarrier reliability. 6) Figure 3 shows a multiplication factor (I UB =I ) which is related to the lifetime of the device. Because a vertical field from both gates in the double gate pinches and effectively reduces the lateral electric field at the narrow fin, the multiplication factor for the narrow fin is smaller than that for the wide fin. As a gate bias increases, therefore, the lateral electric field is suppressed quickly for narrow fin. The steep slope of the multiplication factor for the narrow fin results in a marked decrease in the substrate current at ¼ ¼ 2:5 V. However, a wide fin still shows a large substrate current in the high gate bias region. As a result of the reduced substrate current and multiplication factor, less hot-carrier degradation is expected as the fin width is reduced in body-tied FinFETs. In order to explain the difference in hot-carrier generation between wide and narrow fins, saturation drain voltages and velocity saturation regions for different fin widths are Fig. 3. The multiplication factor is small for the narrow fin, and the steep slope indicates a decrease in the substrate current at the high gate bias region. aturation Voltage, sat [v] 1.5 1.2.9.6.3. =4nm.4.8 1.2 1.6 2. Voltage, Fig. 4. For narrow fins, a large saturation voltage reduces the lateral channel electric field and suppresses impact ionization. suggested in Figs. 4 and 5. In a simple lateral electric field model, maximum electric field is given by E max ð sat Þ=l, where sat is the drain saturation voltage and l is a characteristic length or velocity saturation region length. The impact ionization process is exponentially dependent on high electric field. Previous experimental results using OI thin-body MOFETs indicated that E max is independent of i y x sat Velocity aturation region E E m E L L X sat E m X Fig. 5. The conceptual schematics for the velocity saturation region (impact ionization region) for double-gate FinFETs. Wide fin FinFETs have a long velocity saturation region due to small values of sat compared with narrow fin FinFETs. 312
body thickness. 7) The results in our simulation of doublegate FinFETs were the same. Thus, it is not sufficient to explain the difference in hot-carrier generation for different fin widths using only the peak lateral electric field model. In this study, it was found that sat is depends on the fin width for double-gate FinFETs. As shown in Fig. 4, sat, which is extracted from the measured data, increases as the fin width decreases. Thus, if we assume that the E max is independent of fin width (body thickness), l of the wide fin FinFETs should be larger due to the small value of sat compared to that of the narrow fin FinFETs. According to the approximation, the length of the velocity saturation is longer at lower sat. 8) As drain voltage exceeds the saturation drain voltage, a velocity saturation region is generated, and the electric field is increased exponentially in this region. The high electric field in this region causes impact ionization and substrate current generation. The conceptual schematics for the velocity saturation region (impact ionization region) for double-gate FinFETs are shown in Fig. 5. The velocity saturation region can be used to explain the substrate current and the hot-electron generation. The length of the velocity saturation region increases with sat. This behavior indicates that the wide fin FinFETs have a long velocity saturation region due to small sat compared with the narrow fin FinFETs. While the maximum electric field is similar for the narrow and wide fins, as fin width increases, the length of the impact ionization occurring extends in the direction of the source. When the carriers enter the velocity saturation region, they cause impact ionization as they pass thorough. Therefore, a longer velocity saturation region is responsible for higher hot-carrier generation for wide fin FinFETs than for narrow fin FinFETs, thereby explaining the results shown in Figs. 2 and 3. Under high electric field, electrons acquire sufficiently high energy and become hot. These hot electrons enter the gate oxide, where they can be trapped or can generate interface states. These oxide traps and/or interface states change device performance features such as threshold voltage, transconductance, and on-current. I and I characteristics of the body-tied FinFETs are compared before and after 1, s C stress in Fig. 6. The drain current was reduced, the threshold voltage was increased, and the subthreshold swing was increased after hot-carrier stress. These degradations become severe when the stress time is increased. In the generalized substrate current model, the maximum substrate current bias condition is approximately = :5 for single-gate MOFETs. 9) However, the maximum substrate current bias condition was different in the doublegate body-tied FinFETs. In order to model the peak substrate current bias condition, the bias condition causing peak substrate current for various fin widths was measured and is plotted in Fig. 7. The x-axis is the drain bias, and the y-axis is the gate bias causing peak substrate current at a fixed drain bias. A linearly fitted line from the measured data shows a slope of.3, which is independent of the fin width. The intersection point on the y-axis corresponds to the threshold voltage for each fin width. Thus, the maximum substrate current bias condition is modeled as ( V T Þ= :3 and is independent of the fin width. This implies that the coupling effect for two gates facing each other causes the 313 rain Current, I [A] rain Current, I [µa] 1-1 1-3 1-5 T 1-7 OX =.5V 1-9 1-11 1-13 Pre-stress 1sec Post-stress 1,sec Post-stress 1-15 -1. -.5..5 1. 1.5 Voltage, 3 2 1 (a) 5 Pre-stress 4 =1.2V 1sec Post-stress 1,sec Post-stress =.8V..4.8 1.2 1.6 rain Voltage, (b) Fig. 6. (a) I and (b) I characteristics before and after C stress. The drain current is reduced, the threshold voltage is increased, and the subthreshold swing increases after the stress. The degradation becomes severe as the stress time increases. Voltage, @ I UBmax 1.8 1.6 1.4 1.2 1..8.6.4.2. : V T,W V T,W=5nm V T,W=3nm.3 5nm 3nm..5 1. 1.5 2. 2.5 3. rain Voltage, Fig. 7. The gate bias causing peak substrate current is ð V T Þ= :3 and independent of the fin width. This result is different from that in case of a planar bulk-mofet. substrate current peak at a low gate voltage for a given drain voltage. Competing C stress bias conditions cause the worst hotcarrier degradation: maximum substrate current condition (ð V T Þ= :3) and maximum gate current condition ( ¼ ¼ ). The maximum substrate current stress condition and the maximum gate current stress condition are mainly responsible for trap generation at the i io 2 interface and oxide trapped charges, respectively. The substrate current and gate current are measured at the same time and plotted in Fig. 8, and the results explain device
ubstrate Current [na] 1 1 1.1.1 @I UBmax : 4nm 7nm = =2V.1 1 1 1 Current [pa] C lifetime [sec.] 1 1 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 Body-Tied FinFET = 1nm 1years lifetime tressed bias = 1.42V 1.54V tressed bias @I UBmax 1.31V 1.34V 1.2.3.4.5.6.7.8 1/ Fig. 8. The substrate current and gate current at the maximum substrate current bias condition and at the maximum gate current bias condition are plotted. As a fin width increases, the discrepancy between both conditions tends to be negligible. Both the interface trap generation and oxide trapped charges affect device reliability equally at a given fin width. degradation. At the @I UBmax bias condition, the substrate current slowly increases while the gate current rapidly increases as the fin width increases. However, at the ¼ bias condition, the substrate current rapidly increases while gate current slowly increases as the fin width increases. Because higher substrate current and gate current cause more degradation, wide fin FinFETs suffer from more degradation than narrow fin FinFETs. In the wide fin case, the discrepancy between both conditions tends to negligible. Thus, both the interface trap generation and oxide trapped charges determine the device reliability equally at a given wide fin. But, for narrow fins, @I UBmax and ¼ compete in terms of which condition degrades the device more. It is crucial to determine the worst hot-carrier stress condition at a given fin width, because the worst degradation mechanism is unclear. This uncertainty becomes more severe as the fin width decreases. The devices were stressed under both conditions for various fin widths. As shown in Fig. 9, the on-current degradation is more severe at @I UBmax than at ¼. This implies that interface trap generation leads in hot-carrier induced device degradation for body-tied FinFETs. The degradation difference between the two conditions becomes small as fin width increases. We concluded that the narrow fin device is I ON egradation [%] 5-5 -1-15 -2-25 -3-35 tress Time : 1,sec. tress Voltage : =2V I ON,Post tress - I ON,Pre tress ION egradation = I ON,Pre tress @I UBmax = 3 4 5 6 7 Fin Width [nm] Fig. 9. The worst C stress condition is at maximum substrate current bias, not at maximum gate current bias. As the fin width increases, the device degradation by hot-carrier stress worsens. 314 Fig. 1. The supply voltage corresponding to a meets 1-year C lifetime under the worst stress conditions was 1.31 and 1.42 V for fin widths 7 and 2 nm, respectively. degraded less by hot-carrier injection than the wide fin device, and a narrow fin is desirable for further device scaling in terms of hot carrier injection reliability. In Fig. 1, hot-carrier lifetime is predicted using both competing stress bias conditions described in Fig. 9. The body-tied FinFETs stressed at @I UBmax has a shorter lifetime than the one stressed at ¼. Therefore, the stress condition @I UBmax is the worst stress condition for double-gate FinFETs. The supply voltage corresponding to a 1-years C lifetime under the worst stress conditions was 1.31 and 1.42 V for fin widths of 7 and 2 nm, respectively. 3. Conclusions In this study, the hot-carrier reliability of body-tied FinFETs was comprehensively evaluated for the first time for various stress conditions. The substrate current and the multiplication factor increase as a fin width increases. In body-tied FinFETs, the maximum substrate current bias condition is ð V T Þ= :3, which is different from planar bulk-mofets at = :5. This provides insight on how to find the worst stress conditions to affect hotcarrier induced device degradation in OI FinFETs. The worst stress condition is at the maximum substrate current bias. For narrow fins, the gate bias causing the peak substrate current is responsible for the major degradation. However, for wide fins, the maximum substrate bias condition and maximum gate bias condition are equally important. The supply voltage corresponding to a 1-year C lifetime was 1.31 V for the worst case. This result guarantees that the body-tied FinFETs meets the requirements for operational voltage according to the ITR roadmap 25. Acknowledgment This work was supported in part by amsung Electronics Co., Ltd., and in part by the National Research Program for the.1-terabit Nonvolatile Memory evelopment, sponsored by the Korea Ministry of cience and Technology. 1) Y.-K. Choi, N. Lindert, P. Xuan,. Tang,. Ha, E. Anderson, T.-J. King, J. Bokor and C. Hu: IEM Tech. ig., 21, p. 421. 2) T. Park,. Choi,. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G. Lee, K. K. Chi,. H. Hong,. J. Hyun, Y. G. hin, J. N. Han, I.. Park, U. I. Chung, J. T. Moon, E. Yoon and J. H. Lee: Tech. ig. ymp. VLI Technology, 23, p. 135.
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