Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These 8-bit latches feature -state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the HC7 are transparent D-type latches. While the latch-enable () input is high, the Q outputs follow the data (D) inputs. When is taken low, the Q outputs are latched at the levels that were set up at the D inputs. An output-enable () input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. SN4HC7, SN74HC7 SN4HC7...J OR W PACKAGE SN74HC7... DB, DW, N, OR PW PACKAGE (TOP VIEW) SN4HC7... FK PACKAGE (TOP VIEW) 4 2 20 9 8 6 7 8 7 6 4 902 does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. The SN4HC7 is characterized for operation over the full military temperature range of C to 2 C. The SN74HC7 is characterized for operation from 40 C to 8 C. 2D 2Q Q D 4D Q 2D 2Q Q D 4D 4Q GND 2 4 6 7 8 9 0 Q 4Q GND 20 9 8 7 6 4 2 V CC 8Q Q D V CC 8Q 8D 7D 7Q 6Q 6D D Q 8D 7D 7Q 6Q 6D Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 997, Texas Instruments Incorporated POST OFFICE BOX 60 DALLAS, TEXAS 726
SN4HC7, SN74HC7 logic symbol FUNCTION TAB (each latch) INPUTS OUTPUT D Q L H H H L H L L L L X Q0 H X X Z EN C 2D D 4D D 6D 7D 8D 4 7 8 4 7 8 2 6 9 2 6 9 Q 2Q Q 4Q Q 6Q 7Q 8Q This symbol is in accordance with ANSI/IEEE Std 9-984 and IEC Publication 67-2. logic diagram (positive logic) C 2 Q To Seven Other Channels 2 POST OFFICE BOX 60 DALLAS, TEXAS 726
absolute maximum ratings over operating free-air temperature range SN4HC7, SN74HC7 Supply voltage range, V CC.......................................................... 0. V to 7 V Input clamp current, I IK (V I < 0 or V I > V CC ) (see Note ).................................... ±20 ma clamp current, I OK (V O < 0 or V O > V CC ) (see Note )................................ ±20 ma Continuous output current, I O (V O = 0 to V CC ).............................................. ± ma Continuous current through V CC or GND................................................... ±70 ma Package thermal impedance, θ JA (see Note 2): DB package................................ C/W DW package................................. 97 C/W N package................................... 67 C/W PW package................................ 28 C/W Storage temperature range, T stg................................................... 6 C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD, except for through-hole packages, which use a trace length of zero. recommended operating conditions SN4HC7 SN74HC7 MIN NOM MAX MIN NOM MAX Supply voltage 2 6 2 6 V = 2 V.. VIH High-level input voltage = 4. V.. V = 6 V 4.2 4.2 = 2 V 0 0. 0 0. VIL Low-level input voltage = 4. V 0. 0. V = 6 V 0.8 0.8 VI Input voltage 0 0 V VO voltage 0 0 V = 2 V 0 000 0 000 ttt Input transition (rise and fall) time = 4. V 0 00 0 00 ns = 6 V 0 400 0 400 TA Operating free-air temperature 2 40 8 C POST OFFICE BOX 60 DALLAS, TEXAS 726
SN4HC7, SN74HC7 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VI I = VIH or VIL VI I = VIH or VIL TA = 2 C SN4HC7 SN74HC7 MIN TYP MAX MIN MAX MIN MAX 2 V.9.998.9.9 IOH = 20 µa 4. V 4.4 4.499 4.4 4.4 6 V.9.999.9.9 V IOH = 6 ma 4. V.98 4..7.84 IOH = 7.8 ma 6 V.48.8.2.4 2 V 0.002 0. 0. 0. IOL = 20 µa 4. V 0.00 0. 0. 0. 6 V 0.00 0. 0. 0. V IOL = 6 ma 4. V 0.7 0.26 0.4 0. IOL = 7.8 ma 6 V 0. 0.26 0.4 0. II VI = or 0 6 V ±0. ±00 ±000 ±000 na IOZ VO = or 0 6 V ±0.0 ±0. ±0 ± µa ICC VI = or 0, IO = 0 6 V 8 60 80 µa Ci 2 V to 6 V 0 0 0 pf timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = 2 C SN4HC7 SN74HC7 MIN MAX MIN MAX MIN MAX 2 V 80 20 00 tww Pulse duration, high 4. V 6 24 20 ns 6 V 4 20 7 2 V 0 7 6 tsu Setup time, data before 4. V 0 ns 6 V 9 2 V 20 26 24 thh Hold time, data after 4. V 0 2 ns 6 V 0 2 4 POST OFFICE BOX 60 DALLAS, TEXAS 726
SN4HC7, SN74HC7 switching characteristics over recommended operating free-air temperature range, C L = 0 pf (unless otherwise noted) (see Figure ) PARAMETER tpd FROM (INPUT) TO (OUTPUT) TA = 2 C SN4HC7 SN74HC7 MIN TYP MAX MIN MAX MIN MAX 2 V 8 0 22 90 D Q 4. V 0 4 8 6 V 26 8 2 2 V 7 7 26 220 Any Q 4. V 8 44 6 V 0 4 8 2 V 6 0 22 90 ten Any Q 4. V 7 0 4 8 ns 6 V 4 26 8 2 2 V 0 0 22 90 tdis Any Q 4. V 0 4 8 ns 6 V 26 8 2 2 V 28 60 90 7 ttt Any Q 4. V 8 2 8 ns 6 V 6 0 ns switching characteristics over recommended operating free-air temperature range, C L = 0 pf (unless otherwise noted) (see Figure ) PARAMETER tpd FROM (INPUT) TO (OUTPUT) TA = 2 C SN4HC7 SN74HC7 MIN TYP MAX MIN MAX MIN MAX 2 V 82 200 00 20 D Q 4. V 22 40 60 0 6 V 9 4 4 2 V 00 22 28 Any Q 4. V 24 4 67 7 6 V 20 8 7 48 2 V 90 200 00 20 ten Any Q 4. V 2 40 60 0 ns 6 V 9 4 4 2 V 4 20 26 ttt Any Q 4. V 7 42 6 ns 6 V 6 4 ns operating characteristics, T A = 2 C PARAMETER TEST CONDITIONS TYP Cpd Power dissipation capacitance per latch No load 00 pf POST OFFICE BOX 60 DALLAS, TEXAS 726
SN4HC7, SN74HC7 PARAMETER MEASUREMENT INFORMATION PARAMETER RL CL S S2 From Under Test CL (see Note A) Test Point RL LOAD CIRCUIT S S2 ten tpzh tpzl tdis tphz tplz tpd or tt kω kω 0 pf or 0 pf 0 pf 0 pf or 0 pf High-Level Pulse Low-Level Pulse tw TAGE WAVEFORMS PULSE DURATIONS Reference Input Data Input tsu TAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES th 90% 90% tr tf Input In-Phase Out-of- Phase tplh tphl 90% 90% 90% tr tphl tf tplh tf 90% tr Control (Low-Level Enabling) tpzl Waveform (See Note B) Waveform 2 (See Note B) tpzh tplz 90% tphz TAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES TAGE WAVEFORMS ENAB AND DISAB TIMES FOR -STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 0 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tplz and tphz are the same as tdis. F. tpzl and tpzh are the same as ten. G. tplh and tphl are the same as t pd. Figure. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 60 DALLAS, TEXAS 726
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