Higher Technological Institute 1 th of Ramadan City Department of Electrical & Computers Engineering Bass Booster Project Electronic Circuits (EEC 117)-G1 Student Name:... Student No.:... Under the supervision of Dr. Mustafa M. Shiple Moderated by: Eng. Ahmed Abdel Moneam June-August 215 [Total Marks is 15] page 1 of 2
Subject: Electronic Circuits /(EEC 117) Term: June - August 215 1 Introduction The bass booster circuit is divided into two main sections; High frequency section and bass (low frequency) section. The high frequency section contains a BJT amplifier and the bass section contains Op Amp as an inverting amplifier. 1, 2, 3, 4 Bass voice sample : 2 Project Objectives This Project aims to analyze bass booster circuit analytically and simulate its behavior by PSpice tool. Moreover, the circuit should be implemented on breadboard and the output signals should be measured too. A comparison should be made between: Analytical solution, Simulation results, and laboratory measurements. 3 Bill of materials (BOM) Table 1: The bill of materials # Component Qty Description 1 ua741 or 2N2222 1 Op Amp 2 BC148 1 NPN Transistor 3 R1 = 15kΩ 1 Resistor 4 R2 = 6.8kΩ 1 Resistor 5 R3 = 1kΩ 1 Resistor 6 R4 = 22kΩ 1 Resistor 7 R5 = 1Ω 1 Resistor 8 R6 = 2.2KΩ 1 Resistor 9 V R1 = 1KΩ 1 Variable resistor 1 V R2 = 1KΩ 1 Variable resistor 11 C1C3 =.1µF 3 Capacitor 12 C4C6 = 1µF/16V 3 Capacitor 1 Build a Great Sounding Audio Amplifier (with Bass Boost) 2 Bass Booster 3 Bass Booster Circuit 4 Bass Booster Topic: Bass Booster Project Good Luck page 2 of 2
Subject: Electronic Circuits /(EEC 117) Term: June - August 215 4 High frequency Amplifier Procedure: 4.1 DC and Ac Analysis 1. Consider the amplifier in Figure 1, Calculate all currents and voltages(hint: use the value of β = 1 and V BE =.7V ). Figure 1: High frequency Amplifier 2. Draw the ac equivalent circuit, and Calculate the voltage gain (A v ), input impedance (Z i ), and output impedance Z o. Topic: Bass Booster Project Good Luck page 3 of 2
Subject: Electronic Circuits /(EEC 117) Term: June - August 215 4.2 Experiment Analysis 1. Construct the circuit in Figure (1) on Pspice and on a breadboard. 2. By using power supply 12V and Voltmeter (AVO), Measure all currents in the circuit (I B, I C ). 3. To measure Z i you could insert a series resistor (1KΩ) 5. See Figure 2. Figure 2: Measuring Input Impedance 4. To measure Z o ; recall (Z o R L ); you could remove R L and insert it again. In each trial calculate the output voltage. 5. By using the measurement results, Calculate β. 6. Fill the Table 2. Table 2: The comparison of CE amplifier parameters # analytical analysis Simulated Measured I C I B V CE β A v Z i Z o 5 Input Impedance Measurement and Calculator Topic: Bass Booster Project Good Luck page 4 of 2
Subject: Electronic Circuits /(EEC 117) Term: June - August 215 5 Low Frequency Amplifier Procedure: 5.1 DC Analysis 1. Consider the amplifier in Figure 3, Calculate all currents and voltages. Figure 3: Bass Booster 2. Calculate the voltage gain (A v ), input impedance (Z i ), and output impedance Z o. 5.2 Experiment Analysis 1. Construct the circuit in Figure 3 on Pspice and on a breadboard. 2. By using power supply 12V, 12V and Voltmeter (AVO), Measure all currents in the circuit. 3. By using the measurement results, Calculate gain. 6 Bass booster main block diagram and circuit: 1. Integrate Low and high amplifiers. Topic: Bass Booster Project Good Luck page 5 of 2
Subject: Electronic Circuits /(EEC 117) Term: June - August 215 Figure 4: Bass Booster 2. Construct the circuit in Figure 4 on Pspice and on a breadboard. 3. Test the bass booster circuit. Topic: Bass Booster Project Good Luck page 6 of 2
1 Product Folder Sample & Buy Technical Documents Tools & Software Support & Community OFFSET N1 ua741 SLOS94E NOVEMBER 197 REVISED JANUARY 215 µa741 General-Purpose Operational Amplifiers 1 Features 3 Description 1 Short-Circuit Protection The µa741 device is a general-purpose operational amplifier featuring offset-voltage null capability. Offset-Voltage Null Capability Large Common-Mode and Differential Voltage The high common-mode input voltage range and the Ranges absence of latch-up make the amplifier ideal for voltage-follower applications. The device is short- No Frequency Compensation Required circuit protected and the internal frequency No Latch-Up compensation ensures stability without external components. A low value potentiometer may be 2 Applications connected between the offset null inputs to null out the offset voltage as shown in Figure 11. DVD Recorders and Players Pro Audio Mixers The µa741c device is characterized for operation from C to 7 C. The µa741m device (obsolete) is characterized for operation over the full military temperature range of 55 C to 125 C. 4 Simplified Schematic Device Information (1) PART NUMBER PACKAGE (PIN) BODY SIZE (NOM) SOIC (8) 4.9 mm 3.91 mm µa741x PDIP (8) 9.81 mm 6.35 mm SO (8) 6.2 mm 5.3 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. IN + IN OFFSET N2 + OUT An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLOS94E NOVEMBER 197 REVISED JANUARY 215 www.ti.com Table of Contents 1 Features... 1 2 Applications... 1 3 Description... 1 4 Simplified Schematic... 1 5 Revision History... 2 6 Pin Configurations and Functions... 3 7 Specifications... 4 7.1 Absolute Maximum Ratings... 4 7.2 Recommended Operating Conditions... 4 7.3 Electrical Characteristics μa741c, μa741m... 5 7.4 Electrical Characteristics μa741y... 6 7.5 Switching Characteristics μa741c, μa741m... 6 7.6 Switching Characteristics μa741y... 6 7.7 Typical Characteristics... 7 8 Detailed Description... 9 8.1 Overview... 9 8.2 Functional Block Diagram... 9 8.3 Feature Description... 1 8.4 Device Functional Modes... 1 8.5 µa741y Chip Information... 1 9 Application and Implementation... 11 9.1 Application Information... 11 9.2 Typical Application... 11 1 Power Supply Recommendations... 13 11 Layout... 13 11.1 Layout Guidelines... 13 11.2 Layout Example... 13 12 Device and Documentation Support... 15 12.1 Trademarks... 15 12.2 Electrostatic Discharge Caution... 15 12.3 Glossary... 15 13 Mechanical, Packaging, and Orderable Information... 15 5 Revision History Changes from Revision D (February 214) to Revision E Page Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.... 1 Moved Typical Characteristics into Specifications section.... 7 Changes from Revision C (January 214) to Revision D Page Fixed Typical Characteristics graphs to remove extra lines.... 7 Changes from Revision B (September 2) to Revision C Page Updated document to new TI data sheet format - no specification changes.... 1 Deleted Ordering Information table.... 1 2 Submit Documentation Feedback Copyright 197 215, Texas Instruments Incorporated
www.ti.com SLOS94E NOVEMBER 197 REVISED JANUARY 215 6 Pin Configurations and Functions OFFSET N1 IN IN+ V CC µa741m... J PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 14 13 12 11 1 9 8 V CC+ OUT OFFSET N2 µa741m... JG PACKAGE µ A741C, µ A741I... D, P, OR PW PACKAGE (TOP VIEW) OFFSET N1 IN IN+ V CC 1 2 3 4 8 7 6 5 V CC+ OUT OFFSET N2 µa741m... U PACKAGE (TOP VIEW) µa741m... FK PACKAGE (TOP VIEW) OFFSET N1 IN IN+ V CC 1 2 3 4 5 1 9 8 7 6 V CC+ OUT OFFSET N2 IN IN+ 3 2 1 2 19 4 18 5 6 7 OFFSET N1 17 16 15 8 14 9 1 11 12 13 V CC+ OUT V CC OFFSET N2 No internal connection Pin Functions PIN NAME JG, D, P, or TYPE DESCRIPTION J U FK PW IN+ 5 3 4 7 I Noninverting input IN 4 2 3 5 I Inverting input 1, 2, 8, 1,3,4,6,8,9,11,13,1 12, 13, 8 1, 9, 1 4,16,18,19,2 14 Do not connect OFFSET N1 3 1 2 2 I External input offset voltage adjustment OFFSET N2 9 5 6 12 I External input offset voltage adjustment OUT 1 6 7 15 O Output V CC + 11 7 8 17 Positive supply V CC 6 4 5 1 Negative supply Copyright 197 215, Texas Instruments Incorporated Submit Documentation Feedback 3
SLOS94E NOVEMBER 197 REVISED JANUARY 215 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over virtual junction temperature range (unless otherwise noted) (1) µa741c µa741m MIN MAX MIN MAX V CC Supply voltage (2) 18 18 22 22 C V ID Differential input voltage (3) 15 15 3 3 V V I Input voltage, any input (2)(4) 15 15 15 15 V Voltage between offset null (either OFFSET N1 or OFFSET N2) and V CC 15 15.5.5 V Duration of output short circuit (5) Unlimited Continuous total power dissipation See Table 1 T A Operating free-air temperature range 7 55 125 C Case temperature for 6 seconds FK package N/A N/A 26 C Lead temperature 1.6 mm (1/16 inch) from case for 6 seconds Lead temperature 1.6 mm (1/16 inch) from case for 1 seconds J, JG, or U package N/A N/A 3 C D, P, or PS package 26 N/A N/A C T stg Storage temperature range 65 15 65 15 C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, unless otherwise noted, are with respect to the midpoint between V CC+ and V CC. (3) Differential voltages are at IN+ with respect to IN. (4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. (5) The output may be shorted to ground or either power supply. For the µa741m only, the unlimited duration of the short circuit applies at (or below) 125 C case temperature or 75 C free-air temperature. 7.2 Recommended Operating Conditions UNIT MIN MAX UNIT V CC+ 5 15 Supply voltage V CC 5 15 µa741c 7 T A Operating free-air temperature C µa741m 55 125 Table 1. Dissipation Ratings Table T A 25 C TA = 7 C DERATING DERATE T A = 85 C T A = 125 C PACKAGE POWER POWER FACTOR ABOVE T A POWER RATING POWER RATING RATING RATING D 5 mw 5.8 mw/ C 64 C 464 mw 377 mw N/A FK 5 mw 11. mw/ C 15 C 5 mw 5 mw 275 mw J 5 mw 11. mw/ C 15 C 5 mw 5 mw 275 mw JG 5 mw 8.4 mw/ C 9 C 5 mw 5 mw 21 mw P 5 mw N/A N/A 5 mw 5 mw N/A PS 525 mw 4.2 mw/ C 25 C 336 mw N/A N/A U 5 mw 5.4 mw/ C 57 C 432 mw 351 mw 135 mw V 4 Submit Documentation Feedback Copyright 197 215, Texas Instruments Incorporated
www.ti.com SLOS94E NOVEMBER 197 REVISED JANUARY 215 7.3 Electrical Characteristics μa741c, μa741m at specified virtual junction temperature, V CC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS T A (1) μa741c μa741m MIN TYP MAX MIN TYP MAX 25 C 1 6 1 5 V IO Input offset voltage V O = mv Full range 7.5 ±15 6 ΔV IO(adj) Offset voltage adjust range V O = 25 C ±15 2 2 mv 25 C 2 2 5 I IO Input offset current V O = na Full range 3 5 25 C 8 5 8 5 I IB Input bias current V O = na Full range 8 15 25 C ±12 ±13 ±12 ±13 V ICR Common-mode input voltage range V Full range ±12 ±12 R L = 1 kω 25 C ±12 ±14 ±12 ±14 R L 1 kω Full range ±12 ±12 V OM Maximum peak output voltage swing V R L = 2 kω 25 C ±1 ±1 ±13 A VD R L 2kΩ Full range ±1 ±1 Large-signal differential voltage R L 2kΩ 25 C 2 2 5 2 amplification V O = ±1 V Full range 15 25 r i Input resistance 25 C.3 2.3 2 MΩ r o Output resistance V O =, See (2) 25 C 75 75 Ω C i Input capacitance 25 C 1.4 1.4 pf 25 C 7 9 7 9 CMRR Common-mode rejection ratio V IC = V ICRmin db Full range 7 7 25 C 3 15 3 15 k SVS Supply voltage sensitivity (ΔV IO /ΔV CC ) V CC = ±9 V to ±15 V µv/v Full range 15 15 I OS Short-circuit output current 25 C ±25 ±4 ±25 ±4 ma 25 C 1.7 2.8 1.7 2.8 I CC Supply current V O =, No load ma Full range 3.3 3.3 25 C 5 85 5 85 P D Total power dissipation V O =, No load mw Full range 1 1 (1) All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full range for the µa741c is C to 7 C and the µa741m is 55 C to 125 C. (2) This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback. UNIT V/mV Copyright 197 215, Texas Instruments Incorporated Submit Documentation Feedback 5
SLOS94E NOVEMBER 197 REVISED JANUARY 215 www.ti.com 7.4 Electrical Characteristics μa741y at specified virtual junction temperature, V CC± = ±15 V, T A = 25 C (unless otherwise noted) (1) μa741y PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V IO Input offset voltage V O = 1 5 mv ΔV IO(adj) Offset voltage adjust range V O = ±15 mv I IO Input offset current V O = 2 2 na I IB Input bias current V O = 8 5 na V ICR Common-mode input voltage range ±12 ±13 V R L = 1 kω ±12 ±14 V OM Maximum peak output voltage swing V R L = 2 kω ±1 ±13 A VD Large-signal differential voltage amplification R L 2kΩ 2 2 V/mV r i Input resistance.3 2 MΩ r o Output resistance V O =, See (1) 75 Ω C i Input capacitance 1.4 pf CMRR Common-mode rejection ratio V IC = V ICRmin 7 9 db k SVS Supply voltage sensitivity (ΔV IO /ΔV CC ) V CC = ±9 V to ±15 V 3 15 µv/v I OS Short-circuit output current ±25 ±4 ma I CC Supply current V O =, No load 1.7 2.8 ma P D Total power dissipation V O =, No load 5 85 mw (1) This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback. 7.5 Switching Characteristics μa741c, μa741m over operating free-air temperature range, V CC± = ±15 V, T A = 25 C (unless otherwise noted) µa741c µa741m PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX t r Rise time V I = 2 mv, R L = 2 kω,.3.3 µs Overshoot factor C L = 1 pf, See Figure 1 5% 5% V I = 1 V, R L = 2 kω, SR Slew rate at unity gain.5.5 V/µs C L = 1 pf, See Figure 1 7.6 Switching Characteristics μa741y over operating free-air temperature range, V CC± = ±15 V, T A = 25 C (unless otherwise noted) µa741y PARAMETER TEST CONDITIONS UNIT MIN TYP MAX t r Rise time V I = 2 mv, R L = 2 kω,.3 µs Overshoot factor C L = 1 pf, See Figure 1 5% V I = 1 V, R L = 2 kω, SR Slew rate at unity gain.5 V/µs C L = 1 pf, See Figure 1 6 Submit Documentation Feedback Copyright 197 215, Texas Instruments Incorporated
V I IB Input Bias Current na Maximum Peak Output Voltage V OM I ua741 www.ti.com SLOS94E NOVEMBER 197 REVISED JANUARY 215 7.7 Typical Characteristics Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. VI OUT V IN + INPUT VOLTAGE WAVEFDORM CL = 1 pf RL = 2 kω TEST CIRCUIT Figure 1. Rise Time, Overshoot, and Slew Rate Input Offset Current na IO 1 9 8 7 6 5 4 3 2 VCC+ = 15 V VCC = 15 V 4 35 3 25 2 15 1 VCC+ = 15 V VCC = 15 V 1 5 V 6 4 2 2 4 6 8 1 12 14 ±14 ±13 ±12 ±11 ±1 ±9 ±8 ±7 ±6 ±5 ±4.1 TA Free-Air Temperature C Figure 2. Input Offset Current vs Free-Air Temperature VCC+ = 15 V VCC = 15 V TA = 25 C.2.4.7 1 RL Load Resistance kω Figure 4. Maximum Output Voltage vs Load Resistance 2 4 7 1 Maximum Peak Output Voltage V OM ±2 ±18 ±16 ±14 ±12 ±1 ±8 ±6 ±4 ±2 6 4 2 2 4 6 8 1 12 14 1 VCC+ = 15 V VCC = 15 V RL = 1 kω TA = 25 C TA Free-Air Temperature C Figure 3. Input Bias Current vs Free-Air Temperature 1k 1k 1k f Frequency Hz Figure 5. Maximum Peak Output Voltage vs Frequency 1M Copyright 197 215, Texas Instruments Incorporated Submit Documentation Feedback 7
SLOS94E NOVEMBER 197 REVISED JANUARY 215 www.ti.com Typical Characteristics (continued) Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. A VD Open-Loop Signal Differential Voltage Amplification V/mV CMRR Common-Mode Rejection Ratio db 4 2 1 1 9 8 7 6 5 4 3 2 1 4 2 1 1 VO = ±1 V RL = 2 kω TA = 25 C 2 4 1 6 8 VCC+ = 15 V VCC = 15 V BS = 1 kω TA = 25 C 1k 1M 1M f Frequency Hz Figure 8. Common-Mode Rejection Ratio vs Frequency 1 12 Input and Output Voltage V 14 VCC± Supply Voltage V Figure 6. Open-Loop Signal Differential Voltage Amplification vs Supply Voltage 8 6 4 2 2 4 16 18 2 VO VI A VD Open-Loop Signal Differential Voltage Amplification db Output Voltage mv V O 11 1 9 8 7 6 5 4 3 2 1 1 1 f Frequency Hz Figure 7. Open-Loop Large-Signal Differential Voltage Amplification vs Frequency 28 24 2 16 12 8 4 4 VCC+ = 15 V VCC = 15 V RL = 2 kω CL = 1 pf TA = 25 C 1% 1 1 1k 1k 1k 9%.5 tr 1 VCC+ = 15 V VCC = 15 V VO = ±1 V RL = 2 kω TA = 25 C VCC+ = 15 V VCC = 15 V RL = 2 kω CL = 1 pf TA = 25 C 1.5 2 1M 1M 2.5 t Time - µs Figure 9. Output Voltage vs Elapsed Time 6 8 1 2 3 4 5 6 7 8 9 t Time ms Figure 1. Voltage-Follower Large-Signal Pulse Response 8 Submit Documentation Feedback Copyright 197 215, Texas Instruments Incorporated
www.ti.com SLOS94E NOVEMBER 197 REVISED JANUARY 215 8 Detailed Description 8.1 Overview The µa741 device is a general-purpose operational amplifier featuring offset-voltage null capability. The high common-mode input voltage range and the absence of latch-up make the amplifier ideal for voltagefollower applications. The device is short-circuit protected and the internal frequency compensation ensures stability without external components. A low value potentiometer may be connected between the offset null inputs to null out the offset voltage as shown in Figure 11. The µa741c device is characterized for operation from C to 7 C. The µa741m device (obsolete) is characterized for operation over the full military temperature range of 55 C to 125 C. 8.2 Functional Block Diagram VCC+ IN IN+ OUT OFFSET N1 OFFSET N2 VCC Component Count Transistors 22 Resistors 11 Diode 1 Capacitor 1 Copyright 197 215, Texas Instruments Incorporated Submit Documentation Feedback 9
SLOS94E NOVEMBER 197 REVISED JANUARY 215 www.ti.com 8.3 Feature Description 8.3.1 Offset-Voltage Null Capability The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, currentgain betas (β), collector or emitter resistors, etc. The input offset pins allow the designer to adjust for these mismatches by external circuitry. See the Application and Implementation section for more details on design techniques. 8.3.2 Slew Rate The slew rate is the rate at which an operational amplifier can change its output when there is a change on the input. The µa741 has a.5-v/μs slew rate. Parameters that vary significantly with operating voltages or temperature are shown in the Typical Characteristics graphs. 8.4 Device Functional Modes The µa741 is powered on when the supply is connected. It can be operated as a single supply operational amplifier or dual supply amplifier depending on the application. 8.5 µa741y Chip Information This chip, when properly assembled, displays characteristics similar to the µa741c. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS (8) (7) (6) IN+ IN OFFSET N1 OFFSET N2 (3) (2) (1) (5) + VCC+ (7) (4) VCC (6) OUT 45 (5) (1) (4) CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 4 MINIMUM (2) (3) TJmax = 15 C. TOLERAES ARE ±1%. 36 ALL DIMENSIONS ARE IN MILS. 1 Submit Documentation Feedback Copyright 197 215, Texas Instruments Incorporated
www.ti.com SLOS94E NOVEMBER 197 REVISED JANUARY 215 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, currentgain betas (β), collector or emitter resistors, etc. The input offset pins allow the designer to adjust for these mismatches by external circuitry. These input mismatches can be adjusted by putting resistors or a potentiometer between the inputs as shown in Figure 13. A potentiometer can be used to fine tune the circuit during testing or for applications which require precision offset control. More information about designing using the input-offset pins, see the application note Nulling Input Offset Voltage of Operational Amplifiers, SLOA45. IN+ IN OFFSET N1 + OUT OFFSET N2 1 kω To VCC Figure 11. Input Offset Voltage Null Circuit 9.2 Typical Application The voltage follower configuration of the operational amplifier is used for applications where a weak signal is used to drive a relatively high current load. This circuit is also called a buffer amplifier or unity gain amplifier. The inputs of an operational amplifier have a very high resistance which puts a negligible current load on the voltage source. The output resistance of the operational amplifier is almost negligible, so it can provide as much current as necessary to the output load. 1 k 12 V + VOUT VIN Figure 12. Voltage Follower Schematic 9.2.1 Design Requirements Output range of 2 V to 11.5 V Input range of 2 V to 11.5 V Copyright 197 215, Texas Instruments Incorporated Submit Documentation Feedback 11
SLOS94E NOVEMBER 197 REVISED JANUARY 215 www.ti.com Typical Application (continued) Resistive feedback to negative input 9.2.2 Detailed Design Procedure 9.2.2.1 Output Voltage Swing The output voltage of an operational amplifier is limited by its internal circuitry to some level below the supply rails. For this amplifier, the output voltage swing is within ±12 V, which accommodates the input and output voltage requirements. 9.2.2.2 Supply and Input Voltage For correct operation of the amplifier, neither input must be higher than the recommended positive supply rail voltage or lower than the recommended negative supply rail voltage. The chosen amplifier must be able to operate at the supply voltage that accommodates the inputs. Because the input for this application goes up to 11.5 V, the supply voltage must be 12 V. Using a negative voltage on the lower rail rather than ground allows the amplifier to maintain linearity for inputs below 2 V. 9.2.3 Application Curves for Output Characteristics VOUT (V) 12 1 8 6 4 2 2 4 6 8 1 12 VIN (V) C1 IIO (ma).45.4.35.3.25.2.15.1.5..5 2 4 6 8 1 12 VIN (V) Figure 13. Output Voltage vs Input Voltage Figure 14. Current Drawn Input of Voltage Follower (I IO ) vs Input Voltage C2.45.4.35.3 ICC (ma).25.2.15.1.5. 2 4 6 8 1 12 VIN (V) Figure 15. Current Drawn from Supply (I CC ) vs Input Voltage C3 12 Submit Documentation Feedback Copyright 197 215, Texas Instruments Incorporated
www.ti.com SLOS94E NOVEMBER 197 REVISED JANUARY 215 1 Power Supply Recommendations The μa741 is specified for operation from ±5 to ±15 V; many specifications apply from C to 7 C. The Typical Characteristics section presents parameters that can exhibit significant variance with regard to operating voltage or temperature. CAUTION Supply voltages larger than ±18 V can permanently damage the device (see the Absolute Maximum Ratings). Place.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout Guidelines. 11 Layout 11.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry. Connect low-esr,.1-μf ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications. Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to Circuit Board Layout Techniques, SLOA89. To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace. Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Layout Example. Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. 11.2 Layout Example VIN RIN + VOUT RG RF Figure 16. Operational Amplifier Schematic for Noninverting Configuration Copyright 197 215, Texas Instruments Incorporated Submit Documentation Feedback 13
SLOS94E NOVEMBER 197 REVISED JANUARY 215 www.ti.com Layout Example (continued) Place components close to device and to each other to reduce parasitic errors Run the input traces as far away from the supply lines as possible RF GND RG IN1 VCC+ VS+ Use low-esr, ceramic bypass capacitor VIN IN1+ OUT RIN Only needed for dual-supply operation GND VCC VS- (or GND for single supply) VOUT GND Ground (GND) plane on another layer Figure 17. Operational Amplifier Board Layout for Noninverting Configuration 14 Submit Documentation Feedback Copyright 197 215, Texas Instruments Incorporated