Sony IMX018 CMOS Image Sensor Imager Process Review

September 6, 2006 Sony IMX018 CMOS Image Sensor Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com

Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Package and Die 2.1 Package 2.2 Die 2.3 Die Features 3 Process 3.1 General Structure 3.2 Organic Layers 3.3 Bond Pads 3.4 Dielectrics 3.5 Metals 3.6 Vias and Contacts 3.7 MOS Transistors and Poly 3.8 Poly Capacitors 3.9 Isolation 3.10 Wells, Epi and Substrate 4 Pixel Array Analysis 4.1 Pixel Schematic 4.2 Pixel Array Plan View Analysis 4.3 Pixel Array Cross-Sectional Analysis 5 Embedded SRAM Analysis 5.1 Cell Schematic 5.2 SRAM Plan View Analysis 5.3 SRAM Cross-Sectional Analysis

Imager Process Review 6 Materials Analysis 6.1 TEM-EDS Analysis of Dielectrics and Contact Silicide in Pixel 7 Critical Dimension 7.1 Package and Die 7.2 Vertical Dimensions 7.3 Horizontal Dimensions 8 References Report Evaluation

Overview 1-1 1 Overview 1.1 List of Figures 2 Package and Die 2.1.1 Sony Ericsson K800i Cell Phone 2.1.2 Inside Sony Ericsson K800i Cell Phone 2.1.3 IMX018 CIS Assembly Top View 2.1.4 IMX018 CIS Assembly Side View 2.1.5 IMX018 CIS Assembly X-Ray Top View 2.1.6 IMX018 CIS Assembly X-Ray Side View 2.1.7 IMX018 Die On PCB 2.1.8 IMX018 Die On PCB X-Ray Top View 2.2.1 Die Photograph Intact 2.2.2 Die Photograph Decapsulated 2.2.3 Die Markings 2.2.4 Annotated Die Photograph 2.3.1 Die Corner 2.3.2 Die Corner a 2.3.3 Die Corner b 2.3.4 Die Corner c 2.3.5 Die Corner d 2.3.6 Die Edge 2.3.7 Minimum Pitch Bond Pads 2.3.8 Bond Pads Detail 2.3.9 Pixel Array Corner a 2.3.10 Pixel Array Corner b 2.3.11 Pixel Array Corner c 2.3.12 Pixel Array Corner d 2.3.13 ADC and Logic Area 3 Process 3.1.1 Array General Structure 3.1.2 Peripheral General Structure 3.1.3 Die Edge and Die Seal 3.1.4 Die Seal and Organic Layer Edge 3.2.1 Blue Filter Edge 3.2.2 Blue-Purple Filter Boundary 3.2.3 Purple-Blue Filter Boundary 3.2.4 RGB Color Filter Edge 3.3.1 Bond Pad 3.3.2 Bond Pad Edge 3.3.3 Bond Pad Edge Detail

Overview 1-2 3.4.1 Peripheral Passivation and ILD 3 3.4.2 Pixel Array Passivation/Lenses and ILD 3 3.4.3 Pixel Array Passivation/Lenses and ILD 3 TEM 3.4.4 Pixel Array Passivation/Lenses Detail TEM 3.4.5 ILD 3 TEM 3.4.6 ILD 2 3.4.7 ILD 2 TEM 3.4.8 ILD 1 3.4.9 ILD 1 TEM 3.4.10 PMD and STI in Periphery 3.4.11 PMD and Deposited Oxide Isolation in Pixel Array 3.4.12 PMD-1 and Pixel AR Layer 3.5.1 Minimum Peripheral Metal 3 3.5.2 Minimum Pixel Array Metal 3 3.5.3 Pixel Array Metal 3 TEM 3.5.4 Minimum Peripheral Metal 2 3.5.5 Minimum Pixel Array Metal 2 3.5.6 Pixel Array Metal 2 TEM 3.5.7 Minimum Peripheral Metal 1 3.5.8 Minimum Pixel Array Metal 1 3.5.9 Pixel Array Metal 1 TEM 3.6.1 Stacked Minimum Pitch Vias 3.6.2 Minimum Pitch Via 2s 3.6.3 Via 2 TEM 3.6.4 Minimum Pitch Via 1s 3.6.5 Stacked Via 1s and Contacts 3.6.6 Minimum Pitch Contacts to Poly 3.6.7 Minimum Pitch Contacts to Substrate 3.6.8 Contact to Poly TEM 3.6.9 Contact to Substrate TEM 3.7.1 Peripheral NMOS (Si Etch) 3.7.2 Peripheral PMOS (Si Etch) 3.7.3 Pixel Array NMOS Transistors (Si Etch) 3.7.4 Pixel Array NMOS Transistor (Glass Etch) 3.7.5 Pixel Array NMOS TEM 3.7.6 Pixel Array NMOS Detail TEM 3.7.7 Pixel Array Gate Oxide TEM 3.8.1 Poly MIS Capacitor 3.8.2 Poly MIS Capacitor Detail 3.9.1 Minimum Width STI 3.9.2 Poly over STI 3.9.3 Minimum Width Deposited Oxide Isolation 3.9.4 Deposited Oxide Isolation TEM 3.9.5 Deposited Oxide Isolation Detail TEM

Overview 1-3 3.10.1 Peripheral and Pixel Array Wells SCM 3.10.2 Peripheral P-well SEM 3.10.3 Peripheral N-well SEM 3.10.4 SRP of Peripheral P-Well 3.10.5 SRP of N-Epi and NBL 3.10.6 Pixel Array Epi and Substrate SCM 3.10.7 SRP in Pixel Array 4 Pixel Array Analysis 4.1.1 Pixel Schematic Circuit 4.2.1 Pixel Array Corner Optical 4.2.2 Pixel Array Lenses 4.2.3 Pixel Array Lenses AFM Tilt-View 4.2.4 Pixel Array Lenses AFM Cross-Section 4.2.5 Pixel Array Passivation Lenses 4.2.6 Pixel Array at Metal 3 Optical 4.2.7 Pixel Array at Metal 3 4.2.8 Pixel Array at Metal 2 4.2.9 Pixel Array at Metal 1 4.2.10 Pixel Array at Poly 4.2.11 Pixel Array at Poly Detail 4.2.12 Pixel Array at Substrate 4.2.13 Pixel Array at Substrate SCM 4.2.14 Pixel Array at Substrate Detail SCM 4.3.1 Pixel at Poly Showing Cross-Sectional Planes Plan View 4.3.2 Pixel Array General Structure (P1S1 Blue-Green Filters) 4.3.3 Pixel Array General Structure (P1S1 Red-Green Filters) 4.3.4 Pixel Array Right Edge (P1S1) 4.3.5 Pixel Array Bottom Edge (P2S2) 4.3.6 Lenses and Blue and Green Color Filters (P1S1) 4.3.7 Lenses and Red-Green Color Filters (P1S1) 4.3.8 Nitride Passivation Lenses (P1S2) 4.3.9 General Structure Transfer Transistors (P1S1) 4.3.10 General Structure T5 Transistor (P1S1) 4.3.11 General Structure T6 and T7 Transistors (P1S1) 4.3.12 T1 and T2 Transfer Transistors (P1S4) 4.3.13 Pixel Through Transfer Transistors SCM (P1S4) 4.3.14 Pixel Through Photocathode (P1S1) 4.3.15 Reset Transistor T5 (P1S1) 4.3.16 Source Follower Transistor T6 and Row Select Transistor T7 (P1S1) 4.3.17 Reset Transistor T5 Width (P1S2) 4.3.18 Source Follower Transistor T6 Width (P1S2) 4.3.19 Row Select Transistor T7 Width (P1S2) 4.3.20 Row Select Transistor T7 Gate Contact (P1S2)

Overview 1-4 5 Embedded SRAM Analysis 5.1.1 Die Photo Showing SRAM Location 5.1.2 6T SRAM Cell 5.2.1 SRAM at Metal 2 5.2.2 SRAM at Metal 2 Detail 5.2.3 SRAM at Metal 1 5.2.4 SRAM at Metal 1 Detail 5.2.5 SRAM at Poly Detail 5.3.1 SRAM Pull Up Transistor Detail 6 Materials Analysis 6.1.1 TEM-EDS Analysis Areas 6.1.2 TEM-EDS of Passivation/Lens 3 Oxide 6.1.3 TEM-EDS of Passivation/Lens 2 Nitride 6.1.4 TEM-EDS of Passivation/Lens 1 Nitride 6.1.5 TEM-EDS of ILD 3-3 Oxide 6.1.6 TEM-EDS of ILD 3-1 Oxide 6.1.7 TEM-EDS of ILD 2-2 Oxide 6.1.8 TEM-EDS of ILD 2-1 Oxide 6.1.9 TEM-EDS of ILD 1-2 Oxide 6.1.10 TEM-EDS of ILD 1-1 Oxide 6.1.11 TEM-EDS of PMD-2 Oxide 6.1.12 TEM-EDS of PMD-1 Oxynitride 6.1.13 TEM-EDS of SWS Nitride 6.1.14 TEM-EDS of Contact Silicide

Overview 1-5 1.2 List of Tables 1 Overview 1.5.1 Device Summary 1.6.1 Summary of Major Findings 2 Package and Die 2.3.1 Package and Die Dimensions 3 Process 3.4.1 Dielectric Composition and Thicknesses 3.5.1 Metallization Composition and Thicknesses 3.5.2 Minimum Metals Peripheral Horizontal Dimensions 3.5.3 Minimum Metals Pixel Array Horizontal Dimensions 3.6.1 Via and Contact Horizontal Dimensions 3.7.1 Transistor and Polysilicon Horizontal Dimensions 3.7.2 Transistor and Polysilicon Vertical Dimensions 3.9.1 Isolation Horizontal Dimension 3.10.1 Wells and Epi Vertical Dimension 4 Pixel Array Analysis 4.2.1 Pixel Horizontal Dimensions 4.3.1 Pixel Vertical Dimensions 4.3.2 Transistor Dimensions in Pixel Array 5 Embedded SRAM Analysis 5.3.1 SRAM Transistor Sizes 7 Critical Dimension 7.1.1 Package and Die Dimensions 7.2.1 Dielectric Composition and Thicknesses 7.2.2 Metallization Composition and Thicknesses 7.2.3 Transistor and Polysilicon Vertical Dimensions 7.2.4 Wells and Epi Vertical Dimension 7.3.1 Minimum Metals Peripheral Horizontal Dimensions 7.3.2 Minimum Metals Pixel Array Horizontal Dimensions 7.3.3 Via and Contact Horizontal Dimensions 7.3.4 Transistor and Polysilicon Horizontal Dimensions 7.3.5 Isolation Horizontal Dimension

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