Ehaced Performace Fully-Sythesizable ADC for Efficiet Digital Voltage-Mode Cotrol Tom Urki, Studet Member, IEEE, Eli Abramov, Studet Member, IEEE, ad Mor Mordechai Peretz, Member, IEEE The Ceter for Power Electroics ad Mixed-Sigal IC, Departmet of Electrical ad Computer Egieerig Be-Gurio Uiversity of the Negev, P.O. Box 653, Beer-Sheva, 8410501 Israel tomur@post.bgu.ac.il, eliab@post.bgu.ac.il, morp@ee.bgu.ac.il http://www.ee.bgu.ac.il/~pemic Abstract This paper itroduces a ew approach for sigma-delta based aalog to digital coverter (SDADC) with ehaced performace suitable for digital voltage regulatio. The ew ADC icreases the umber of digital represetatios of the sampled sigal per coversio cycle, for the same oversamplig clock frequecy. This advatage also traslates to reduced power cosumptio for the same coversio rate sice slower clock ca be employed to obtai similar coversio rate. A all-digital, fully-sythesizable realizatio of the ew architecture sets it as a attractive cadidate for may digital applicatio platforms, ragig from housekeepig ad moitorig, ad eve as the primary ADC for the compesatio loop. High accuracy ad fast effective coversio rate have bee verified through simulatio ad experimets, demostratig wide rage of sampled voltages with less tha 1% error for wide operatio rage. A experimetal closed-loop operatio o a voltage-mode (VM) buck coverter, with the digital voltage loop implemeted o FPGA, demostrates superior operatio over a covetioal SD operatio. The digital cotroller core icludig the ew SDADC have bee also implemeted as IC by a automated sythesis process ad place-ad route tools i a 0.18μm 5V CMOS process resultig i effective silico area of 0.07mm. Keywords - Sigma-delta modulator, itegrated circuit, aalog-digital coverter, voltage-mode cotrol, digital cotrol. I. INTRODUCTION Sigma-Delta modulators ad coverters are major eablers of the digital techology ramp up datig back to the late 1980s. The appearace of low-cost ad reliable meas to traslate cotiuous-time sigals oto the sample-data domai revolutioized the field of low ad medium frequecy rage sigal processig ad i particular the audio world [1]-[4]. Nowadays, the availability of simple ad efficiet iterface from the aalog world to the digital hardware is still extremely importat i all fields of electroics. I particular for power maagemet, where fast performace with reasoable cost is critical, aalog implemetatio of the cotroller core is still predomiat [5], [6]. I the last decade or so there has bee a sigificat progress i digital power maagemet thaks to the developmet of dedicated hardware that is tailored to its uique eeds [7]-[1]. With the itegratio of digital techology, the power maagemet system trasforms as well. Now comprises desig flexibility, scalability, ad upgrade optios; commuicatio ad power quality loggig; plug-ad-play operatio; ad of course, improved performace. Sice a typical digital compesatio loop must have at least comparable dyamics to its aalog precursor, a highperformace peripherals are essetial, i.e., the digital PWM (DPWM) ad ADC [7], [8], [11], [1]. Coversio of 10bit word withi 100s is a commo requiremet to accommodate switchig frequecies i the rage of 300kHz (where the cotrol badwidth is approximately 1/6f s). As a cosequece, high-performace ADCs such as pipelie or successive approximatio are employed [13], [14]. Sice Sigma-Delta aalog to digital coverters (SDADC) are operated through oversamplig cocept ad require very high speed clock, i the order of 100s MHz to geerate comparable coversio rate, they are typically avoided for compesatio purposes ad mostly used for slower tasks such as housekeepig ad user iterfaces. O the other had, the very simple hardware of a SDADC is a attractive feature, which should be further pursued. A typical voltage-mode (VM) compesatio loop for switch-mode power supply (SMPS), as illustrated for a buck coverter i Fig. 1, operates o the basis of oe sample per cycle to regulate the average value of the output voltage ad fully utilize the correctio rate (switchig frequecy) of the loop. For a compesator based o covetioal SDADC, this calls for oversamplig clock of at least time the switchig frequecy (where is the umber of ADC bits) with a bit stream of similar size. However, sice covergece of a liear cotrol scheme takes several switchig cycles, this strict requiremet are eased i this study by tradig some of the accuracy with faster readig. The data of the log strig, for precisio, is geerated out of lower resolutio, shorter strigs. Iformatio of the output voltage status cotiuously updates the loop, ad sice it is of shorter duratio, the potetial deviatio i the output voltage is lower which agrees with the mometary lower resolutio readig. I this way, with mior hardware additios, a SDADC ca be 978-1-5386-5541-/18/$31.00 018 IEEE
Fig. 1. Simplified schematic diagram of digital voltage-mode cotrol loop for a buck coverter utilizig the SDADC. cosidered as a attractive cadidate for various tasks, ad eve for core cotrol i digital voltage regulatio. The objective of this study is therefore to itroduce a modified architecture for Sigma-Delta Aalog to Digital Coversio. The SDADC digitizes wide rage of sampled voltages with high accuracy ad wide dyamic rage to capture fast variatios without sacrificig precisio. These attributes make the ew ADC suitable i digital voltage regulatio ad i particular for applicatios of Adaptive Voltage Scalig (AVS). It is a further objective of this study to delieate a simple all-digital voltage feedback loop, as i Fig. 1, implemeted o IC. The rest of the paper is orgaized as follows: sectio II details the architecture of the SDADC ad covers its priciple of operatio. The all-digital voltage loop compesatio is described sectio III. Sectio IV covers issues of practical implemetatio, icludig desig flow, IC layout, ad silico size estimatio. Experimetal system implemetatio ad validatio are preseted i sectio V. Sectio VI cocludes the paper. II. ENHANCED PERFORMANCE SDADC PRINCIPLE OF OPERATION The priciple of operatio of the modified SDADC is described i compariso to a covetioal SDADC ad with the aid of Figs. ad 3, which show a coceptual block diagram of the modified coversio scheme ad high-level operatio flowchart, respectively. It is assumed here that a first-order SD modulator is used to geerate a bit stream with average value that is proportioal to the sampled sigal v out(t). A detailed full-digital realizatio of the modulator will be described later i the practical implemetatio, Sectio IV. To produce a -bit digital value represetatio of the sampled sigal, the amout of oes of the bit-stream is stored i a mai -bit couter (see Fig. ). The couter acts as a sic Low-Pass Filter (LPF), ad resets at pre-determied itervals to perform decimatio [1]-[3]. The sampled output voltage v out(t) is traslated to a digital represetatio v out[]. I the SDADC of this study, the sampled sigal is updated several times, with coarser resolutio, durig a full coversio cycle. These mid-cycle time updates are geerated by a state machie combied with a digital logic block, ad pre-defied accordig to the overall umber of bits of the couter. A -bit register holds the most recet digital value of the sampled sigal, ad is updated throughout the coversio cycle i both mid-cycle ad fullcycle update poits. Thus, a coarse result of the sampled sigal is geerated, which is refied through the coversio cycle, ad after over samplig clock cycles (f OS) a full resolutio digital represetatio of v out[] is obtaied. Typically SDADCs are desiged to sample sigals that do ot vary betwee two reset operatios of the couter [1], [3], [15]. The cocept employed i this study is desiged to accurately track the sampled sigal variatios betwee two or more reset evets of the couter, exploitig the SDADC advatages without the pealty of slower dyamics, power cosumptio, or icreased desig efforts [1]-[4], [15]-[18]. This eables to update the result more tha a sigle time per coversio cycle ad fast digitizig of the sampled sigal with high accuracy. Effectively, wider dyamic rage is achieved eve for fast variatios without sacrificig precisio. For the modulator operatio (detailed i Sectio IV), give clocks cycles sice the latest reset operatio the value of the recostructed cotiuous-time equivalet for the digitizatio process, V out * (t), is foud with respect to the mai couter s value, ad ca be expressed as * v, (1) out () t = Vref CNTR where V ref is the referece value for the modulatio process, ad CTR is the couter s value for a give umber of bits. For itermediate updates durig the coversio cycle (referred throughout the text as mid-cycle updates), the effective umber of bits is smaller tha ad the recostructed value is scaled ad ormalized accordig to the bits differece as follows m = CNTR, () mid = CNTR m CNTRmid CNTR where m is the umber of bits durig mid-cycle update commad ad CTR mid is the digital represetatio of the sampled sigal at mid-cycle update poits. Oe of the drawbacks of typical SDADCs is power cosumptio due to relatively high operatig frequecies to assure Nyquist samplig criterio [1], [3], [15]. Employig the modified operatio cocept, power savig optio is eabled. This is achieved by settig the SDADC ito two operatio modes: (a) trasiet detectio, (b) steady-state. For trasiet evet or ay other sudde potetial variatio of the sampled sigal, the system operates at high clock. The latter combied with mid-cycle updates, results i fast resposes of both the SDADC ad the overall cotrol loop. However, if the system is i steady-state mode, i.e. a system goveror detects mior deviatios of the coversio output alog a predetermied umber of cycles, the clock frequecy ca be lowered. This reduces the power cosumptio without
Fig.. Simplified block diagram of the ew architecture for SDADC. sacrificig precisio of the sampled sigal. The selectio procedure betwee the modes is illustrated i the flowchart of Fig. 3. III. ALL DIGITAL VOLTAGE LOOP COMPENSATION Digital VM compesatio for SMPS is a simple ad streamlied approach [1], [19], [0], to regulate the output voltage to a desired referece voltage over wide rage of operatig coditios. Sice a sigle state variable (the output voltage) is cotrolled, it requires moderate hardware complexity. It should be oted however, that the dyamic performace of this cotrol scheme may ot suffice all applicatios ad therefore a additioal curret loop is added which may be either aalog [5], [1] or digital [7]-[10]. I the cotext of this study, which aims to itroduce a ew ADC architecture, a voltage feedback loop has bee selected as a demostrative tool for simplicity. A coceptual block diagram of a typical sigle-loop VM cotrol scheme is depicted i Fig. 4. As ca be see, the output voltage v out(t) (or a scaled versio of it) is sesed ad the sampled by the SDADC, to produce a digital represetatio of the output voltage value v out[]. The allows, the sampled voltage is compared with a digital referece value, ad results i a error sigal v e[]. The error sigal is passed through a digital compesator (either PI or PID), which the updates the DPWM uit to geerate drive sigals for the low ad high side power switches of the coverter. K A/D ad K DPWM are the gais of the SDADC ad DPWM, respectively. The power stage that has bee selected for evaluatio is a buck coverter, with idealized cotrol-tooutput trasfer fuctio G vd(s) that ca be expressed as [7], [11] Vi 1 Cout Gvd () s = ; ω 0 =, Q= RL. (3) s s LCout L + + 1 ω0 ω0q Fig. 5 shows a coceptual timig diagram for a output voltage variatio for both a covetioal SDADC ad the ehaced performace SDADC developed i this study. Output voltage regulatio is achieved by properly adjustig the duty-ratio commad d[] as a fuctio of the geerated error sigal v e[]. Fig. 5a shows that the covetioal SDADC is beig updated oly at the ed a of a full coversio cycle, resultig i relatively slow closed-loop Fig. 3. Fig. 4. High-level flowchart of the clock selectio mode. Block diagram of the digital VM cotrol system. respose due to limited samplig ad correctio rate. For similar settigs of the digital hardware (i.e., clock speed ad calculatio hardware), the ew SDADC employs coarse correctios throughout the operatio cycle at shorter itervals, which provides more iformatio o the voltage, but with lower resolutio tha the ed-of-cycle result. Cosequetly, the output voltage is corrected faster, ad
rate ad resolutio is virtually idetical for samples at midcycle as the oe obtaied at the ed of the loger cycle. The faster ad more accurate respose of the ew SDADC implies that higher effective badwidth of the closed-loop system is achieved for the same hardware complexity ad ruig frequecy of the cotroller. Fig. 5. Coceptual timig sequece of duty-ratio updates i respose to voltage referece chage: (a) Covetioal SDADC, (b) Ehaced performace. Sampled Sigal S i (t) R 1 C 1 Iverter-Based CMP S o (t) D Bit-Stream Fig. 6. SDADC modulator schematic circuit. covergece to desired referece value V ref is obtaied. While iformatio of coarser resolutio apparetly distorts the trackig capability of the loop, the iformatio flows i a faster rate ad as a result compesates for lower accuracy. It should be oted that, the ratio betwee the effective samplig f OS SET CLR Q Q TRG. IV. PRACTICAL IMPLEMENTATION Practical implemetatio ad desig cosideratios of the SDADC s mai fuctioal uits are discussed i this sectio. Sice this desig is ultimately IC orieted, with automatic tools, emphasis is made to reduce the use of aalog peripherals. A. Modulator Stage Covetioal SD modulators comprise differece amplifier followed by a itegrator ad comparator [], [4], [15]. I this study, a digital-orieted approach is cosidered ad is show i Fig. 6. A iverter is used as the modulator s frot-ed, with the sesed sigal as the high logic level (supply) of the iverter. This ca be implemeted i variety of ways such as variable supply [], [3], curret-starved iverter [4], [5], or digital differetiator or comparator [0]. To reduce circuit complexity, the itegrator is realized by a simple RC etwork (may be double RC for further size reductio) with a corer frequecy of at least oe order of magitude lower tha the clock frequecy. The oe-bit quatizer is also realized by aother iverter, where the threshold value of the iverter is the compariso [0]. Fially, the quatized value is held for a clock cycle usig a D flip-flop which also drives the first iverter data path. Utilizig this cofiguratio of Fig. 6, a simple ad efficiet SD modulator with streamlied IC implemetatio is facilitated. Fig. 7 depicts a example for steady-state operatio of the SDADC s modulator. The modulator produces the bit-stream such that the voltage at ode S o(t) is toggled aroud the threshold voltage of iverter-based comparator V th. This is achieved by feedback lik betwee the flip-flop ad the iput samplig iverter operatio as ca be see i Fig. 7, resultig i a square sigal S i(t) betwee 0 ad the sampled voltage value, which charges/discharges the itegrator s output. The relatioship betwee the sampled sigal ad the geerated bit-stream is accordig to (1), ad it is a primary cocept for the ew SDADC architecture. B. Operatio Mode Detector As discussed i Sectio II, the SDADC i this study has a clock selectio mechaism to reduce the power cosumptio at steady-state operatio. A algorithm to idetify trasitios is described with the aid of Figs. 8 ad 9. Every four sequetial full cycle results are held i the registers as show i Fig. 8. The results are cotiuously compared ad as log as they are equal, the system operates at a lower clock frequecy. For a case that the compariso block detects a sigle chage betwee the four sequetial results, the system immediately switches to fast clock mode with rapid trasitios to obtai the most accurate value of the
Fig. 9. Simulatio results of clock selectio eterig ad exitig power savig mode. Fig. 7. Typical steady-state samplig operatio of the SDADC. (a) Output voltage of the samplig iverter (b) Itegrator s output (c) Geerated bit-stream represetig the sampled sigal. Fig. 10. SDADC layout 00μm x 117μm. 5.5 5 1.6% Fig. 8. Simplified block diagram for operatio mode decisio makig algorithm. sampled sigal. It should be oted that full cycle coversio is geerated whe the reset couter (see Fig. ) reaches -1. Fig. 9 shows simulatio example demostratig the clock selectio algorithm for a 10-bit SDADC to a iput sigal that periodically toggles betwee 3V to 4V. As ca be see, while the sampled voltage is costat the reset couter icreases with slow clock, however, wheever trasitio occurs, the reset couter rapidly icreases with the aid of the fast clock withi i the system. C. IC Implemetatio The realizatio of the digital cotrol i this study primarily relies o a automated digital implemetatio flow, usig vedor s stadard cells. The IC implemetatio of the voltage cotrol loop is described through three mai steps. I the first step, digital custom desig is carried out for SDADC s modulatio stage ad iverter-based comparator. Secod, the cotroller s uits icludig the SDADC core are described i HDL as stadaloe uits. This is doe for simplicity of the verificatio ad fuctioality simulatios. 4.5 4 3.5 3.5 1.7% 1.% 0.5% 1.5% 3 4 5 6 Fig. 11. Accuracy post-layout results of the SDADC for wide rage of sampled voltages. The, each uit is traslated to hardware usig sythesis ad timig verificatio tools ito a optimized gate-level represetatio, give a set of desig costraits. The silico layout for each uit is geerated by a automated place-adroute process. I the third step, all uits are itegrated together oto the higher hierarchy of the digital cotroller, ad the resultat overall die-area is 0.07mm (with 5V CMOS realizatio). It should be emphasized however, that
for higher desity assigmet or scaled techology (such as deeper sub-micro process), the area ad power cosumptio ca be further reduced. The implemeted SDADC comprises of a double RC etwork based itegrator, frot-ed custom desiged iverter, stadard cell based iverter that fuctios as a comparator, ad a digital computatio core that operates at f OS=6.5MHz. Fig. 10 shows the SDADC layout which results i effective silico area of 0.03mm, which is sigificatly compact i compariso to other ADCs with similar performace. Fig. 11 depicts post-layout results of the SDADC for a wide rage of sampled voltages to characterize ad quatify the samplig accuracy. As ca be see, for sampled voltages i the rage of.5-to-5v the obtaied samplig error is less tha 1.7%. V. SIMULATION CASE STUDY Usig the aalysis ad observatios from the previous sectios, set of simulatios have bee coducted i PSIM (PowerSim, Ic.) to verify the effectiveess of the ew ehaced performace SDADC i a closed-loop operatio of a buck coverter as illustrated i Fig. 1. Fig. 1 shows the respose to referece chages of the buck coverter operatig i closed loop for differet settigs of the operatig frequecy, output capacitor ad iductor. I the first case (Fig. 1a) a covetioal SDADC is examied, ad switchig frequecy f sw1 is as follows fos f sw1 =, (4) where f os is the oversamplig clock frequecy. I the secod test case (Fig. 1b), the ew SDADC is used, demostratig improved performace compared to the results obtaied i Fig. 1a. It should be oted that for this evaluatio, the values for iductace ad capacitace i the buck coverter remai the same. Sice the effective samplig frequecy is higher whe utilizig the ew approach, the switchig frequecy may exceed to f sw, which ca be expressed as: fos f sw =, (5) m ad the ratio betwee f sw ad f sw1, usig (4) ca be writte as fsw = fsw = f. (6) m m sw1 fsw 1 As ca be observed from Fig. 1b, the ew loop settigs that allowed icreased switchig frequecy f sw, result i improved covergece of the output voltage to the ew steady-state value. The advatage of utilizig the ew SDADC becomes widely apparet i respose of the third test case of Fig. 1c. Sice higher switchig frequecy is allowed, the iductace ad capacitace values may be adjusted to satisfy similar ripple costraits as i Fig. 1a. This implies that effectively higher badwidth ca be achieved, resultig i better dyamic respose (for the same cotrol hardware) ad lower Fig. 1. Respose to chages i the referece voltage for the digitally cotrolled buck coverter: (a) Covetioal SDADC with samplig frequecy f sw1, (b) New SDADC with samplig frequecy f sw, ad same compoets (c) New SDADC adjusted f sw ad compoets. volume of the overall solutio. For the example of Fig. 1c, the frequecy is adjusted f sw = 4f sw1so that same target ripples as i Fig. 1a.the output capacitor C ad iductor L ca be calculated as f sw1 fsw 1 C = C1 ; L = L1. (7) fsw fsw Fig. 13 shows a simulatio closed-loop VM operatio of a buck coverter with L=75μH ad C out=100μf at operatig frequecy 100 KHz For a step evet of the output voltage referece, Fig. 13a shows the trasiet respose of the coverter usig a covetioal SDADC with f OS=6.5 MHz. Fig. 13b shows the trasiet respose of the coverter usig the ew SDADC for the same operatig coditios ad =10. It ca be see that both the overshoot ad settlig time are sigificatly reduced whe the samplig frequecy is icreased as a result of the mid-cycle updates.
Recostructed ADC Result [V] 9 8 7 6 5 4 3 Ideal Experimetal <0.8%.5% 4.6% 4.1% 3.%.3% 4 6 8 Sampled Sigal [V] Fig. 14. SDADC accuracy experimetal measuremets for wide rage sampled output voltages. TABLE I EXPERIMENTAL PROTOTYPE CHARACTERISTICS Fig. 13. Output voltage trasiet respose of the simulated buck coverter for 3.3V to 5V: (a) Covetioal SDADC with full-cycle update (b) New SDADC with mid-cycle updates. VI. EXPERIMENTAL SYSTEM IMPLEMENTATION AND VALIDATION To validate the operatio of the ew SDADC i a VM cotrol loop, a FPGA based cotroller utilizig 10-bit couter based SDADC has bee fully coded i Verilog ad implemeted o a Cycloe IV FPGA usig Quartos eviromet, resultig i approximately 05 logic cells. The operatio has bee demostrated with a buck coverter prototype operatig at 100 khz for a omial output voltage of 3.3V. Table summarizes the experimetal setup mai characteristics. The first step of the experimetal validatio is to characterize ad quatify the samplig accuracy of the SDADC. This is doe for a wide rage output voltages of the buck coverter prototype. Fig. 14 shows the results for varyig the output voltage i the rage of.8v to 8V. It ca be see that i the rage of the omial output voltage that the error of the SDADC is less tha 1%, while worst-case error of 4.6% is obtaied for sampled voltage of 8V. To further validate the effectiveess of the ehaced SDADC, the experimetal prototype has bee evaluated through a closed-loop VM operatio. Fig. 15 shows the results for a step evet of the output voltage referece, such that the output voltage varies from 3.3V to 5V, which are i good agreemet with the simulatio results i Fig. 13. Show i Fig. 15a is the respose of the system with the developed SDADC, it ca be see that system is well regulated validatig the proper fuctioality of both the SDADC ad digital cotrol loop, where a 100mV overshot is obtaied. Fig. 15b shows the respose of the experimetal prototype while usig a covetioal SDADC, it ca be observed that the obtaied overshot is 8.8V that is 38 times larger overshoot compared to the SDADC developed i this study. I additio, 3.6 times shorter settlig time is achieved Parameter Value/Type Iput voltage Vi 10V Output voltage Vout 3.3V Switchig frequecy fs 100kHz Iductor 75 H Capacitor 100 F, ESR=0.5 Couter umber of bits 10-bit Number of mid-cycle updates 4 Modulator s clock frequecies 3.15/6.5 MHz while usig the ew SDADC. Fig. 16 depicts a zoom-i o trasiet evet of the output voltage withi the system. It ca be well observed that durig the trasitio, the duty-ratio is varied accordig to the pre-defied mid-cycle update commads, which i this case are set i the rage of 6-bits to 10-bits. The duty-ratio is icreasigly growig to compesate for the variatio at the output voltage, elimiate the eed to wait for a update commad every 10 clock cycles. VII. CONCLUSION A ehaced performace fully-sythesizable SDADC has bee preseted, ad verified through simulatio ad experimetal data. The ew SDADC has less hardware ad silico requiremets compared to a covetioal SDADC, while presetig much better dyamics, geeratig fast digitizig of the sampled sigal with high accuracy ad wide dyamic rage, eve for fast variatios without the pealty of sacrificig the precisio. I additio, a digital VM compesatio has bee realized ad experimetally verified with a buck coverter. The accuracy of the SDADC has bee experimetally characterized by measurig the output voltage over wide rage operatig poits, demostratig worst-case error of 4.6%, while i the viciity of the omial operatig coditios 99% accuracy has bee achieved. The VM cotrol icludig the ew SDADC have bee desiged i digitally-orieted approach without ay power hugry aalog blocks, ad implemeted i 0.18 m 5V CMOS process resultig i total effective silico area of 0.07mm.
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