EE 330 Lecture 5 asic Logic Circuits Complete Logic Family Other Logic Styles complex logic gates
Review from Last Time The key patents that revolutionized the electronics field: Jack Kilby (34 years old at invention) patent: 3,138,743 Filed Feb 6, 1959 Issued June 23, 1964 Robert Noyce (31 years old at invention) patent: 2,981,877 Filed July 30, 1959 Issued pril 25, 1961
asic Logic Circuits
asic Logic Circuits Will present a brief description of logic circuits based upon simple models and qualitative description of processes Will later discuss process technology needed to develop better models Will even later provide more in-depth discussion of logic circuits based upon better device models
Models of Devices Several models of the electronic devices will be introduced throughout the course Complexity ccuracy Insight pplication Will use the simplest model that can provide acceptable results for any given application
MOS Transistor Qualitative Discussion of n-channel Operation Source Gate Drain Drain ulk Gate Cross-Sectional View n-channel MOSFET Source Symbol for n-channel MOSFET n-type n+-type Top View Source Drain p-type p+-type Gate SiO 2 (insulator) Designer always works with top view Complete Symmetry in construction between Drain and Source POL (conductor)
MOS Transistor Qualitative Discussion of n-channel Operation Source Gate Drain Drain ulk Gate V GS Source n-channel MOSFET ehavioral Description of Operation of n-channel MOS Transistors Created for use in asic Digital Circuits If V GS is large, short circuit exists between drain and source If V GS is small (or negative), open circuit exists between drain and source
Voltage xis oolean/continuous Notation: G=1 oolean xis 0V G=0 - Voltage xis is Continuous between 0V and - oolean axis is discrete with only two points Most logic circuits characterized by the relationship between the oolean input/output variables though these correspond to voltage intervals on the continuous voltage axis
MOS Transistor Qualitative Discussion of n-channel Operation ulk Source Gate Drain Drain Gate n-channel MOSFET Source Equivalent Circuit for n-channel MOSFET D G = 0 D G = 1 Source assumed connected to (or close to) ground V GS =0 denoted as oolean gate voltage G=0 V GS = denoted as oolean gate voltage G=1 oolean G is relative to ground potential S S This is the first model we have for the n-channel MOSFET! Ideal switch-level model
MOS Transistor MODEL Drain I D Gate Source Equivalent Circuit for n-channel MOSFET with source as ground D D G = 0 G = 1 S Mathematical model (not dependent upon oolean notation): I =0 if V is low D DS GS V =0 if V is high GS S (or negative)
MOS Transistor Qualitative Discussion of p-channel Operation Source Gate Drain Drain ulk Gate Cross-Sectional View Source Symbol for p-channel MOSFET p-channel MOSFET n-type n+-type Top View Source Drain p-type p+-type Gate Complete Symmetry in construction between Drain and Source SiO 2 (insulator) POL (conductor)
ulk MOS Transistor Qualitative Discussion of p-channel Operation Source Gate Drain Drain Gate Source p-channel MOSFET ehavioral Description of Operation of p-channel transistors created for use in basic digital circuits If V GS is large (and negative), short circuit exists between drain and source If V GS is small (near 0 or positive), open circuit exists between drain and source
MOS Transistor Qualitative Discussion of p-channel Operation Source Gate Drain Drain ulk Gate p-channel MOSFET Source D Equivalent Circuit for p-channel MOSFET D G = 0 G = 1 Source assumed connected to (or close to) positive V GS =0 denoted as oolean gate voltage G=1 V GS = - denoted as oolean gate voltage G=0 oolean G is relative to ground potential S S This is the first model we have for the p-channel MOSFET!
MOS Transistor MODEL Drain I D Gate Source Equivalent Circuit for p-channel MOSFET with Source at VDD D D G = 0 G = 1 S S Mathematical model (not dependent upon oolean notation): I =0 if V is small D GSp or V GSp is positive V =0 if V is large DS GSp
MOS Transistor Comparison of Operation Drain Drain Gate Gate Source Source D D D D G = 0 G = 1 G = 0 G = 1 S S S S Source assumed connected to (or close to) ground Source assumed connected to (or close to) positive and oolean G at gate is relative to ground
Logic Circuits = 1 = 0 = 0 = 1 Circuit ehaves as a oolean Inverter
Logic Circuits Truth Table 0 1 1 0 Inverter
Logic Circuits C =0 =0 C =1
Logic Circuits C =1 =0 C =0
Logic Circuits C =0 =1 C =0
Logic Circuits C =1 =1 C =0
Logic Circuits Truth Table C C 0 0 1 0 1 0 1 0 0 1 1 0 NOR Gate
Logic Circuits C Truth Table C 0 0 1 0 1 1 1 0 1 1 1 0 NND Gate
Logic Circuits pproach can be extended to arbitrary number of inputs n-input NOR gate n-input NND gate 1 2 1 2 n F 1 n F 2 1 2 n n 1 2 F 1 2 F n n
Complete Logic Family 1 2 F 1 2 F n n Family of n-input NOR gates forms a complete logic family Family of n-input NND gates forms a complete logic family Having both NND and NOR gates available is a luxury Can now implement any combinational logic function!! If add one flip flop, can implement any oolean system!! Flip flops easy to design but will discuss sequential logic systems later
Other logic circuits Other methods for designing logic circuits exist Insight will be provided on how other logic circuits evolve Several different types of logic circuits are often used simultaneously in any circuit design
Pull-up and Pull-down Networks PUN GND PDN GND PU network comprised of p-channel device and tries to pull to VDD when conducting PD network comprised of n-channel device and tries to pull to GND when conducting One and only one of these networks is conducting at the same time
Pull-up and Pull-down Networks PUN C C PDN PU network comprised of p-channel devices PD network comprised of n-channel devices One and only one of these networks is conducting at the same time
Pull-up and Pull-down Networks C PUN C PDN PU network comprised of p-channel devices PD network comprised of n-channel devices One and only one of these networks is conducting at the same time
Pull-up and Pull-down Networks In these circuits, the PUN and PDN have the 3 interesting characteristics 1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time X n PUN PDN What are V H and V L? What is the power dissipation? How fast are these logic circuits?
Consider the inverter What are V H and V L? What is the power dissipation? How fast are these logic circuits? Use switch-level model for MOS devices
Consider the inverter What are V H and V L? What is the power dissipation? How fast are these logic circuits? Use switch-level model for MOS devices V H = V L =0 I D =0 thus P H =P L =0 t HL =t LH =0 (too good to be true?)
Pull-up and Pull-down Networks For these circuits, the PUN and PDN have 3 interesting characteristics Three key characteristics of these Static CMOS Gates 1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time PUN Three key properties of these Static CMOS Gates 1. What are V H and V L? V H =, V L =0 (too good to be true?) 2. What is the power dissipation? P H =P L =0 (too good to be true?) 3. How fast are these logic circuits? t HL =t LH =0 (too good to be true?) X n PDN These 3 properties are inherent in all oolean circuits that have these 3 characteristics!!!
Pull-up and Pull-down Networks Three key characteristics of Static CMOS Gates 1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time Three properties of Static CMOS Gates (based upon simple switch-level model) 1. V H =, V L =0 (too good to be true?) X n PUN PDN 2. P H =P L =0 (too good to be true?) 3. t HL =t LH =0 (too good to be true?) These 3 properties are inherent in oolean circuits with these 3 characteristics
Pull-up and Pull-down Networks Concept can be extended to arbitrary number of inputs n-input NOR gate n-input NND gate X 1 X 1 X 2 X n X 2 X 1 X n X 2 X 1 X 2 X n X n
Pull-up and Pull-down Networks Concept can be extended to arbitrary number of inputs n-input NOR gate n-input NND gate X 1 X 1 X 2 X n X 2 X 1 X n X 2 X 1 X 2 X n X n 1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time
Pull-up and Pull-down Networks X 1 X 2 X n PUN X 1 X 2 X n X n n-input NOR gate PDN X 1 X 2 X n X 1 X 2 1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time X n n-input NND gate V H =, V L =0 P H =P L =0 t HL =t LH =0
Nomenclature X 1 X 2 X 1 X 2 X n X 1 X n X 2 X 1 X 2 X n X n n-input NOR gate n-input NND gate In this class, logic circuits that are implemented by interconnecting multipleinput NND and NOR gates will be referred to as Static CMOS Logic Since the set of NND gates is complete, any combinational logic function can be realized with the NND circuit structures considered thus far Since the set NOR gates is complete, any combinational logic function can be realized with the NOR circuit structures considered thus far Many logic functions are realized with Static CMOS Logic and this is probably the dominant design style used today!
Example 1: Circuit Structures Circuit Design How many transistors are required to realize the function F C in a basic CMOS process if static NND and NOR gates are used? ssume, and C are available.
Example 1: How many transistors are required to realize the function F C in a basic CMOS process if static NND and NOR gates are used? ssume, and C are available. Solution: C F 20 transistors and 5 levels of logic
How many transistors are required to realize the function in a basic CMOS process if static NND and NOR gates are used? ssume, and C are available. C F Solution (alternative): From basic oolean Manipulations C C F C 1 F F 8 transistors and 3 levels of logic Example 1:
Example 1: How many transistors are required to realize the function F C in a basic CMOS process if static NND and NOR gates are used? ssume, and C are available. Solution (alternative): From basic oolean Manipulations F 1 C F F 6 transistors and 2 levels of logic
Example 2: XOR Function = widely-used 2-input Gate Static CMOS implementation = + 22 transistors 5 levels of logic Delays unacceptable (will show later) and device count is too large!
Example 3: C D Standard Static CMOS Implementation C D 3 levels of Logic 16 Transistors if asic CMOS Gates are Used Can the same oolean functionality be obtained with less transistors?
Observe: C D D C D C Significant reduction in transistor count and levels of logic for realizing same oolean function Termed a Complex Logic Gate implementation Some authors term this a compound gate
Complex Logic Gates Pull-up Network C D D Pull-down Network C C D
Complex Gates Pull up and pull down network never both conducting One of the two networks is always conducting C D D C
Complex Gates Nomenclature: PUN X n PDN When the logic gate shown is not a multiple-input NND or NOR gate but has Characteristics 1, 2, and 3 above, the gate will be referred to as a Complex Logic Gate Complex Logic Gates also implement static logic functions and some authors would refer to this as Static CMOS Logic as well but we will make the distinction and refer to this as Complex Logic Gates
Complex Gates PUN X n PDN Complex Gate Design Strategy: 1. Implement in the PDN 2. Implement in the PUN (must complement the input variables since p- channel devices are used) ( and often expressed in either SOP or POS form)
XOR in Complex Logic Gates = Will express and in standard SOP or POS form
XOR in Complex Logic Gates = = + = + = = + +
XOR in Complex Logic Gates = + = + + PDN PUN
XOR in Complex Logic Gates = + = + + 12 transistors and 2 levels of logic Notice a significant reduction in the number of transistors required
XOR in Complex Logic Gates = + = + + Multiple PU and PD networks can be used = + + + + + +
Complex Logic Gate Summary: PUN X n PDN If PUN and PDN satisfy the characteristics: 1. PU network comprised of p-channel device 2. PD network comprised of n-channel device 3. One and only one of these networks is conducting at the same time Properties of PU/PD logic of this type (with simple switch-level model): Rail to rail logic swings Zero static power dissipation in both =1 and =0 states rbitrarily fast (too good to be true? will consider again with better model)
End of Lecture 5