19-3; Rev 1; 3/11 ±1kV ESD-Protected Mbps, 3V to.v, SOT3 General Description The MAX38E/MAX381E/MAX383E/MAX384E are single receivers designed for RS-48 and RS-4 communication. These devices guarantee data rates up to Mbps, even with a 3V power supply. Excellent propagation delay (1ns max) and package-to-package skew time (8ns max) make these devices ideal for multidrop clock distribution applications. The MAX38E/MAX381E/MAX383E/MAX384E have true fail-safe circuitry, which guarantees a logichigh receiver output when the receiver inputs are opened or shorted. The receiver output will be a logic high if all transmitters on a terminated bus are disabled (high impedance). These devices feature 1/4-unit-load receiver input impedance, allowing up to 18 receivers on the same bus. The MAX38E is a single receiver available in a -pin SOT3 package. The MAX381E/MAX383E single receivers have a receiver enable ( or ) function and are offered in a 6-pin SOT3 package. The MAX384E features a voltage logic pin that allows compatibility with low-voltage logic levels, as in digital FPGAs/ASICs. On the MAX384E, the voltage threshold for a logic high is user-defined by setting V L in the range from 1.6V to. The MAX384E is also offered in a 6-pin SOT3 package. Clock Distribution Telecom Racks Base Stations Industrial Control Local Area Networks Pin Configurations appear at end of data sheet. Applications Features ESD Protection: ±1kV Human Body Model ±6kV IEC 1-4-, Contact Discharge ±1kV IEC 1-4-, Air-Gap Discharge Guaranteed Mbps Data Rate Guaranteed 1ns Receiver Propagation Delay Guaranteed ns Receiver Skew Guaranteed 8ns Package-to-Package Skew Time V L Pin for Connection to FPGAs/ASICs Allow Up to 18 Transceivers on the Bus (1/4-unit-load) Tiny SOT3 Package True Fail-Safe Receiver -7V to +1V Common-Mode Range 3V to.v Power-Supply Range Enable (High and Low) Pins for Redundant Operation Three-State Output Stage (MAX381E/MAX383E) Thermal Protection Against Output Short Circuit PART Ordering Information TEMP RANGE PIN- PACKAGE TOP MARK MAX38EAUK+T -4 C to +1 C SOT3- ADVM MAX381EAUT+T -4 C to +1 C 6 SOT3-6 ABAT MAX383EAUT+T -4 C to +1 C 6 SOT3-6 ABAU MAX384EAUT+T -4 C to +1 C 6 SOT3-6 ABAV +Denotes a lead(pb)-free/rohs-compliant package. T = Tape and reel. Selector Guide MAX38E/MAX381E/MAX383E/MAX384E PART V L ABLE DATA RATE PACKAGE MAX38E Mbps -Pin SOT3 MAX381E Active High Mbps 6-Pin SOT3 MAX383E Active Low Mbps 6-Pin SOT3 MAX384E Mbps (Note 1) 6-Pin SOT3 Note 1: MAX384E data rate is dependent on V L. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-69-464, or visit Maxim s website at www.maxim-ic.com.
MAX38E/MAX381E/MAX383E/MAX384E ABSOLUTE MAXIMUM RATINGS (All Voltages Referenced to GND) Supply Voltage ( )...-.3V to +6V Control Input Voltage (, )...-.3V to +6V V L Input Voltage...-.3V to +6V Receiver Input Voltage (A, B)...-7.V to +1.V Receiver Output Voltage (RO)...-.3V to ( +.3V) Receiver Output Voltage (RO) (MAX384E)...-.3V to (V L +.3V) Receiver Output Short-Circuit Current...Continuous Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Continuous Power Dissipation (T A = +7 C) -Pin SOT3 (derate 7.1mW/ C above +7 C)...71mW 6-Pin SOT3 (derate 8.7mW/ C above +7 C)...696mW Operating Temperature Range MAX38_EA...-4 C to +1 C Storage Temperature Range...-6 C to +1 C Junction Temperature...+1 C Lead Temperature (soldering, 1s)...+3 C Soldering Temperature (reflow)...+6 C ( = 3V to.v, V L =, T A = T MIN to T MAX, unless otherwise noted. Typical values are at = V and T A = + C.) (Notes, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage 3.. V Supply Current I CC No load 9 1 ma V L Input Range V L MAX384E 1.6 V V L Supply Current I L No load (MAX384E) 1 μa RECEIVER Input Current (A and B) I A, B = V GND or.v Receiver Differential Threshold Voltage V IN = +1V V IN = -7V - V TH -7V V CM +1V (Note 4) - -1 - mv Receiver Input Hysteresis V TH V A + V B = V mv Receiver Enable Input Low V IL MAX381E, MAX383E only.4 V Receiver Enable Input High V IH MAX381E, MAX383E only V Receiver Enable Input Leakage I LEAK MAX381E, MAX383E only ±1 μa MAX38E/MAX381E/MAX383E, Receiver Output High Voltage V OH I OH = -4mA, RO high MAX384E, I OH = -1mA, 1.6V V L, RO high MAX38E/MAX381E/MAX383E, Receiver Output Low Voltage V OL I OL = 4mA, RO low MAX384E, I OL = 1mA, 1.6V V L, RO low Three-State Output Current at Receiver -.4 V L -.4 I OZR V O, RO = high impedance ± μa Receiver Input Resistance R IN -7V V CM +1V (Note ) 48 k Receiver Output Short-Circuit Current ESD PROTECTION ESD Protection (A, B) I OSR V RO ±13 ma Human Body Model ±1 IEC1-4- (Air-Gap Discharge) ±1 IEC1-4- (Contact Discharge) ±6.4.4 μa V V kv
SWITCHING CHARACTERISTICS ( = 3V to.v, V L =, T A = T MIN to T MAX, unless otherwise noted. Typical values are at = V and T A = + C.) (Notes, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Maximum Data Rate f MAX C L = 1pF (Notes, 6) Mbps Receiver Propagation Delay t PLH Figure 1, C L = 1pF, V ID = V, V CM = V 7 1 t PHL Figure 1, C L = 1pF, V ID = V, V CM = V 8 1 Receiver Output t PLH - t PHL t PSKEW Figure 1, C L = 1pF, T A = + C ns Device-to-Device Propagation Delay Matching ABLE/DISABLE TIME FOR MAX381E/MAX383E Same power supply, maximum temperature difference between devices = +3 C. ns 8 ns Receiver Enable to Output Low t PRZL Figure, C L = 1pF ns Receiver Enable to Output High t PRZH Figure, C L = 1pF ns Receiver Disable Time from Low t PRLZ Figure, C L = 1pF ns Receiver Disable Time from High t PRHZ Figure, C L = 1pF ns Note : Parameters are 1% production tested at + C, limits over temperature are guaranteed by design. Note 3: All currents into the device are positive; all currents out of the device are negative. All voltages are referenced to device ground, unless otherwise noted. Note 4: V CM is the common-mode input voltage. V ID is the differential input voltage. Note : Not production tested. Guaranteed by design. Note 6: See Table for MAX384E data rates with V L <. ( = 3.3V, T A = + C, unless otherwise noted.) OUTPUT VOLTAGE (V) 4 3 1 RECEIVER OUTPUT LOW VOLTAGE vs. OUTPUT CURRT = 3.3V = V MAX38/1/3/4E toc1 OUTPUT VOLTAGE (V) 4 3 1 RECEIVER OUTPUT HIGH VOLTAGE vs. OUTPUT CURRT = V = 3.3V Typical Operating Characteristics MAX38/1/3/4E toc RECEIVER OUTPUT HIGH VOLTAGE (V). 4. 4. 3. 3. RECEIVER OUTPUT HIGH VOLTAGE vs. TEMPERATURE = V = 3.3V MAX38/1/3/4E toc3 MAX38E/MAX381E/MAX383E/MAX384E 1 3 4 6 OUTPUT CURRT (ma) - -4-3 - -1 OUTPUT CURRT (ma). V A = 1V, B = GND, I OH = -4mA - - 7 1 1 3
MAX38E/MAX381E/MAX383E/MAX384E Typical Operating Characteristics (continued) ( = 3.3V, T A = + C, unless otherwise noted.) RECEIVER OUTPUT LOW VOLTAGE (mv) 1 1 RECEIVER OUTPUT LOW VOLTAGE vs. TEMPERATURE = 3.3V A = GND, V B = 1V, I OL = 4mA = V - - 7 1 1 SUPPLY CURRT (ma) SUPPLY CURRT (ma) 9 8 7 6 1 8 6 4 MAX38/1/3/4E toc4 tplh (ns) SUPPLY CURRT vs. TEMPERATURE = V = 3.3V - - 7 1 1 SUPPLY CURRT vs. DATA RATE I CC, = V L = V I CC, = V L = 3.3V I L, = V L = 3.3V DATA RATE (kbps) 9 8 7 6 4 I L, = V L = V 1 1 1 1, 1, RECEIVER PROPAGATION DELAY (t PLH ) vs. TEMPERATURE = V = 3.3V - - 7 1 1 MAX38/1/3/4E toc7 MAX38/1/3/4E toc9 DATA RATE (Mbps) VL SUPPLY CURRT (ma) 6 4 3 1 1.1.1 MAX38/1/3/4E toc tphl (ns) 1 9 8 7 6 RECEIVER PROPAGATION DELAY (t PHL ) vs. TEMPERATURE = V = 3.3V - - 7 1 1 MAX384E MAXIMUM DATA RATE vs. VOLTAGE LOGIC LEVEL 1.. 3. 4.. VOLTAGE LOGIC LEVEL (V) V L SUPPLY CURRT vs. TEMPERATURE = V L = V DATA RATE = Mbps = V L = 3.3V DATA RATE = Mbps = V L = V DATA RATE = 1kbps = V L = 3.3V DATA RATE = 1kbps.1 - - 7 1 1 MAX38/1/3/4E toc8 MAX38/1/3/4 toc1 MAX38/1/3/4E toc6 4
PIN MAX38E MAX381E MAX383E MAX384E NAME Detailed Description The MAX38E/MAX381E/MAX383E/MAX384E are single, true fail-safe receivers designed to operate at data rates up to Mbps. The fail-safe architecture guarantees a high output signal if both input terminals are open or shorted together. See the True Fail-Safe section. This feature assures a stable and predictable output logic state with any transmitter driving the line. These receivers function with a 3.3V or V supply voltage and feature excellent propagation delay times (1ns). The MAX38E is a single receiver available in a -pin SOT3 package. The MAX381E (, active high) and MAX383E (, active low) are single receivers that also contain an enable pin. Both the MAX381E and MAX383E are available in a 6-pin SOT3 package. The MAX384E is a single receiver that contains a V L pin, which allows communication with low-level logic included in digital FPGAs. The MAX384E is available in a 6-pin SOT3 package. The MAX384E s low-level logic application allows users to set the logic levels. A logic high level of 1.6V will limit the maximum data rate to Mbps. ±1kV ESD Protection ESD-protection structures are incorporated on the receiver input pins to protect against ESD encountered during handling and assembly. The MAX38E/ MAX381E/MAX383E/MAX384E receiver inputs (A, B) have extra protection against static electricity found in normal operation. Maxim s engineers developed state-of-the-art structures to protect these pins against FUNCTION Pin Description Positive Supply: 3V.V. Bypass with a.1μf 1 1 1 1 capacitor to GND. GND Ground 3 3 3 3 RO 4 4 4 4 B Inverting Receiver Input Receiver Output. RO will be high if (V A - V B ) -mv. RO will be low if (V A - V B ) -mv. Receiver Output Enable. Drive low to enable RO. When is high, RO is high impedance. Receiver Output Enable. Drive high to enable RO. When is low, RO is high impedance. V L voltage, ranging from 1.6V to. RO output high is pulled Low-Voltage Logic-Level Supply Voltage. V L is a user-defined up to V L. Bypass with a.1μf capacitor to GND. 6 6 6 A Noninverting Receiver Input ±1kV ESD without damage. After an ESD event, this family of parts continues working without latchup. ESD protection can be tested in several ways. The receiver inputs are characterized for protection to the following: ±1kV using the Human Body Model ±6kV using the Contact Discharge method specified in IEC 1-4- (formerly IEC 81-) ±1kV using the Air-Gap Discharge method specified in IEC 1-4- (formerly IEC 81-) ESD Test Conditions ESD performance depends on a number of conditions. Contact Maxim for a reliability report that documents test setup, methodology, and results. Human Body Model Figure 3a shows the Human Body Model, and Figure 3b shows the current waveform it generates when discharged into a low impedance. This model consists of a 1pF capacitor charged to the ESD voltage of interest, which is then discharged into the device through a 1.kΩ resistor. IEC 1-4- Since January 1996, all equipment manufactured and/or sold in the European community has been required to meet the stringent IEC 1-4- specification. The IEC 1-4- standard covers ESD testing and performance of finished equipment; it does not specifically refer to integrated circuits. The MAX38E/MAX381E/MAX383E/MAX384E help MAX38E/MAX381E/MAX383E/MAX384E
MAX38E/MAX381E/MAX383E/MAX384E users design equipment that meets Level 3 of IEC 1-4-, without additional ESD-protection components. The main difference between tests done using the Human Body Model and IEC 1-4- is higher peak current in IEC 1-4-. Because series resistance is lower in the IEC 1-4- ESD test model (Figure 4a), the ESD-withstand voltage measured to this standard is generally lower than that measured using the Human Body Model. Figure 4b shows the current waveform for the ±8kV IEC 1-4- Level 4 ESD Contact Discharge test. The Air-Gap test involves approaching the device with a charger probe. The Contact Discharge method connects the probe to the device before the probe is energized. Machine Model The Machine Model for ESD testing uses a pf storage capacitor and zero-discharge resistance. It mimics the stress caused by handling during manufacturing and assembly. All pins (not just the RS-48 inputs) require this protection during manufacturing. Therefore, the Machine Model is less relevant to the I/O ports than are the Human Body Model and IEC 1-4-. True Fail-Safe The MAX38E/MAX381E/MAX383E/MAX384E guarantee a logic-high receiver output when the receiver inputs are shorted or open, or when they are connected to a terminated transmission line with all drivers disabled. This guaranteed logic high is achieved by setting the receiver threshold between -mv and -mv. If the differential receiver input voltage (V A - V B ) is greater than or equal to -mv, RO is logic high. If (V A - V B ) is less than or equal to -mv, RO is logic low. In the case of a terminated bus with all transmitters disabled, the receiver s differential input voltage is pulled to ground by the termination. This results in a logic high with a mv minimum noise margin. Unlike previous fail-safe devices, the -mv to -mv threshold complies with the ±mv EIA/TIA-48 standard. Receiver Enable (MAX381E and MAX383E only) The MAX381E and MAX383E feature a receiver output enable (, MAX381E or, MAX383E) input that controls the receiver. The MAX381E receiver enable () pin is active high, meaning the receiver outputs are active when is high. The MAX383E receiver enable () pin is active low. Receiver outputs are high impedance when the MAX381E s pin is low and when the MAX383E s pin is high. Table 1. MAX381E/MAX383E Enable Table PART ABLE = HIGH ABLE = LOW MAX381E Active High Z MAX383E High Z Active Low-Voltage Logic Levels (MAX384E only) An increasing number of applications now operate at low-voltage logic levels. To enable compatibility with these low-voltage logic level applications, such as digital FPGAs, the MAX384E V L pin is a user-defined supply voltage that designates the voltage threshold for a logic high. At lower VL voltages, the data rate will also be lower. A logic-high level of 1.6V will receive data at Mbps. Table gives data rates at various voltages at V L. Table. MAX384E Data Rate Table = 3V TO.V V L MAXIMUM DATA RATE 1.6V Mbps.V 33Mbps 3.3V Mbps Applications Information Propagation Delay Matching The MAX38E/MAX381E/MAX383E/MAX384E ( = V L ) exhibit propagation delays that are closely matched from one device to another, even between devices from different production lots. This feature allows multiple data lines to receive data and clock signals with minimal skew with respect to each other. Figure shows the typical propagation delays. Small receiver skew times, the difference between the low-tohigh and high-to-low propagation delay, help maintain a symmetrical ratio (% duty cycle). The receiver skew time t PLH - t PHL is under ns for either a 3.3V supply or a V supply. Multidrop Clock Distribution Low package-to-package skew (8ns max) makes the MAX38E/MAX381E/MAX383E/MAX384E (VCC = V L ) ideal for multidrop clock distribution. When distributing a clock signal to multiple circuits over long transmission lines, receivers in separate locations, and possibly at two different temperatures, would ideally 6
provide the same clock to their respective circuits. Thus, minimal package-to-package skew is critical. The skew must be kept well below the period of the clock signal to ensure that all of the circuits on the network are synchronized. 18 Receivers on the Bus The standard RS-48 input impedance is 1kΩ (oneunit load). The standard RS-48 transmitter can drive 3 unit loads. The MAX38E/MAX381E/MAX383E/ MAX384E present a 1/4-unit-load input impedance RO 1V -1V V OH V OL A B f IN = 1MHz t r, t f 3ns / / t PHL INPUT Figure 1. Receiver Propagation Delay OUT / t PRZH OUTPUT t PLH S3 1.V -1.V V ID R CL GERATOR / / V OH Ω S1 OP S CLOSED S3 = 1.V S1 OP S CLOSED S3 = 1.V (48kΩ), which allows up to 18 receivers on the bus. Any combination of these RS-48 receivers with a total of 3 unit loads can be connected to the same bus. Thermal Protection The MAX38E/MAX381E/MAX383E/MAX384E feature thermal protection. Thermal protection sets the output stage in high-impedance mode when a short circuit occurs at the output, limiting both the power dissipation and temperature. The thermal temperature threshold is +16 C, with a hysteresis of C. OUT 1kΩ Test Circuits/Timing Diagrams / S1 S t PRZL / / V OL S1 CLOSED S OP S3 = -1.V S1 CLOSED S OP S3 = -1.V MAX38E/MAX381E/MAX383E/MAX384E t PRHZ OUT.V V OH t PRLZ FOR MAX381E THE ABLE SIGNAL IS INVERTED. OUT.V V OL Figure. MAX381E/MAX383E Receiver Enable/Disable Timing 7
MAX38E/MAX381E/MAX383E/MAX384E HIGH- VOLTAGE DC SOURCE R C 1MΩ CHARGE-CURRT LIMIT RESISTOR Cs 1pF R D 1.kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR Figure 3a. Human Body ESD Test Model HIGH- VOLTAGE DC SOURCE R C Ω to 1Ω CHARGE-CURRT LIMIT RESISTOR Cs 1pF R D 33Ω DISCHARGE RESISTANCE STORAGE CAPACITOR Figure 4a. IEC 1-4- ESD Test Model A, 1V/div DEVICE UNDER TEST Test Circuits/Timing Diagrams (continued) DEVICE UNDER TEST AMPERES I P 1% 9% 36.8% 1% t RL Ir TIME t DL CURRT WAVEFORM Figure 3b. Human Body Model Current Waveform IPEAK tr =.7ns to 1ns I 1% 9% 1% 3ns 6ns PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) Figure 4b. IEC 1-4- ESD Generator Current Waveform t RO,.V/div 1ns B = GND Figure. Receiver Propagation Delay Driven by External RS- 48 Device 8
DATA IN TOP VIEW GND RO TRANSMITTER 1Ω MAX381E/MAX383E IN REDUNDANT RECEIVER APPLICATION + 1 A MAX38E 3 4 SOT3- Typical Operating Circuit B MAX383E MAX381E GND RO RO1 RO 1 6 A ( ) ARE FOR MAX383E + + MAX381E MAX383E 3 4 SOT3-6 () B PROCESS: BiCMOS GND RO Pin Configurations 1 6 A MAX384E 3 4 SOT3-6 V L Chip Information Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. B LAND PATTERN NO. SOT3 U+ 1-7 9-174 6 SOT3 U6+1 1-8 9-17 MAX38E/MAX381E/MAX383E/MAX384E 9
MAX38E/MAX381E/MAX383E/MAX384E REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED 1/ Initial release 1 3/11 Added lead-free parts to the Ordering Information, deleted the transistor count from the Chip Information section 1, 9 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 1 Maxim Integrated Products, 1 San Gabriel Drive, Sunnyvale, CA 9486 48-737-76 11 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.