a FEATURES Flexible Configuration Differential Input & Output Driver or Two Single-Ended Drivers High Output Power Power Package dbm Differential Line Drive for ADSL Application V p-p Differential Output Voltage, R L = ma Minimum Output Drive/Amp, R L = Thermally Enhanced SOIC ma Minimum Output Drive/Amp, R L = Low Distortion db @ MHz THD, R L =, = V p-p.% &. Differential Gain & Phase, R L = ( Back-Terminated Video Loads) High Speed MHz Bandwidth ( 3 db) 9 V/ s Differential Slew Rate ns Settling Time to.% Thermal Shutdown APPLICATIONS ADSL, HDSL & VDSL Line Interface Driver Coil or Transformer Driver CRT Convergence & Astigmatism Adjustment Video Distribution Amp Twisted Pair Cable Driver PRODUCT DESCRIPTION The consists of two high speed amplifiers capable of supplying a minimum of ma. They are typically configured as a differential driver enabling an output signal of V p-p on ± V supplies. This can be increased further with the use of a TOTAL HARMONIC DISTORTION dbc 8 9 G = + = V p-p R L = Ω (DIFFERENTIAL) R L = Ω (DIFFERENTIAL) k k k M M FREQUEY Hz Total Harmonic Distortion vs. Frequency Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUTIONAL BLOCK DIAGRAM -Pin Through-Hole SIP (Y) & Surface-Mount DDPAK(VR) TAB IS +V S High Output Current Differential Driver 3 9 8 3 = NO CONNECT REFER TO PAGE 3 FOR -PIN SOIC PACKAGE +IN IN OUT +V S V S OUT coupling transformer with a greater than : turns ratio. The low harmonic distortion of db @ MHz into Ω combined with the wide bandwidth and high current drive make the differential driver ideal for communication applications such as subscriber line interfaces for ADSL, HDSL and VDSL. The differential slew rate of 9 V/µs and high load drive are suitable for fast dynamic control of coils or transformers, and the video performance of.% &. differential gain & phase into a load of Ω enable up to backterminated loads to be driven. Three package styles are available, and all work over the industrial temperature range ( C to +8 C). Maximum driver performance is achieved with the power package available as through hole (Y) and surface-mount (VR), while the -pin SOIC (RB) driver performance is reduced due to the smaller package which has a higher thermal resistance. = Vp-p Ω Ω Ω +V AMP G = + AMP V V D = Vp-p R = Ω R = Ω : TRANSFORMER IN +IN R L Ω Subscriber Line Differential Driver = Vp-p Analog Devices, Inc., 99 One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: /39- Fax: /3-83
SPECIFICATIONS (@ T A = + C, V S = ± V dc, B = kω and R LOAD = Ω unless otherwise noted) A Model Conditions V S Min Typ Max Units DYNAMIC PERFORMAE Small Signal Bandwidth ( 3 db) G = + ± MHz G = + ± 9 MHz Bandwidth (. db) G = + ± MHz G = + ± MHz Differential Slew Rate = V p-p, G = + ± 8 9 V/µs Settling Time to.% V Step, G = + ± ns NOISE/HARMONIC PERFORMAE Total Harmonic Distortion f = MHz, R LOAD = Ω, = V p-p ± dbc Input Voltage Noise f = khz, G = + (Single Ended) ±, ±.8 nv/ Hz Input Current Noise (+I IN ) f = khz, G = + ±, ±.8 pa/ Hz Input Current Noise ( I IN ) f = khz, G = + ±, ± 9 pa/ Hz Differential Gain Error NTSC, G = +, R LOAD = Ω ±. % Differential Phase Error NTSC, G = +, R LOAD = Ω ±. Degrees DC PERFORMAE Input Offset Voltage ± 8 mv ± mv T MIN T MAX 3 mv Input Offset Voltage Drift µv/ C Differential Offset Voltage ±. mv ±. mv T MIN T MAX mv Differential Offset Voltage Drift µv/ C Input Bias Current ±, ± 9 µa T MIN T MAX µa +Input Bias Current ±, ± µa T MIN T MAX µa Differential Input Bias Current ±, ± µa T MIN T MAX µa Open-Loop Transresistance ±, ±.. MΩ T MIN T MAX. MΩ INPUT CHARACTERISTICS Differential Input Resistance +Input ± MΩ Input Ω Differential Input Capacitance ±. pf Input Common-Mode Voltage Range ± 3. ± V ± 3. ± V Common-Mode Rejection Ratio T MIN T MAX ±, ± db Differential Common-Mode Rejection Ratio T MIN T MAX ±, ± 8 db OUTPUT CHARACTERISTICS Voltage Swing Single Ended, R LOAD = Ω ±.. ± V ±..8 ± V Differential, R LOAD = Ω ± 3 ± V T MIN T MAX ±.. ± V Output Current, VR, Y R LOAD = Ω ± ma ± 3 ma RB- R LOAD = Ω ± ma Short Circuit Current ±. A Output Resistance ± 3 Ω MATCHING CHARACTERISTICS Crosstalk f = MHz ± db POWER SUPPLY Operating Range 3 T MIN T MAX ±8 V Quiescent Current ± 3 3 ma ± 3 ma T MIN T MAX ± ma ± ma Power Supply Rejection Ratio T MIN T MAX ±, ± db NOTES Output current is limited in the -pin SOIC package to the maximum power dissipation. See absolute maximum ratings and derating curves. See Figure for bandwidth, gain, output drive recommended operation range. 3 Observe derating curves for maximum junction temperature. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS Supply Voltage........................... ±8 V Total Internal Power Dissipation Plastic (Y & VR)... 3. Watts (Observe Derating Curves) Small Outline (RB)... Watts (Observe Derating Curves) Input Voltage (Common Mode)................... ±V S Differential Input Voltage........................ ± V Output Short Circuit Duration...................... Observe Power Derating Curves Can Only Short to Ground Storage Temperature Range Y, VR & RB Package................ C to + C Operating Temperature Range A........................... C to +8 C Lead Temperature Range (Soldering, seconds).... +3 C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Specification is for device in free air with ft/min air flow: -Pin Through Hole and Surface Mount: θ JA = C/Watt; -Pin Surface Mount: θ JA = C/Watt. PIN CONFIGURATION -Pin Thermally-Enhanced SOIC (RB-) THERMAL HEAT TABS +V S * 3 3 TOP VIEW 9 8 (Not to Scale) 8 +IN 9 +IN IN OUT IN OUT V S 3 +V S THERMAL HEAT TABS +V S * = NO CONNECT *HEAT TABS ARE CONNECTED TO THE POSITIVE SUPPLY. MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the is limited by the associated rise in junction temperature. The maximum safe junction temperature for the plastic encapsulated parts is determined by the glass transition temperature of the plastic, about C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of C for an extended period can result in device failure. The has thermal shutdown protection, which guarantees that the maximum junction temperature of the die remains below a safe level, even when the output is shorted to ground. Shorting the output to either power supply will result in device failure. To ensure proper operation, it is important to observe the derating curves and refer to the section on power considerations. It must also be noted that in high (noninverting) gain configurations (with low values of gain resistor), a high level of input overdrive can result in a large input error current, which may result in a significant power dissipation in the input stage. This power must be included when computing the junction temperature rise due to total internal power. MAXIMUM POWER DISSIPATION Watts T J = C 3 θ JA = C/W SOLDERED DOWN TO COPPER HEAT SINK (STILL AIR = FT/MIN) 9 AVR, AY 8 θ JA = C/W (STILL AIR = FT/MIN) NO HEAT SINK AVR, AY 3 θ JA = C/W (STILL AIR = FT/MIN) NO HEAT SINK ARB- 3 3 8 9 AMBIENT TEMPERATURE C Plot of Maximum Power Dissipation vs. Temperature ORDERING GUIDE Temperature Package Package Model Range Description Option AY C to +8 C -Pin Through Hole Y- SIP with Staggered Leads AVR C to +8 C -Pin Surface Mount VR- DDPAK ARB- C to +8 C -Pin Thermally RB- Enhanced SOIC ARB--REEL C to +8 C -Pin Thermally RB- Enhanced SOIC CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE 3
Typical Performance Characteristics 3 COMMON-MODE VOLTAGE RANGE ±Volts SUPPLY CURRENT ma 3 3 3 8 V S = ±V SUPPLY VOLTAGE ±Volts 8 8 JUTION TEMPERATURE C Figure. Input Common-Mode Voltage Range vs. Supply Voltage Figure. Total Supply Current vs. Temperature 8 33 SINGLE-ENDED OUTPUT VOLTAGE V p-p 3 NO LOAD R L = Ω (DIFFERENTIAL) R L = Ω (SINGLE-ENDED) DIFFERENTIAL OUTPUT VOLTAGE V p-p TOTAL SUPPLY CURRENT ma 3 T A = + C SUPPLY VOLTAGE ±Volts 8 8 SUPPLY VOLTAGE ±Volts Figure. Output Voltage Swing vs. Supply Voltage Figure. Total Supply Current vs. Supply Voltage SINGLE-ENDED OUTPUT VOLTAGE Volts p-p 3 V S = ±V k k LOAD RESISTAE (Differential Ω) (Single-Ended Ω/) Figure 3. Output Voltage Swing vs. Load Resistance 3 DIFFERENTIAL OUTPUT VOLTAGE Volts p-p INPUT BIAS CURRENT µa, B +IB, ±V V S = ±V 3 I B I B 8 8 JUTION TEMPERATURE C Figure. Input Bias Current vs. Temperature
8 INPUT OFFSET VOLTAGE mv 8 V S = ±V RTI OFFSET mv T A = C f =.Hz Ω 9.9Ω kω V S = ±V V S = ±V kω V S = ±V R L = Ω 8 JUTION TEMPERATURE C....8...8... LOAD CURRENT Amps Figure. Input Offset Voltage vs. Temperature Figure. Thermal Nonlinearity vs. Output Current Drive SHORT CIRCUIT CURRENT ma SOURCE SINK CLOSED-LOOP OUTPUT RESISTAE Ω.. V S = ±V 8 JUTION TEMPERATURE C 3k k 3k M 3M M 3M M FREQUEY Hz 3M Figure 8. Short Circuit Current vs. Temperature Figure. Closed-Loop Output Resistance vs. Frequency RTI OFFSET mv T A = C R L = Ω V S = ±V V S = ±V f =.Hz Ω 9.9Ω kω kω R L = Ω 8 8 Volts DIFFERENTIAL OUTPUT VOLTAGE V p-p 3 R L = Ω R L = Ω R L = Ω R L = Ω T A = C 8 FREQUEY MHz Figure 9. Gain Nonlinearity vs. Output Voltage Figure. Large Signal Frequency Response
TRANSIMPEDAE VOLTAGE NOISE nv/ Hz INVERTING INPUT CURRENT NOISE NONINVERTING INPUT CURRENT NOISE CURRENT NOISE pa/ Hz TRANSIMPEDAE db 9 8 PHASE PHASE Degrees INPUT VOLTAGE NOISE k k k FREQUEY Hz 3 k k k M M M FREQUEY Hz Figure 3. Input Current and Voltage Noise vs. Frequency Figure. Open-Loop Transimpedance vs. Frequency COMMON-MODE REJECTION db 9 8 3 VIN Ω Ω Ω Ω TOTAL HARMONIC DISTORTION dbc 8 9 G = + = V p-p R L = Ω (DIFFERENTIAL) R L = Ω (DIFFERENTIAL) k k M FREQUEY Hz M M k k k M M FREQUEY Hz Figure. Common-Mode Rejection vs. Frequency Figure. Total Harmonic Distortion vs. Frequency PSRR db 3 8 9. G = + R L = Ω. PSRR +PSRR 3 FREQUEY MHz OUTPUT SWING FROM ±V TO Volts 8 8 %.% %.% GAIN = + 8 SETTLING TIME ns Figure. Power Supply Rejection vs. Frequency Figure 8. Output Swing and Error vs. Settling Time
G = + SINGLE-ENDED SLEW RATE V/µs (PER AMPLIFIER) 3 G = + 8 DIFFERENTIAL SLEW RATE V/µs OPEN-LOOP TRANSRESISTAE MΩ 3 T Z +T Z OUTPUT STEP SIZE V p-p 8 JUTION TEMPERATURE C Figure 9. Slew Rate vs. Output Step Size Figure. Open-Loop Transresistance vs. Temperature 8 PSRR db 8 +PSRR OUTPUT SWING Volts 3 + + R L = Ω R L = Ω PSRR 8 JUTION TEMPERATURE C 8 JUTION TEMPERATURE C Figure. PSRR vs. Temperature Figure 3. Single-Ended Output Swing vs. Temperature 3 CMRR db 9 8 CMRR +CMRR OUTPUT SWING Volts 3 + R L = Ω 8 JUTION TEMPERATURE C 8 JUTION TEMPERATURE C Figure. CMRR vs. Temperature Figure. Differential Output Swing vs. Temperature
DIFF GAIN % DIFF GAIN %..3......3..........3 BACK TERMINATED LOADS (Ω) PHASE GAIN G = + = kω NTSC 3 8 9 PHASE GAIN BACK TERMINATED LOADS (Ω) GAIN PHASE G = + = kω NTSC 3 8 9...3......3...8...... DIFF PHASE Degrees DIFF PHASE Degrees NORMALIZED FLATNESS db ±V ±V. ±V. B A. A B.3 Ω. 9.9Ω ±V. Ω.. 9. 3 FREQUEY MHz 3 8 NORMALIZED FREQUEY RESPONSE db Figure. Differential Gain and Differential Phase (per Amplifier) Figure 8. Bandwidth vs. Frequency, G = + CROSSTALK db 3 8 9 G = + =, ±V = mvrms R L = Ω NORMALIZED OUTPUT VOLTAGE db 3 Ω Ω Ω.3. 3 FREQUEY MHz. 3 FREQUEY MHz Figure. Output-to-Output Crosstalk vs. Frequency Figure 9. 3 db Bandwidth vs. Frequency, G = + OUTPUT VOLTAGE db 3 = dbm Ω 9.9Ω Ω Ω 9 % V µs 9. 3 FREQUEY MHz Figure. 3 db Bandwidth vs. Frequency, G = + Figure 3. V p-p Differential Sine Wave, R L = Ω, f = khz 8
Ω +V µf +V µf.µf.µf 8 R S 8 PULSE GENERATOR Ω Ω.µF µf R L = Ω PULSE GENERATOR Ω Ω.µF µf R L = Ω T R /T F = ps V T R /T F = ps V Figure 3. Test Circuit, Gain = + Figure 3. Test Circuit, Gain = + /R S G = + = 98Ω R L = Ω G = + = Ω R L = Ω R S = Ω mv ns V ns Figure 3. mv Step Response, G = + Figure 3. V Step Response, G = + G = + = Ω R L = Ω +V Ω µf Ω 8.µF PULSE GENERATOR T R /T F = ps Ω Ω.µF µf R L = Ω V ns V Figure 33. V Step Response, G = + Figure 3. Test Circuit, Gain = G = + = Ω R L = Ω G = = Ω R L = Ω V ns mv ns Figure 3. V Step Response, G = + Figure 38. mv Step Response, G = 9
G = = Ω R L = Ω Choice of Feedback and Gain Resistors The fine scale gain flatness will, to some extent, vary with feedback resistance. It therefore is recommended that once optimum resistor values have been determined, % tolerance values should be used if it is desired to maintain flatness over a wide range of production lots. Table I shows optimum values for several useful configurations. These should be used as starting point in any application. Table I. Resistor Values V ns Figure 39. V Step Response, G = THEORY OF OPERATION The is a dual current feedback amplifier with high ( ma) output current capability. Being a current feedback amplifier, the s open-loop behavior is expressed as transimpedance, V O / I IN, or T Z. The open-loop transimpedance behaves just as the open-loop voltage gain of a voltage feedback amplifier, that is, it has a large dc value and decreases at roughly db/octave in frequency. Since R IN is proportional to /g M, the equivalent voltage gain is just T Z g M, where the g M in question is the transconductance of the input stage. Using this amplifier as a follower with gain, Figure, basic analysis yields the following result: V O T Z ( S) = G T Z ( S)+G R IN + where: G = + R IN = /g M Ω R N R IN ( ) ( ) G = + 99 99 + 99 99 + 99 + K PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS As to be expected for a wideband amplifier, PC board parasitics can affect the overall closed-loop performance. Of concern are stray capacitances at the output and the inverting input nodes. If a ground plane is to be used on the same side of the board as the signal traces, a space ( mm min) should be left around the signal lines to minimize coupling. POWER SUPPLY BYPASSING Adequate power supply bypassing can be critical when optimizing the performance of a high frequency circuit. Inductance in the power supply leads can form resonant circuits that produce peaking in the amplifier s response. In addition, if large current transients must be delivered to the load, then bypass capacitors (typically greater than µf) will be required to provide the best settling time and lowest distortion. A parallel combination of. µf and. µf is recommended. Under some low frequency applications, a bypass capacitance of greater than µf may be necessary. Due to the large load currents delivered by the, special consideration must be given to careful bypassing. The ground returns on both supply bypass capacitors as well as signal common must be star connected as shown in Figure. +V S Figure. Recognizing that G R IN << for low gains, it can be seen to the first order that bandwidth for this amplifier is independent of gain (G). Considering that additional poles contribute excess phase at high frequencies, there is a minimum feedback resistance below which peaking or oscillation may result. This fact is used to determine the optimum feedback resistance,. In practice parasitic capacitance at the inverting input terminal will also add phase in the feedback loop, so picking an optimum value for can be difficult. Achieving and maintaining gain flatness of better than. db at frequencies above MHz requires careful consideration of several issues. +IN IN (OPTIONAL) V S +OUT OUT Figure. Signal Ground Connected in Star Configuration
DC ERRORS AND NOISE There are three major noise and offset terms to consider in a current feedback amplifier. For offset errors refer to the equation below. For noise error the terms are root-sum-squared to give a net output error. In the circuit below (Figure ), they are input offset (V IO ) which appears at the output multiplied by the noise gain of the circuit ( + / ), noninverting input current (I BN R N ) also multiplied by the noise gain, and the inverting input current, which when divided between and and subsequently multiplied by the noise gain always appear at the output as I BI. The input voltage noise of the is less than nv/ Hz. At low gains though, the inverting input current noise times is the dominant noise source. Careful layout and device matching contribute to better offset and drift specifica-tions for the compared to many other current feedback amplifiers. The typical performance curves in conjunction with the equations below can be used to predict the performance of the in any application. = V IO + R F ± I BN R N + R F ± I BI Figure gives the relationship between output voltage swing into various loads and the power dissipated by the (P IN ). This data is given for both sine wave and square wave (worst case) conditions. It should be noted that these graphs are for mostly resistive (phase < ± ) loads. When the power dissipation requirements are known, Equation and the graph on Figure can be used to choose an appropriate heat sinking configuration. P IN Watts 3 f = khz SQUARE WAVE SINE WAVE R L = Ω R L = Ω R L = Ω 3 Volts p-p R N I BI I BN Figure. Output Offset Voltage POWER CONSIDERATIONS The ma drive capability of the enables it to drive a Ω load at V p-p when it is configured as a differential driver. This implies a power dissipation, P IN, of nearly watts. To ensure reliability, the junction temperature of the should be maintained at less than C. For this reason, the will require some form of heat sinking in most applications. The thermal diagram of Figure 3 gives the basic relationship between junction temperature (T J ) and various components of θ JA. T J =T A + P IN θ JA Equation Figure. Total Power Dissipation vs. Differential Output Voltage Normally, the will be soldered directly to a copper pad. Figure plots θ JA against size of copper pad. This data pertains to copper pads on both sides of G epoxy glass board connected together with a grid of feedthroughs on mm centers. This data shows that loads of ohms or less will usually not require any more than this. This is a feature of the s - lead power SIP package. An important component of θ JA is the thermal resistance of the package to heatsink. The data given is for a direct soldered connection of package to copper pad. The use of heatsink grease either with or without an insulating washer will increase this number. Several options now exist for dry thermal connections. These are available from Bergquist as part # SP-9. Consult with the manufacturer of these products for details of their application. 3 T J θa (JUTION TO DIE MOUNT) 3 T A CASE θ B (DIE MOUNT TO CASE) θ A + θ B = θ JC θ JA C/W AVR, AY (θ JC = C/W) T J θ JC θ CA P IN θ JA T A WHERE: P IN = DEVICE DISSIPATION T A = AMBIENT TEMPERATURE T J = JUTION TEMPERATURE θ JC = THERMAL RESISTAE JUTION TO CASE θ CA = THERMAL RESISTAE CASE TO AMBIENT.k k.k k.k COPPER HEAT SINK AREA (TOP AND BOTTOM) mm Figure. Power Package Thermal Resistance vs. Heat Sink Area Figure 3. A Breakdown of Various Package Thermal Resistances
Other Power Considerations There are additional power considerations applicable to the. First, as with many current feedback amplifiers, there is an increase in supply current when delivering a large peak-to-peak voltage to a resistive load at high frequencies. This behavior is affected by the load present at the amplifier s output. Figure summarizes the full power response capabilities of the. These curves apply to the differential driver applications (e.g., Figure 9 or Figure 3). In Figure, maximum continuous peak-to-peak output voltage is plotted vs. frequency for various resistive loads. Exceeding this value on a continuous basis can damage the. The is equipped with a thermal shutdown circuit. This circuit ensures that the temperature of the die remains below a safe level. In normal operation, the circuit shuts down the at approximately 8 C and allows the circuit to turn back on at approximately C. This built-in hysteresis means that a sustained thermal overload will cycle between power-on and power-off conditions. The thermal cycling typically occurs at a rate of ms to several seconds, depending on the power dissipation and the thermal time constants of the package and heat sinking. Figures and illustrate the thermal shutdown operation after driving OUT to the + rail, and OUT to the rail, and then short-circuiting to ground each output of the. The will not be damaged by momentary operation in this state, but the overload condition should be removed. 9 OUT resistor should be placed in series with each output. See Figure 8. This circuit can deliver 8 ma into loads of up to. Ω. Ω Ω Ω +V 8 V.µF 9 µf.µf µf Figure 8. Parallel Operation for High Current Output Differential Operation Various circuit configurations can be used for differential operation of the. If a differential drive signal is available, the two halves can be used in a classic instrumentation configuration to provide a circuit with differential input and output. The circuit in Figure 9 is an illustration of this. With the resistors shown, the gain of the circuit is. The gain can be changed by changing the value of. This circuit, however, provides no common-mode rejection. +V Ω Ω R L % OUT +IN Ω 8.µF µf OUT V µs Ω R L Figure. OUT Shorted to Ground, Square Wave Is OUT, = kω, = Ω IN Ω 9 OUT.µF µf 9 % OUT V OUT Figure. OUT Shorted to Ground, Square Wave Is OUT, = kω, = Ω Parallel Operation To increase the drive current to a load, both of the amplifiers within the can be connected in parallel. Each amplifier should be set for the same gain and driven with the same signal. In order to ensure that the two amplifiers share current, a small ms V Figure 9. Fully-Differential Operation Creating Differential Signals If only a single ended signal is available to drive the and a differential output signal is desired, several circuits can be used to perform the single-ended to differential conversion. One circuit to perform this is to use a dual op amp as a predriver that is configured as a noninverter and inverter. The circuit shown in Figure performs this function. It uses an AD8 dual op amp with the gain of one amplifier set at + and the gain of the other at. The kω resistor across the input terminals of the follower makes the noise gain (NG = ) equal to the inverter s. The two outputs then differentially drive the inputs to the with no common-mode signal to first order.
+V +V +V kω.µf 3 8 AD8 kω Ω 8.µF µf AMP 8 Ω Ω R L Ω R L kω AD8 kω.µf Ω 9 AMP 9 V.µF µf V V Figure. Differential Driver with Single-Ended Differential Converter Another means for creating a differential signal from a singleended signal is to use a transformer with a center-tapped secondary. The center tap of the transformer is grounded and the two secondary windings are connected to obtain opposite polarity signals to the two inputs of the amplifiers. The bias currents for the inputs are provided by the center tap ground connection through the transformer windings. One advantage of using a transformer is its ability to provide isolation between circuit sections and to provide good commonmode rejection. The disadvantages are that transformers have no dc response and can sometimes be large, heavy and expensive. This circuit is shown in Figure. Ω Ω Ω Ω Ω +V 8 V 9.µF µf kω kω.µf µf Figure. Differential Driver with Transformer Input Direct Single-Ended to Differential Conversion Two types of circuits can create a differential output signal from a single-ended input without the use of any other components other than resistors. The first of these is illustrated in Figure. R L Figure. Direct Single-Ended to Differential Conversion Amp has its + input driven with the input signal, while the + input of Amp is grounded. Thus the input of Amp is driven to virtual ground potential by its output. Therefore Amp is configured for a noninverting gain of five, ( + / ), because is connected to the virtual ground of Amp s input. When the + input of Amp is driven with a signal, the same signal appears at the input of Amp. This signal serves as an input to Amp configured for a gain of, ( / ). Thus the two outputs move in opposite directions with the same gain and create a balanced differential signal. This circuit can work at various gains with proper resistor selection. But in general, in order to change the gain of the circuit, at least two resistor values will have to be changed. In addition, the noise gain of the two op amps in this configuration will always be different by one, so the bandwidths will not match. A second circuit that has none of the disadvantages mentioned in the above circuit creates a differential output voltage feedback op amp out of the pair of current feedback op amps in the. This circuit, drawn in Figure 3, can be used as a high power differential line driver, such as required for ADSL (asymmetrical digital subscriber loop) line driving. Each of the s op amps is configured as a unity gain follower by the feedback resistors (R A ). Each op amp output also drives the other as a unity gain inverter via the two R B s, creating a totally symmetrical circuit. If the + input to Amp is grounded and a small positive signal is applied to the + input of Amp, the output of Amp will be driven to saturation in the positive direction and the output of Amp driven to saturation in the negative direction. This is similar to the way a conventional op amp behaves without any feedback. 3
(Ω) (OPTIONAL) +V R I V CC 8 AMP R A R A AMP 9 V CC ~pf.µf µf R B R B Ω Ω (OPTIONAL) Ω Twelve Channel Video Distribution Amplifier The high current of the enables it to drive up to twelve standard Ω reverse terminated video loads. Figure is a schematic of such an application. The input video signal is terminated in Ω and applied to the noninverting inputs of both amplifiers of the. Each amplifier is configured for a gain of two to compensate for the divide-by-two feature of each cable termination. Six separate Ω resistors for each amplifier output are used for the cable back termination. In this manner, all cables are relatively independent of each other and small disturbances on any cable will not have an effect on the other cables. When driving six video cables in this fashion, the load seen by each amplifier output is resistive and is equal to Ω/ or Ω. The differential gain is.% and the differential phase is.. +V V.µF µf Figure 3. Single-Ended to Differential Driver If a resistor ( ) is connected from the output of Amp to the + input of Amp, negative feedback is provided which closes the loop. An input resistor (R I ) will make the circuit look like a conventional inverting op amp configuration with differential outputs. The inverting input to this dual output op amp becomes Pin, the positive input of Amp. The gain of this circuit from input to either output will be ± / R I. Or the single-ended to differential gain will be /R I. The differential outputs can be applied to the primary of a transformer. If each output can swing ± V, the effective swing on the transformer primary is V p-p. The optional capacitor can be added to prevent any dc current in the transformer due to dc offsets at the output of the. B B B3 +V V TP TP3 C TP +V C.µF R3 VIDEO IN Ω Ω Ω 8 V 9.µF µf Ω.µF µf VIDEO OUT TO Ω CABLES Figure. Video Distribution Amp Driving Video Cables J J R R R R R9 C3 8 µf U R C3 R R R R C R8 J 3 R T R J 3 J 3 TP V C.µF C9 R 9 8 J3 R9 R R R C µf 9 U R R3 JP J R8 Figure. Evaluation Board Schematic
Figure. AVR Evaluation Board Assembly Drawing Figure. AVR Evaluation Board Layout (Component Side) Figure 8. AVR Evaluation Board Layout (Solder Side)
OUTLINE DIMENSIONS Dimensions shown in inches and (mm).. (.9). (3.8) BSC.8 (3.).9 (.3).8 (.3) PIN -Pin Surface Mount DDPAK (VR-).39 (.). (.) BSC.98 (.).8 (9.). (.) BSC.3 (.9). (.).3 (3.9) TYP. (.) TYP. (3.).8 (.3). (.) PLACES.9 (.) DIA PLACES.8 (.). (.3) SEATING PLANE. (.8). (.).3 (.). (.) 8.88 (.).8 (.). (.). (.3).9 (.3).8 (.3). (.8). (.) -Pin Through Hole SIP with Staggered Leads (Y-). (.9). (3.8) BSC.39.8 (3.) (.) PIN SEATING PLANE.98 (.).8 (9.). (.) BSC.3 (.9). (.). (.8) BSC.3 (3.9) TYP.. ±. (.) (.3 TYP ±.) SHORT.8 (.3) LEAD. (.) PLACES.9 (.) DIA PLACES. (3.).8 (.). (.3).9 ±. (.38 ±.).3 (.). (.). ±. (.9 ±.) LONG LEAD. (.). (.3).9 ±. (. ±.). ±. (9. ±.).9 ±. (.9 ±.) C /9 -Pin Thermally Enhanced SOIC (RB-). (.).98 (.) 3.99 (.).9 (.).93 (.).393 (.) PIN.3 (.).9 (.3).9 (.).98 (.) x.8 (.3). (.). (.) BSC. (.).3 (.33) SEATING PLANE. (.3).9 (.3) 8. (.). (.) PRINTED IN U.S.A.