19-; Rev 3; 2/1 EVALUATION KIT MANUAL FOLLOWS DATA SHEET 2.7V, Single-Supply, Cellular-Band General Description The // power amplifiers are designed for operation in IS-9-based CDMA, IS-136- based TDMA, and PDC cellular telephones operating in the 9MHz range. When matched for CDMA operation and biased with margin over the adjacent and alternate channel specification (-dbc/-6dbc), the amplifiers achieve dbm output power with 37% efficiency (). At +dbm outputa very common power level for CDMA phonesthe still has 7% efficiency, yielding excellent overall talk time. At the same power level, the / have an unprecedented %/17% efficiency, while still obtaining %/% efficiency at maximum output power. The // have internally referenced bias ports that are normally terminated with simple resistors. The bias ports allow customization of ACPR margin and gain. They can also be used to throttle back bias current when generating low power levels. The // have excellent gain stability over temperature (±.db), so overdesign of driver stages and excess driver current are dramatically reduced, further increasing the phone s talk time. The devices can be operated from +2.7V to +V while meeting all ACPR specifications over the entire temperature range. Nonlinear efficiency is % when matched for linear operation, or % when matched for non-linear-only operation (). The devices are packaged in a -pin TSSOP with exposed pad (EP). For module or direct chip attach applications, the is also available in die form. Applications Cellular-Band CDMA Dual-Mode Phones Cellular-Band PDC Phones Cellular-Band TDMA Dual-Mode Phones Dual-Mode Phones 2-Way Pagers Power-Amplifier Modules DEVICE Selector Guide (%) CDMA AT +dbm CDMA AT +dbm TDMA AT +dbm Features Low Average CDMA Current Consumption in Typical Urban Scenario ma () 9mA () ma ().µa Shutdown Mode Eliminates External Supply Switch ±.db Gain Variation Over Temperature No External Reference or Logic Interface Circuitry Needed Supply Current and ACPR Margin Dynamically Adjustable +2.7V to +V Single-Supply Operation 37% Efficiency at +2.7V Operation PART TOP VIEW IN1 1 PWR 2 3 BIAS1H SHDN 6 BIAS2L 7 OUT1 TEMP. RANGE Ordering Information EUE - C to + C TSSOP-EP E/D - C to + C Dice* EUE - C to + C TSSOP-EP EUE - C to + C TSSOP-EP *Contact factory for dice specifications. Pin Configurations / PIN- PACKAGE BIAS IN BIAS2H 1 13 GND NFP 11 OUT 1 BIAS1L 9 OUT1 TSSOP-EP mm x 6.mm // 37 7 17 2 TSSOP-EP Pin Configurations continued at end of data sheet. Maxim Integrated Products 1 For price, delivery, and to place orders, please contact Maxim Distribution at 1--629-62, or visit Maxim s website at www.maxim-ic.com.
// ABSOLUTE MAXIMUM RATINGS to GND (no RF input)...-.3v to +6.V Logic Inputs to GND...-.3V to ( +.3V) BIAS to GND...-.3V to ( +.3V) RF Input Power...+13dBm (mw) Logic Input Current...±1mA Output VSWR with +13dBm Input...2.:1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS Total DC Power Dissipation (T PADDLE = +1 C) -Pin TSSOP-EP (derate 6mW/ C above T PADDLE = +1 C)...W θja... C/W Operating Temperature Range...- C to + C Junction Temperature...+ C Storage Temperature Range...-6 C to + C Lead Temperature (soldering, 1sec)...+ C ( = +2.7V to +V, T A = T MIN to T MAX, no input signal applied, V SHDN = 2.V. Typical values are at = +3.3V and, unless otherwise noted.) (Note ) Idle Current PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Voltage Range 2.7. PWR = 9 / I CC 3 Shutdown Supply Current I CC SHDN =. 1 µa Logic Input Current High Logic = -1 µa Logic Input Current Low Logic = GND -1 1 µa Logic Threshold High 2. V Logic Threshold Low. V 3 V ma AC ELECTRICAL CHARACTERISTICS ( EV kit, = V PWR = V SHDN = +3.3V,, f IN = 36MHz, CDMA modulation, SHDN =, matching networks tuned for MHz to 9MHz operation, Ω system, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Frequency Range (Notes 1, 2) f IN PWR = or GND 9 MHz 23. PWR = Power Gain (Note 1) G P T A = T MIN to T MAX db 1 21 Gain Variation vs. Temperature (Note 1) T A = T MIN to T MAX, relative to ±. db Output Power (High-Power Mode) (Note 1) Output Power (Low-Power Mode) (Note 1) PWR =, P IN adjusted to meet ACPR 27 specification, f IN = MHz to 9MHz P OUT PWR = = 2.V, P IN adjusted to meet 27 ACPR specification, f IN = MHz to 9MHz, P IN adjusted to meet ACPR. specification, f IN = MHz to 9MHz P OUT, = 2.V, P IN adjusted to meet 1. ACPR specification, f IN = MHz to 9MHz dbm dbm 2
AC ELECTRICAL CHARACTERISTICS (continued) ( EV kit, = V PWR = V SHDN = +3.3V,, f IN = 36MHz, CDMA modulation, SHDN =, matching networks tuned for MHz to 9MHz operation, Ω system, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AMPS Output Power (Note 1) P OUT P IN = dbm. 31 dbm Adjacent-Channel Power Ratio Limit (Notes 1, 2) Alternate-Channel Power Ratio Limit (Notes 1, 2) Power-Added Efficiency (Note 3) V ACPR CC = 2.V to.v, offset = khz, - dbc khz BW, f IN = MHz to 9MHz V ACPR CC = 2.V to.v, offset = 19kHz, -6 dbc khz BW, f IN = MHz to 9MHz AMPS Power-Added Efficiency PAE P IN = dbm % Power-Mode Switching Time (Note ) ns Turn-On Time (Notes 1, ) PWR = or GND 1 µs Maximum Input VSWR VSWR f IN = MHz to 9MHz, or 2.:1 Nonharmonic Spurious due to Load Mismatch (Notes 1, ) PAE PWR =, P IN adjusted to meet ACPR specification, P IN adjusted to meet ACPR specification P IN = 1dBm -6 dbc Noise Power (Note 6) Measured at 1MHz -139, measured at 1MHz -136 dbm/hz AMPS Noise Power (Note 6) Measured at 1MHz, P IN = dbm -13 dbm/hz Harmonic Suppression (Note 7) dbc % // AC ELECTRICAL CHARACTERISTICS ( EV kit, = V SHDN = +3.3V,, f IN = 36MHz, CDMA modulation, matching networks tuned for MHz to 9MHz operation, Ω system, unless otherwise indicated.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Frequency Range (Notes 1, 2) f IN 9 MHz Power Gain (Note 1) G P. T A = T MIN to T MAX 23 db Gain Variation vs. Temperature (Note 1) P IN adjusted to meet ACPR specification, 27 f IN = MHz to 9MHz Output Power (Note 1) P OUT = 2.V, P IN adjusted to meet ACPR. specification, f IN = MHz to 9MHz ±.7 db AMPS Output Power (Note 1) P OUT P IN = dbm 31 dbm Adjacent-Channel Power Ratio (Notes 1, 2) Alternate-Channel Power Ratio (Notes 1, 2) T A = T MIN to T MAX, relative to dbm V ACPR CC = 2.V to.v, offset = khz, - - dbc khz BW, f IN = MHz to 9MHz V ACPR CC = 2.V to.v, offset = 19kHz, -6-7 dbc khz BW, f IN = MHz to 9MHz 3
// AC ELECTRICAL CHARACTERISTICS (continued) ( EV kit, = V SHDN = +3.3V,, f IN = 36MHz, CDMA modulation, matching networks tuned for MHz to 9MHz operation, Ω system, unless otherwise indicated.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power-Added Efficiency P IN adjusted to give P OUT = dbm 37 PAE % (Note 3) P IN adjusted for P OUT = dbm 7 AMPS Power-Added Efficiency PAE P IN = dbm % Turn-On Time (Notes 1, ) 1 µs Maximum Input VSWR VSWR f IN = MHz to 9MHz 1.3:1 Nonharmonic Spurious Due to Load Mismatch (Notes 1, ) P IN = 1dBm -6 dbc Noise Power (Note 6) Measured at 1MHz -1 dbm/hz AMPS Noise Power (Note 6) Measured at 1MHz, P IN = dbm -139 dbm/hz Harmonic Suppression (Note 7) 7 dbc AC ELECTRICAL CHARACTERISTICS ( EV kit, = V SHDN = +3.3V,, f IN = 36MHz, CDMA modulation, matching networks tuned for MHz to 9MHz operation, Ω system, unless otherwise indicated.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Frequency Range (Notes 1, 2) f IN PWR = or GND 9 MHz. PWR = Power Gain (Note 1) G P T A = T MIN to T MAX 23 db 27. Gain Variation vs. Temperature (Note 1) T A = T MIN to T MAX, relative to ±. db Output Power (High-Power Mode) (Note 1) PWR =, P IN adjusted to meet ACPR 27 specification, f IN = MHz to 9MHz P OUT PWR = = 2.V, P IN adjusted to meet 27 ACPR specification, f IN = MHz to 9MHz dbm Output Power (Low-Power Mode) (Note 1), P IN adjusted to meet ACPR 1. specification, f IN = MHz to 9MHz P OUT, = 2.V, P IN adjusted to meet 13 1 ACPR specification, f IN = MHz to 9MHz AMPS Output Power (Note 1) P OUT P IN = dbm 31 dbm Adjacent-Channel Power Ratio Limit (Notes 1, 2) ACPR - dbc = 2.V to.v, offset = khz, khz BW, f IN = MHz to 9MHz dbm Alternate-Channel Power Ratio Limit (Notes 1, 2) V ACPR CC = 2.V to.v, offset = 19kHz, -6 dbc khz BW, f IN = MHz to 9MHz Power-Added Efficiency (Note 3) PAE PWR =, P IN adjusted to meet ACPR specification, P IN adjusted to meet ACPR specification 17 %
AC ELECTRICAL CHARACTERISTICS (continued) ( EV kit, = V PWR = V SHDN = +3.3V,, f IN = 36MHz, CDMA modulation, SHDN =, matching networks tuned for MHz to 9MHz operation, Ω system, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AMPS Power-Added Efficiency PAE P IN = dbm % Power-Mode Switching Time (Note ) ns Turn-On Time (Notes 1, ) PWR = or GND 1 µs Maximum Input VSWR VSWR f IN = MHz to 9MHz, or 2.:1 Nonharmonic Spurious due to Load Mismatch (Notes 1, ) P IN = 1dBm -6 dbc Noise Power (Note 6) Measured at 1MHz -137, measured at 1MHz -1 dbm/hz AMPS Noise Power (Note 6) Measured at 1MHz, P IN = dbm -136 dbm/hz Harmonic Suppression (Note 7) dbc Note 1: Minimum and maximum values are guaranteed by design and characterization, not production tested. Note 2: P MAX is met over this frequency range at the ACPR limit with a single matching network. For optimum performance at other frequencies, the output matching network must be properly designed. See the Applications Information section. Operation between 7MHz and 1MHz is possible but has not been characterized. Note 3: PAE is specified into a Ω load, while meeting ACPR requirements. Note : Time from logic transition until P OUT is within 1dB of its final mean power. Note : Murata isolator as load with :1 VSWR any phase angle after isolator. Note 6: Noise power can be improved by using the circuit in Figures 1, 2, and 3. Note 7: Harmonics measured on evaluation kit, which provides some harmonic attenuation in addition to the rejection provided by the IC. The combined suppression is specified. Note : + C guaranteed by production test, + C guaranteed through correlation to worst-case temperature testing. // Typical Operating Characteristics (// EV kits, = +3.3V, SHDN =, CDMA modulation,, unless otherwise noted.) SUPPLY CURRENT (na) 1 1 1 6 SHUTDOWN CURRENT vs. SUPPLY VOLTAGE SHDN = GND NO INPUT DRIVE 2. 3. 3..... -1 GAIN vs. SUPPLY VOLTAGE PWR = 2. 3. 3.... -2 1 GAIN vs. SUPPLY VOLTAGE 2. 3. 3.... -3
// SUPPLY CURRENT (ma) 36 3 6 vs. SUPPLY VOLTAGE PWR = 2. 3. 3.... OUTPUT POWER vs. INPUT POWER -1 - -1 - -6 - -2 INPUT POWER (dbm) SUPPLY CURRENT PWR = /3.3V AT /+ C/+ C - -7-1 SUPPLY CURRENT (ma) Typical Operating Characteristics (continued) (// EV kits, = +3.3V, SHDN =, CDMA modulation,, unless otherwise noted.) 1 13 11 1 9 27 23 1 vs. SUPPLY VOLTAGE 2. 3. 3.... GAIN PWR = 1 3 SUPPLY CURRENT - - -11 ACPR (dbc) 31 29 27 23 21 - - - -6-7 OUTPUT POWER vs. INPUT POWER PWR = 2 6 INPUT POWER (dbm) GAIN -1-1 ADJACENT-CHANNEL POWER RATIO PWR = -6-9 - 1 3 3 6 9 1 - - -1 1 6
ACPR (dbc) - - - - -6-6 3 36 3 ADJACENT-CHANNEL POWER RATIO -1-1 vs. FREQUENCY PWR = P OUT = dbm.%.7% 33.2% 33.1% 33.% 36 2 FREQUENCY (MHz) -13 - Typical Operating Characteristics (continued) (// EV kits, = +3.3V, SHDN =, CDMA modulation,, unless otherwise noted.) GAIN vs. SUPPLY VOLTAGE 2. 3. 3.... -19 3 1 1 39 37 3 33 31 29 PWR = VCC T A = T MIN TO T MAX 1 3 vs. FREQUENCY P OUT = dbm % 11% % % 36 2 FREQUENCY (MHz) vs. SUPPLY VOLTAGE 7 11% 2. 3. 3.... -1-17 - SUPPLY CURRENT (na) 1 1 1 6 31 29 27-1 - 1 SHDN = GND NO INPUT DRIVE SHUTDOWN CURRENT vs. SUPPLY VOLTAGE 2. 3. 3..... OUTPUT POWER vs. INPUT POWER 2 6 INPUT POWER (dbm) - -1-21 //
// 27 23 3 1 GAIN 1 3 1 3 - - SUPPLY CURRENT (ma) Typical Operating Characteristics (continued) (// EV kits, = +3.3V, SHDN =, CDMA modulation,, unless otherwise noted.) 6 3 36 3 SUPPLY CURRENT /3.3V AT /+ C/+ C USING OPTIONAL TB CIRCUIT IN FIGURE 2 1 3 36.% vs. FREQUENCY 36.7% 36.% 36.7% 36.3% 31 36 1 6 FREQUENCY (MHz) -23 - ACPR (dbc) POWER (dbm) - - - -6-7 - 1-1 - - - - ADJACENT-CHANNEL POWER RATIO - -1 1 TDMA POWER SPECTRUM -6 CENTER 36MHz.kHz/div SPAN 2.kHz - -27 SUPPLY CURRENT (na) 1 1 1 6 SHUTDOWN CURRENT vs. SUPPLY VOLTAGE SHDN = GND NO INPUT DRIVE 2. 3. 3..... -1 GAIN vs. SUPPLY VOLTAGE PWR = 2. 3. 3.... toc2 3 GAIN vs. SUPPLY VOLTAGE PIN = SET FOR ACPR LIMIT 2. 3. 3.... toc3
36 3 vs. SUPPLY VOLTAGE PWR = 2. 3. 3.... OUTPUT POWER vs. INPUT POWER -1 - -1 - -6 - -2 INPUT POWER (dbm) toc toc7 Typical Operating Characteristics (continued) (// EV kits, = +3.3V, SHDN =, CDMA modulation,, unless otherwise noted.) 19 1 17 1 27 23 vs. SUPPLY VOLTAGE 2. 3. 3.... GAIN PWR = 1 3 toc toc 31 29 27 29 27 OUTPUT POWER vs. INPUT POWER PWR = 1 2 3 6 7 INPUT POWER (dbm) GAIN -1-1 toc6 toc9 // SUPPLY CURRENT SUPPLY CURRENT ADJACENT-CHANNEL POWER RATIO SUPPLY CURRENT (ma) 6 PWR = /3.3V AT /+ C/+ C toc1 SUPPLY CURRENT (ma) 1 toc11 ACPR (dbc) - - - -6-7 PWR = toc 1 3 3 6 9 1 - - -1 1 9
// ACPR (dbc) - - - -6-7 ADJACENT-CHANNEL POWER RATIO - -1-1 3 36 3 31.3% toc13 3 1 vs. FREQUENCY PWR = P OUT = dbm 31.6% 31.9% Typical Operating Characteristics (continued) (// EV kits, = +3.3V, SHDN =, CDMA modulation,, unless otherwise noted.) PWR = 1 3.2%.% toc 17.6% toc1 1 vs. FREQUENCY P OUT = dbm 17.% 17.3% 17.%.9% -1-1 toc17 toc 1 36 2 FREQUENCY (MHz) 36 2 FREQUENCY (MHz) 1
PIN 1 2 3,, 1 6 7, 9 1 11 1 3, 2, 6, 9 7, 1, 11, 1, NAME IN1 PWR BIAS1H SHDN BIAS2L OUT1 BIAS1L OUT NFP N.C. FUNCTION RF Input Port. Requires external matching network. Pin Description Mode-Select Input. Drive low to select the low-power mode (BIAS1L and BIAS2L). Drive high to select high-power mode (BIAS1H and BIAS2H). Voltage Supply. Bypass with capacitors connected between this pin and GND. High-Power Mode First Stage Bias Control. See General Description. Shutdown Control Input. Drive SHDN low to enable shutdown. Drive high for normal operation. On the, make sure that both pins get driven simultaneously. To place the / into shutdown mode, also pull the PWR pin low. Low-Power Mode Second Stage Bias Control. See General Description. RF Output Ports. Require an appropriate output matching network and collector bias. Low-Power Mode First Stage Bias Control. See General Description. RF Output Port. Requires an appropriate output matching network and collector bias. Noise Filtering Pin. Connect noise filtering network as described in Noise Filtering section. If unused, leave open. Not Internally Connected. Do not make any connections to these pins. // 13, Slug 13, Slug GND Ground. Solder the package slug to high-thermal-conductivity circuit board ground plane. BIAS2H High-Power Mode Second Stage Bias Control. See General Description. IN RF Input Port. Requires external matching network. Detailed Description The // are linear power amplifiers (PAs) intended for CDMA and TDMA applications. The devices have been fully characterized in the MHz to 9MHz U.S. cellular band and can be used from 7MHz to 1MHz by adjusting the input and output match. In CDMA applications, they provide typically dbm of output power and up to 37% poweradded efficiency (PAE) from a single +2.7V to +V supply. In TDMA applications, efficiency is 2% at dbm of output power. An inherent drawback of traditional PAs is that their efficiency drops rapidly with reduced output power. For example, in a PA designed for maximum efficiency at +dbm, the efficiency at +dbm falls well below.% (over 21mA from a +3.3V supply). This behavior significantly reduces talk time in CDMA phones because over 9% of the time they are at output powers below +dbm. The // are optimized for lowest current draw at output powers that are most likely to occur in real-life situations. This provides up to % reduced average PA current. High-Power and Low-Power Modes The / are designed to provide optimum PAE in both high- and low-power modes. For a +3.3V supply, maximum output power is +dbm in high-power mode and +dbm in low-power mode. Use the system s microcontroller to determine required output power, and switch between the two modes as appropriate with the PWR logic pin. Bias Control The bias current of the first stage in low-power mode is proportional to the current flowing out of BIAS1L. The voltage at BIAS1L is fixed by an internal bandgap refer- 11
// ence, so the current out of this pin is inversely proportional to the value of the resistor between this pin and ground. Similarly, the bias current of the first stage in high-power mode is proportional to the current flowing out of BIAS1H. The current in the second stage is proportional to the currents out of BIAS2L and BIAS2H for low- and high-power modes, respectively. Additionally, these resistors allow for customization of gain and alternate- and adjacent-channel power ratios. Increasing the bias current in the first stage increases the gain and improves alternate-channel power ratio at the expense of efficiency. Increasing the bias current in the second stage increases gain at the expense of efficiency as well as adjacent- and alternate-channel power ratios. The PA bias current can be dynamically adjusted by summing a current into the bias pin of interest with an external source such as a DAC. See the Typical Application Circuit for using a voltage DAC and current setting resistors RTB1 and RTB2. Choosing RTB1 = R1 and RTB2 = R2 allows current adjustment RFIN between ma to double the nominal idle current with DAC voltages between V and 2.V. The DAC must be able to source approximately 1µA. Shutdown Mode Pull pins 2 and 6 low to place the // into shutdown mode. In this mode, all gain stages are disabled and supply current drops to.µa. Increasing Efficiency Further The incorporates an additional external switch to increase efficiency to 17% at +dbm and to % at +dbm. This efficiency increase is mainly due to the additional isolation between the high- and lowpower outputs provided by the external switch. Applications Information External Components The // require matching circuits at their inputs and outputs for operation in a Ω system. The application circuits in Figures 1, 2, and 3 describe the topology of the matching circuits for C2 L1 C1 L2 C3 L3 C11 PWR 1 2 RH2 C SHDN RH1 3 6 BIAS 1 13 11 C13 OPTIONAL NOISE-REDUCTION CIRCUIT L6 C6 C RL2 L 7 1 9 RL1 C9 C L C C7 RFOUT Figure 1. Typical Application Circuit
each device; suggested component values, suppliers, and part numbers are listed in Table 1. These values are optimized for best simultaneous efficiency and return loss performance. Use high-quality components in these matching circuits for greatest efficiency. Layout and Power-Supply Bypassing A properly designed PC board is essential to any RF/microwave circuit. Be sure to use controlled impedance lines on all high-frequency inputs and outputs. Proper grounding of the GND pins is fundamental; if the PC board uses a topside RF ground, connect all GND pins (especially the TSSOP package exposed GND pad) directly to it. On boards where the ground plane is not on the component side, it s best to connect all GND pins to the ground plane with plated through-holes close to the package. OPTIONAL TB CIRCUIT TX POWER R TB1 R TB2 C11 C3 L1 L3 RFIN C1 1 2 3 To minimize coupling between different sections of the system, the ideal power-supply layout is a star configuration with a large decoupling capacitor at a central node. The traces branch out from this central node, each leading to a separate node on the PC board. A second bypass capacitor with low ESR at the RF frequency of operation is located at the end of each trace. This arrangement provides local decoupling at the pin. Input and output impedance-matching networks are very sensitive to layout-related parasitics. It is important to keep all matching components as close to the IC as possible to minimize the effects of stray inductance and stray capacitance of PC board traces. 1 R2 // R1 C SHDN 6 BIAS 13 11 C13 L 7 1 9 L7 OPTIONAL NOISE-REDUCTION CIRCUIT C C9 L6 C7 C6 RFOUT Figure 2. Typical Application Circuit 13
// Noise Filtering For improved noise performance, the / / allow for additional noise filtering for further suppression of transmit noise. This is achieved by using C6 and L6 on the, C13 and L7 on the, and C6 and L6 on the. Use the recommended component values for optimal noise power (Table 1). C3 L3 PWR C11 C SHDN RL2 L1 L RH1 RFIN C1 L2 1 2 3 6 7 BIAS 1 13 11 1 9 C2 RL1 RH2 C13 C6 L6 OPTIONAL NOISE- REDUCTION CIRCUIT L C C C7 U1 UPG2TA 2 3 6 R1 PWR C9 C Q1 OPTIONAL RFOUT Figure 3. Typical Application Circuit 1
Pin Configurations (continued) TOP VIEW IN1 SHDN BIAS1H SHDN N.C. OUT1 1 2 3 6 7 TSSOP-EP BIAS N.C. BIAS2H 1 N.C. 13 GND NFP 11 N.C. 1 N.C. 9 OUT1 TRANSISTOR COUNT: Chip Information // Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 1 San Gabriel Drive, Sunnyvale, CA 96-737-76 1 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.