ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 6: September 17, 2012 Restoration Today How do we make sure logic is robust Can assemble into any (feed forward) graph Can tolerate voltage drops and noise.while maintaining digital abstraction 1 2 Outline Two Problems Two problems Cascade failure Restoration Transfer Curves Noise Margins Non-linear 1. Output not go to rail Stops short of Vdd or Gnd 2. Signals may be perturbed by noise V x = V ideal ± V noise 3 4 Output not go to Rail Output not go to Rail CMOS, capacitive load Mostly doesn t have problem CMOS, resistive load? Consider: Vdd=1V Vin=Gnd (both inputs) Ron (PMOS) = 500Ω Rload = 10KΩ What is Vout? R on =500 Ω R on =500 Ω R load =10K Ω How close to rail do I need to get? 5 6 1
Wire Resistance Wire Resistance 1000 µm long wire? 1 cm long wire? Length of die side? Last Wednesday: R wire =10Ω R = ρl A 7 8 Die Sizes Processor Die Size Transistor Count Process Implications What does the circuit really look like for an inverter in the middle of the chip? Core 2 Extreme X6800 143 mm² 291 Mio. 65 nm Core 2 Duo E6700 143 mm² 291 Mio. 65 nm Core 2 Duo E6600 143 mm² 291 Mio. 65 nm Core 2 Duo E6400 111 mm² 167 Mio. 65 nm Core 2 Duo E6300 111 mm² 167 Mio. 65 nm Pentium D 900 280 mm² 376 Mio. 65 nm Athlon 64 FX-62 230 mm² 227 Mio. 90 nm Athlon 64 5000+ 183 mm² 154 Mio. 90 nm http://www.tomshardware.com/reviews/core2-duo-knocks-athlon-64,1282-4.html 9 10 Implications What does the circuit really look like for an inverter in the middle of the chip? Rwire IR-Drop R rest_of_chip Since interconnect is resistive and gates pull current off the supply interconnect The Vdd seen by a gate is lower than the supply Voltage by V drop =I supply x R distribute Rwire Rrest_of_chip Two gates in different locations See different R distribute Therefore, see different V drop 11 12 2
Output not go to Rail CMOS, capacitive load no problem CMOS, resistive load voltage divider Due to IR drop, rails for two communicating gates may not match Two Problems 1. Output not go to rail Is this tolerable? 2. Signals may be perturbed by noise Voltage seen at input to a gate may not lower/higher than input voltage 13 14 Noise Sources? Signals will be degraded What did we see in lab when zoomed in on signal transition? Signal coupling Crosstalk Leakage Ionizing particles IR-drop in signal wiring 1. Output not go to rail Is this tolerable? 2. Signals may be perturbed by noise Voltage seen at input to a gate may not lower/higher than input voltage What happens to degraded signals? 15 16 Preclass Preclass All 1 s logical output? 1.0 inputs, gate: o=1-ab output voltage? 17 18 3
Preclass 0.95 inputs, gate: o=1-ab output voltage? Degradation Cannot have signal degrade across gates Want to be able to cascade arbitrary set of gates 19 20 Gate Creed Gates should leave the signal better than they found it better closer to the rails Restoration Discipline Define legal inputs Gate works if Vin close enough to the rail Restoration Gate produces Vout closer to rail This tolerates some drop between one gate and text (between out and in) Call this our Noise Margin 21 22 Noise Margin Restoration Discipline (getting precise) V oh output high V ol output low Define legal inputs Gate works if Vin close enough to the rail V ih input high V il input low Vin > V ih or Vin < V il Restoration Gate produces Vout closer to rail NM h = V oh -V ih NM l = V il -V ol One mechanism, addresses numerous noise sources. 23 Vout < V ol or Vout > V oh Note: don t just say V in >V ih V out >V oh 24 4
Transfer Function What gate is this? 25 26 Where is there gain? What is gain? ΔVout/Δvin > 1 Decomposing Where is there not gain? Dividing point? V il, V ih = slope -1 points V oh =f(v il ) V ol =f(v ih ) 27 28 V il, V ih = slope -1 points V oh =f(v il ) Closer to rail V ol =f(v ih ) than Vil, Vih Not make much difference on Vout Making Vil lower would reduce NM = Vil-Vol 29 For multi-input functions, should be worst case. i.e. hold non-controlling inputs at Vil, Vih respectively. (relate preclass exercise) 30 5
Ideal Transfer Function Class Ended Here 31 32 Linear Transfer Function? O=Vdd-A Noise Margin? Linear Transfer Function? Consider two in a row (buffer) O1=Vdd-A What is transfer function to buffer output O2? O2=(Vdd-O1) = Vdd-(Vdd-A)=A 33 34 Linear Transfer Function? For buffer: O2=A Consider chain of buffers What happens if A drops a bit between each buffer? A i+1 = A i -Δ Non-linearity Need non-linearity in transfer function Could not have built restoring gates with R, L, C circuit Linear elements Conclude: Linear transfer functions do not provide restoration. 35 36 6
Transistor Non-Linearity 37 V ol V oh All Gates If we hope to assemble design from collection of gates, Voltage levels must be consistent and supported across all gates Must adhere to a V il, V ih, V ol, V oh that is valid across entire gate set =MAX ( g.v ol) V il =MIN ( g.v il) =MIN ( g.v oh) V ih =MAX ( g.v ih) 38 Admin Big Idea Wednesday in Ketterer Lab combo Read through HW2 Transfer library/schematics to eniac Be ready to run electric and spice on linux CETS machines <or> own laptop that you bring with you Friday back here 39 Need robust logic Can assemble into any (feed forward) graph Can tolerate loss and noise.while maintaining digital abstraction Restoration and noise margins Every gate makes signal better Design level of noise tolerance 40 7