Design and Implementation of a WCDMA Uplink Baseband Receiver IC

Transcription

1 Design and Implementation of a WCDMA Uplink Baseband Receiver IC ( 馬席彬 ) Assistant Professor Department of Electrical Engineering National Tsing Hua University Feb. 12, 2004

2 Outline Design Flow Architecture Design Simulation Channel Model Functional Simulation Results Circuit Design Implementation and Measurements Conclusions 2

3 Design Flow 3

4 Architecture Design 4

5 Common Frame Structure in Uplink Physical Channels [2] 5

6 Transmitter Architecture and Configuration General Tx Architecture PRACH Transmission PCPCH Transmission DPDCH & DPCCH Transmission 6

7 Proposed Receiver Architecture 7

8 Receiver Configurations (a) Preamble (b) Message Part & DPCH (c) Disable beamforming 8

9 Criteria for Choosing Major System Parameters Beamforming algorithm Feasibility for IC implementation Matched filter Fast acquisition for channel delay profile Hardware efficiency Area and power consumption Carrier Synchronization Fast acquisition for frequency offset Speed of convergence Timing Synchronization Performance and Area RAKE combining algorithm Performance 9

10 Channel Estimator 10

11 Carrier Synchronization (1/2) 11

12 Carrier Synchronization (2/2) (a) Acquisition, (b) Initial frequency offset and phase shift calculation, (c) Tracking. 12

13 RAKE Combining 13

14 RAKE Combining Concept Q Q Finger 1 Finger 2 Finger 3 Combining Combined Signal Finger 4 I I 14

15 Phased Array Antennas 15

16 Baseband Complex Model for a Linear Equally Spaced Array DOA (θ,φ) [14] 16

17 Beamforming Concept Q Antenna 2 Antenna 3 Combining Q Antenna 1 Combined Signal I I Antenna 4 17

18 Beamformer/Beam Searcher 18

19 Functional Simulation 19

20 Simulation Channel Model Power Delay Profile Scalar Channel Model Vector Channel Model 20

21 Carrier Synchronization (1/2) Preamble Symbols Phasor Difference 21

22 Carrier Synchronization (2/2) Margin 22

23 RAKE Combiner 1 st Path 2 nd Path Combined 23

24 Beamformer/Beam Searcher (1/3) Simulated Beam Pattern 2 users 11 users 24

25 Beamformer/Beam Searcher (2/3) Matched Filter Output Under Beamformer Test w/o Beamformer w/ Beamformer 2 users 11 users 25

26 Beamformer/Beam Searcher (3/3) RAKE Combining Output 26

27 Word Length Determination where SNR = 10 log 10 σ 1 µ = 2 = µ σ 2 2 n I p 0, k n k = 1 1 n n 1 k = 1 2 ( µ ) I p 0, k 2 Input of matched filter 27

28 System Performance 28

29 Circuit Design 29

30 Channel Estimator 30

31 Latch File Structure 31

32 Area Consideration 6T Synthesized Synthesized Latch Custom Layout Custom Layout 22T D-type flip flop 32

33 Power Consumption Consideration Conventional Correlation Method Proposed Correlation Method 33

34 Low Voltage Operation Consideration (1/3) Modified TSPC Ring Decoders Lower power consumption Fast response Operate at low voltage 34

35 Low Voltage Operation Consideration (2/3) Faster response 35

36 Low Voltage Operation Consideration (3/3) Low Voltage Operation Original TSPC split-output circuit Modified TSPC split-output circuit 36

37 Carrier Synchronization 37

38 RAKE Combiner RAKE Combiner Correlator 38

39 Beam Searcher 39

40 Beamformer & Phase De-rotator 40

41 Implementation and Measurement 41

42 Floorplan for the Receiver 42

43 Ratio of Each Building Block Transistor Count Area 43

44 Die Photo Custom Layout Synthesized (ROM) Other : Automatic Placement & Routing 44

45 Chip Features Baseband processor for uplink W-CDMA receiving operating at 3.84 Mchip/s. Operation at MHz sampling rate (four samples per chip) at a supply voltage of 2.15 V. Provision for both spatial diversity (beamforming) and path diversity (RAKE combiner). Low-power latch-file structure for the digital matched filter in the channel estimator. Low-complexity correlator-based beam searcher that supports real-time adaptive beamforming based on fourelement antenna array. Special phase/frequency estimation hardware for fast carrier synchronization. 45

46 Measurement Environment 46

47 Communication Performance 47

48 Power Dissipation 48

49 Conclusions Investigate major specifications for IMT Design and implement a baseband receiver IC conforming to 3GPP W-CDMA uplink transmission. Improve the receiver performance with advanced receiving technologies using low-complexity hardware. RAKE combining Beamformer 49

50 Related Publications Journal papers, Ming-Luen Liou, and Tzi-Dar Chiueh, A 123-mW Digital Beamforming Receiver for Third-Generation W-CDMA Uplink Communications, accepted by IEEE Journal of Solid-State Circuits for publication. Yuan-Hao Huang,, Ming-Luen Liou, and Tzi-Dar Chiueh, An 1.1G MAC/s Sub-Word- Parallel Digital Signal Processor for Wireless Communication Applications, accepted by IEEE Journal of Solid-State Circuits for publication., Steve Heng-Chen Hsu, and Tzi-Dar Chiueh, Design and Implementation of an Uplink Baseband Receiver for Wideband CDMA Communications, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, No. 12, pp , December Conference papers, and Tzi-Dar Chiueh, Design and Implementation of an Uplink Baseband Receiver IC for Wideband CDMA Communication Systems with Beamforming Capability, 2002 VLSI Design/CAD Symposium, Taitung, August 12-15, 2002., Steve Hengchen Hsu, Tzi-Dar Chiueh, Real-Time Baseband Signal Processing Module for Wideband CDMA Transceiver, National Symposium on Telecommunications, December 2000., Steve Hengchen Hsu, and Tzi-Dar Chiueh, An Uplink Baseband Receiver architecture and FPGA Implementation for W-CDMA Systems, in the IEEE Proc. of the 6th Asia-Pacific Conference on Communications, Seoul, Korea, November 2000, pp T. D. Chiueh, H. P. Ma, and H. C. Hsu, An Uplink Transceiver Architecture for Wideband CDMA Systems, in Proc IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 99), Phuket, Thailand, December 1999, pp 經濟部第三代通訊系統核心技術與 WB-WCDMA/WLL 系統發展研討會, 民國八十八年四月 50