Another Compensator Design Example

Transcription

1 Another Compensator Design Example + V g i L (t) + L + _ f s = 1 MHz Dead-time control PWM 1/V M duty-cycle command Compensator G c c( (s) C error Point-of-Load Synchronous Buck Regulator + I out R _ + V V ref v o _ Power stage parameters Switching frequency: f s = 1MHz V ref = 1.8 V I out = to 5 A V g = 5 V L = 1 H R L = 3 m C = 2 F R esr =.8 m V M = 1 V H = 1

2 Buck Averaged Small-Signal Model V g d R L L i L R esr + G vd ( s) vˆ o dˆ 1 s v + R g D i + v L D v g esr Gvd ( s) Vg 2 I o d C 1 s s 1 Q o o Pair of poles: Low-frequency gain (including PWM gain): 1 f o 11kHz 2 CL 1 G vd 5 14dB o VM L / C R Qloss db Q load 5 Resr RL L / C ESR zero: QlossQload Q Q db 1 loss Qload Q fesr 1MHz loss Qload 2CR esr

3 Uncompensated loop gain T u i L (t) I out + L + + V g C R v o _ f s = 1 MHz Dead-time control PWM duty-cycle command G vd (s) Compensator error + H sense = 1 (in this example) 1/V M G c (s) = 1 + V ref T u (s) = H sense (1/V M )G vd (s) Plot magnitude and phase responses of T u (s) to plan how to design G c (s)

4 Magnitude and phase Bode plots of T u 8dB 6dB T u (s) = H sense (1/V M )G vd (s) 4dB 2dB T uo G vdo ( 1/ V ) H 5 14dB M sense Q dB db -2dB f o 11kHz 1 1/ 2Q f o 4dB/dec T uo f f o c 2 o target tff c 2dB/dec f esr 1MHz -9 o 1 1/ 2Q f o 1/1 f esr 1 Hz 1 Hz 1 KHz 1 KHz 1 KHz 1 MHz -18 o

5 Magnitude and phase Bode plots of T u [db] magnitude Uncompensated loop gain, Tu = Gvd*Hsense*(1/VM) Exact magnitude and phase responses (MATLAB) Target cross-over frequency f c = f s /1 = 1 khz phase [deg] frequency [Hz] No phase margin: a lead (PD) compensator is required

6 Lead (PD) compensator design 1. Choose: f c 1 khz m 53 o 2. Compute: 33 khz 3 khz 3. Find G co to position the crossover frequency: T uo f f o c 2 G co f f p z 1 G co 1 T uo f f c o 2 f f z p db Magnitude of T u at f c Magnitude of G c at f c

7 Lead (PD) compensator summary G c ( s) G co s 1 z 1 s s 1 1 p1 p2 Lead compensator HF pole G co db f z 33 khz f p1 3 khz f 1 khz (=1/1 of f s ) c High-frequency gain of the lead compensator: G co f p1 /f z = 49 (34 db) Added high-frequency pole: f p2 1MHz (= f esr = f s in this example) Practical implementation would require an op-amp with a gain bandwidth product of at least 49*f p2 = 49 MHz

8 Loop gain with lead (PD) compensator 8dB 6dB 4dB 2dB db T uo G co dB G ( s) G c f c co s 1 z 1 s s 1 1 p 1 p 1 khz 2-2dB f z 1kHz f z 33kHz f p 3kHz o -9 o 1 Hz 1 Hz 1 KHz 1 KHz 1 KHz 1 MHz m 53 o -18 o

9 Add lag (PI) compensator Integrator at low frequencies Choose 1f L < f c so that phase margin stays approximately the same: f L = 8 khz Keep the same cross-over frequency: G c G co G cm db

10 Adding PI Compensator 8dB 6dB 4dB 2dB db f L 8kHz f c 1 khz -2dB 1 f L o 1/1 f L PI compensator phase -9 o 1 Hz 1 Hz 1 KHz 1 KHz 1 KHz 1 MHz m 53 o -18

11 Complete analog PID compensator: summary G cm db f L 8 khz f z f p1 33 khz 3 khz f p2 1MHz Crossover frequency: Phase margin: f c 1 khz (=1/1 of f s ) 53o m

12 Magnitude and phase Bode plots of T 8dB 6dB 4dB 2dB db f c 1 khz -2dB Phase of uncompensated T u o Phase of compensated T -9 o 1 Hz 1 Hz 1 KHz 1 KHz 1 KHz 1 MHz m 53 o -18 o

13 Verification: exact loop gain magnitude and phase responses (MATLAB) 5 Loop Gain [db] f c 15 khz magnitude -5 phase [ deg] o m frequency [Hz]

14 Analog PID compensator implementation C 3 C 4 R4 output voltage sense R 1 V ref C 2 _ + R 2 v c control voltage Design equations (approximate) G c ( s) G cm s L 1 1 s z s s 1 1 p1 p2 f z G cm 1 R R f L 2R C f 2 R 1 R 4 p 1 C 4 2R4C C f p 2 2R2 3

15 Verification of closed-loop responses Closed-loop reference-to-output response Closed-loop output impedance and step-load transient response

16 Construction of closed-loop T/(1+T) response 8dB 6dB 4dB Closed-loop reference-to-output response v/v ref = T/(1+T) 2dB db v/v ref -2dB -4dB Closed-loop BW f c -6dB -8dB 1 Hz 1 Hz 1 KHz 1 KHz 1 KHz 1 MHz

17 Closed-loop reference-to-output response 5 Reference-to-output response v/v ref T/(1+T) [db]

18 Small-signal step-reference response v o (t) x mv step (1.79 V to 1.8 V) in v ref i L (t) x 1-4 d(t) s/div x 1-4

19 Small-signal step-reference response v o (t) x mv step (1.79 V to 1.8 V) in v ref 1.85 i L (t) d(t) s/div s/div Note: duty-cycle command x 1-4 does not saturate, response correlates very well with theory based on linear small-signal models x 1-4 x 1-4

20 Output impedance Synchronous buck open-loop output impedance R L L R esr Z out ( s) 1 Resr sc R L sl C Z out L = 1 H R L = 3 m C = 2 F R esr =.8 m

21 Open-loop output impedance: algebra on the graph 8dB 6dB R L L R esr Z out 4dB 2dB 1/C L C db -2dB R L 3 m 3.5 db -4dB f o 11kHz -6dB -8dB R esr.8 m 62 db -1dB 1 Hz 1 Hz 1 KHz 1 KHz 1 KHz 1 MHz

22 Construction of 1/(1+T) 8dB 6dB 4dB 2dB db -2dB 1 Hz 1 Hz 1 KHz 1 KHz 1 KHz 1 MHz

23 Construction of closed-loop output impedance 8dB 6dB 4dB Z out, CL Zout 1 T 2dB db -2dB -4dB -6dB -8dB -1dB 1 Hz 1 Hz 1 KHz 1 KHz 1 KHz 1 MHz

24 Closed-loop output impedance Z out,cl 8dB 6dB 4dB Z out, CL Zout 1 T 2dB db -2dB -4dB 8 m, -42 db -6dB -8dB -1dB Z out,cl 1 Hz 1 Hz 1 KHz 1 KHz 1 KHz 1 MHz

25 Verification: closed-loop output impedance 5 Output impedance tput impedance [dbohm] Ou -5 open-loop Zout closed-loop l Z out,cl

26 Step-load transient responses v o (t) x A step-load transient i L (t) x 1-4 d(t) s/div x 1-4

27 Step-load transient responses v o (t) x A step-load transient i L (t) x 1-4 d(t) s/div x s/div v 15 mv 1 s settling time x 1-4