XR :1 Sensor Interface AFE. General Description. Typical Application

Transcription

1 6: Sensor Interface AFE General Description The XR9 is a unique sensor interface integrated circuit with an on-board 6: multiplexer, offset correction DAC, instrumentation amplifier and voltage reference. The XR9 is designed to integrate multiple bridge sensors with a microcontroller (MCU) or field-programmable gate array (FPGA). The integrated offset correction DAC provides digital calibration of the variable and in many cases substantial offset voltage generated by the bridge sensors. The DAC is controlled by an IC compatible wire serial interface. The serial interface also provides the user with easy controls to the XR9 s many functions such as input and gain selection. An integrated LDO provides a regulated voltage to power the input bridge sensors and is selectable, between 3V and.65v, via the serial interface for lower voltage compatibility. The LDO current can be sensed and a proportional voltage present at the output of the IC for monitoring the LDO current. The XR9 offers 8 fixed gain settings (from V/V to 76V/V), each with an error of only ±.5%, that are selectable via the IC interface. It also offers less than mv maximum input offset voltage, pa maximum input bias current, and pa maximum input offset current. The XR9 is designed to operate from.7v to 5V supplies and is specified over the industrial temperature range of -4 C to +85 C. It is offered in a space saving 6mm x 6mm QFN-4 package. It consumes less than 556μA maximum supply current and offers a sleep mode for added power savings. The low power, low input bias current and integrated features make the XR9 well suited for both industrial and consumer applications using bridge sensors. FEATURES Integrated features for interfacing multiple bridge sensors with an MCU or FPGA: 6: differential mux with I C interface Instrumentation amplifier LDO Offset correction DAC with I C interface (±56mV offset correction range - RTI) Eight selectable voltage gains from V/V to 76V/V with only ±.5% gain error mv maximum input offset voltage pa maximum input bias current 556μA maximum supply current.7v to 5V analog supply voltage range.8v to 5V digital supply voltage range -4 C to +85 C temperature range 6mm x 6mm QFN-4 package APPLICATIONS Bridge sensor interface Pressure & temperature sensors Strain gauge amplifier Industrial process controls Weigh scales Ordering Information - back page Typical Application 6.8μF + V CC 6.8μF + V DD.μF.μF.5 BRDG VCC VDD BRIDGE 6 IN6+ LDO.μF BRIDGE IN- IN6- IN+ 6: MUX -BIT DAC INA / PGA ±56mV OFFSET TRIM PGA IC CONTROL XR9 OUT SDA SCL V DD k nf V DD 4.7k 4.7k ADC µc RTI Noise (µv) Time (sec) AGND DGND Figure. Typical Application Figure..Hz to Hz RTI Voltage Noise /

2 Absolute Maximum Ratings Stresses beyond the limits listed below may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Analog Supply Voltage (V CC)... V to 5.5V Digital Supply Voltage (V DD )... V to 5.5V Digital Input/Output (V DDIO )... V to 5.5V V IN... to V CC Differential Input Voltage (current limit of ma)... V CC ESD Rating (HBM - Human Body Model)...4kV Operating Conditions Analog Supply Voltage Range....7V to 5.5V Digital Supply Voltage Range...7V to 5.5V Operating Temperature Range...-4 C to 85 C Junction Temperature...5 C Storage Temperature Range C to 5 C Lead Temperature (Soldering, s)...6 C Package thermal resistance θ JA... 3 C/W NOTE:. JEDEC standard, multi-layer test boards, still air. /

3 Electrical Characteristics T A = 5 C, V CC = 3.3V, V DD =.8V, R L = kω to V; G = 76; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units DC Performance V IO Input offset voltage Input referred - ±. mv d VIO Input offset voltage average drift 3 μv/ C I B Input bias current - 5 pa I OS Input offset current - pa PSRR Power supply rejection ratio V CC =.7V to 5V 6 9 db Gain Gain =. V/V Gain =. V/V Gain = 4 4. V/V Gain = 8 8. V/V Nominal; refer to Gain Register Table (pg. ) Gain = 5 5. V/V Gain = V/V Gain = V/V Gain = V/V G E Gain error % Gain error vs temperature ± ppm/ C I SVCC V CC supply current No load to output; no load to LDO μa I SVCCD Disable V CC supply current No load to output; no load to LDO μa I SVDD V DD supply current No load to output; no load to LDO; I C running 6 μa I STOTAL Total supply current No load to output; no load to LDO μa I SDTOTAL Input Characteristics Total disable supply current No load to output; no load to LDO; LDO DIS 45 μa No load to output; no load to LDO; LDO EN 7 85 μa Input impedance 3. Ω pf CMIR Common mode input range.5.3 to V CMRR Common mode rejection ratio Input referred. V CM =.5 to.v db Output Characteristics V OUT Output voltage swing R L = kω to V..4 to V V OO Output offset Offset DAC ; G =.4.6 V Offset DAC LDO Offset DAC range RTI (referred to input) ±56 mv Offset monotonicity 8 Bits Output voltage k load, LDO bit LOW -6% 3 +6% V k load, LDO bit HIGH -6%.65 +6% V Dropout voltage V CC =.8V, LDO =.65V, I LOAD = ma 5 mv Output current 5 ma Power supply rejection ratio Output current sense transimpedance slope Output referred, V CC = 3V to 5V, LDO =.65V db Output referred, V CC = 3.3V to5v, LDO = 3V db Output voltage relative to V / LDO current, G =.8.. V/mA Output current sense range clip G = 8.8 ma 3/

4 Electrical Characteristics (Continued) T A = 5 C, V CC = 3.3V, V DD =.8V, R L = kω to V; G = 76; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Dynamic Performance BW -3dB bandwidth G = khz G = 3 khz SR Slew rate V OUT = V pp ; Gain = V/μs e ni Input voltage noise - RTI f = Hz 75 nv/ Hz f = Hz 46 nv/ Hz f = khz 35 nv/ Hz i n Input current noise f = Hz.6 fa/ Hz e npp Peak-to-peak noise f =. to Hz μv pp XTALK Crosstalk Channel-to-channel, f = khz 9 db T S Set-up time, % settling Analog ready after serial register finished write 3.5 μs T WAKE Wake up time, % settling Wake from ACK of SLEEP_OUT command 9.6 μs Digital Characteristics (CMOS) Symbol Parameter Conditions Min Typ Max Units V IH Logic Input HIGH.7 x V DD V DD V V IL Logic Input LOW.3 x V DD V I IH Input Leakage HIGH V I = V S μa I IL Input Leakage LOW V I = - μa CLK F Clock Rate.4 MHz I C Bus Timing T A = -4 to +85 C, V DD =.8-5V; unless otherwise noted. Symbol Parameter Standard Mode I C-BUS Fast Mode I C-BUS Min Max Min Max f SCL Operating frequency 4 khz T BUF Bus free time between STOP and START μs T HD;STA START condition hold time 4..6 μs T SU;STA START condition setup time μs T HD;DAT Data hold time μs T VD;ACK Data valid acknowledge.6.6 μs T VD;DAT SCL LOW to data out valid.6.6 ns T SU;DAT Data setup time 5 5 ns T LOW Clock LOW period μs T HIGH Clock HIGH period 4..6 μs T F Clock/data fall time 3 3 ns T R Clock/data rise time 3 ns T SP Pulse width of spikes tolerance.5.5 μs Units 4/

5 Electrical Characteristics (Continued) Figure 3: I C Bus Timing Diagram 5/

6 Register Information Table. Register List Reg No. Hex Dec Name Function R/ W/ C Byte of Parameter Parameter x NOP No operation C N/A Reset Default Code Power-up Condition Remark Does not execute a function. NOP is used to test successful I C communication x SW_RESET Software reset C N/A Resets all registers to default values Read ID x DEVICE_ID Read Device ID R x3 3 VERSION_ID Sleep in/out x4 4 SLEEP_OUT _ REG Read HW & SW version numbers Normal operating mode, system active R [5:]: report 9 in BCD [5:]: reserved [:8]: Hardware version # [7:]: Software version # x9 C N/A Active Instructs the XR9 to report its device ID 9 in binary form ( ) N/A Initial H/W version number is ; Initial S/W version number is. Puts the XR9 into active mode. (wake up) x5 5 SLEEP_IN_ REG Sleep Mode C N/A Active Puts the analog portion of the XR9 into sleep mode. During sleep mode, the only I C command that can be received/processed is the SLEEP_OUT command (x4). All other register addresses will be ignored. Basic Config x6 6 Gain Gain select R/W [:]: Gain select x x7 7 LDO LDO Settings R/W x8 8 LDO Current Sense Select []:LDO 3V,.65V []:LDO disable x Gain = LDO = 3V LDO Current Sense C N/A Off Eight gain settings are selectable (from V/V to 76V/V), refer to the Gain Register Table for more information. Bit controls the LDO voltage (: 3V; :.65V). Bit (Sleep Mode only). Bit controls whether the LDO shuts down or stays on during Sleep Mode. (: Enable; : Disable). When the XR9 is active, the LDO is always on. When on, the LDO current is sensed and a proportional voltage is present at the output of the XR9. Current Sense Mode remains active until an input select command is received by the XR9. 6/

7 Reg No. Hex Dec Name Function R/ W/ C Byte of Parameter Parameter Default Code Power-up Condition Remark Channel Switch (Input Mux Select) x 6 Input_ Select Channel C Select +IN, -IN; Channel x 7 x 8 x3 9 x4 x5 x6 x7 3 x8 4 x9 5 xa 6 xb 7 xc 8 xd 9 xe 3 xf 3 Input_ Input_3 Input_4 Input_5 Input_6 Input_7 Input_8 Input_9 Input_ Input_ Input_ Input_3 Input_4 Input_5 Input_6 Select Channel C Select +IN, -IN; Channel Select Channel 3 C Select +IN3, -IN3; Channel 3 Select Channel 4 C Select +IN4, -IN4; Channel 4 Select Channel 5 C Select +IN5, -IN5; Channel 5 Select Channel 6 C Select +IN6, -IN6; Channel 6 Select Channel 7 C Select +IN7, -IN7; Channel 7 Select Channel 8 C Select +IN8, -IN8; Channel 8 Channel N/A is selected Select Channel 9 C Select +IN9, -IN9; Channel 9 Select Channel C Select +IN, -IN; Channel Select Channel C Select +IN, -IN; Channel Select Channel C Select +IN, -IN; Channel Select Channel 3 C Select +IN3, -IN3; Channel 3 Select Channel 4 C Select +IN4, -IN4; Channel 4 Select Channel 5 C Select +IN5, -IN5; Channel 5 Select Channel 6 C Select +IN6, -IN6; Channel 6 7/

8 Reg No. Hex Dec Name Function R/ W/ C Byte of Parameter Parameter Default Code Power-up Condition Remark Offset DAC Config x 3 DAC Channel x 33 DAC Channel x 34 DAC3 Channel 3 x3 35 DAC4 Channel 4 x4 36 DAC5 Channel 5 x5 37 DAC6 Channel 6 x6 38 DAC7 Channel 7 x7 39 DAC8 x8 4 DAC9 Channel 8 Channel 9 []: DAC Sign [9:]: DAC Range x mv offset Bit controls the sign of the DAC offset voltage. Bits 9 thru control the value of the DAC offset voltage. []: DAC Sign = positive; = negative x9 4 DAC Channel xa 4 DAC Channel xb 43 DAC Channel xc 44 DAC3 Channel 3 xd 45 DAC4 Channel 4 xe 46 DAC5 Channel 5 xf 47 DAC6 Channel 6 NOTE: Register Numbers not listed above have no function. 8/

9 Table. DAC Registers Hex D D9 D8 D7 D6 D5 D4 D3 D D D Offset % of FS Input Voltage RTI x3ff 5 +56mV x x7ff -5-56mV x4 DAC Sign -bit DAC Range Table 3: Gain Registers Hex D D D Gain x x x 4 x3 8 x4 5 x5 3 x6 6 x7 76 9/

10 Pin Configuration IN+ 3 IN5- IN- 9 IN5+ IN+ 3 8 IN4- IN- IN XR9 QFN-4 7 IN4+ 6 IN3- IN3-6 5 IN3+ IN IN- IN4-8 3 IN+ IN5+ 9 IN- IN5- IN+ 3 IN VDD 39 SDA 38 SCL 37 DGND 36 VCC IN7+ 35 OUT 34 AGND IN8+ 33 BRDG 3 IN6- IN9+ 3 IN6+ NOTE: IN+ MaxLinear recommends grounding the exposed pad. IN6- IN7- IN8- IN9- IN- Pin Functions Pin No. Pin Name Description IN+ Positive Input IN- Negative Input 3 IN+ Positive Input 4 IN- Negative Input 5 IN3+ Positive Input 3 6 IN3- Negative Input 3 7 IN4+ Positive Input 4 8 IN4- Negative Input 4 9 IN5+ Positive Input 5 IN5- Negative Input 5 IN6+ Positive Input 6 IN6- Negative Input 6 3 IN7+ Positive Input 7 4 IN7- Negative Input 7 5 IN8+ Positive Input 8 6 IN8- Negative Input 8 7 IN9+ Positive Input 9 8 IN9- Negative Input 9 9 IN+ Positive Input IN- Negative Input Pin No. Pin Name Description IN+ Positive Input IN- Negative Input 3 IN+ Positive Input 4 IN- Negative Input 5 IN3+ Positive Input 3 6 IN3- Negative Input 3 7 IN4+ Positive Input 4 8 IN4- Negative Input 4 9 IN5+ Positive Input 5 3 IN5- Negative Input 5 3 IN6+ Positive Input 6 3 IN6- Negative Input 6 33 BRDG BRDG Power Connection ( LDO output ) 34 AGND Analog Ground 35 OUT Output 36 VCC Analog Supply 37 DGND Digital Ground 38 SCL Serial Clock Input 39 SDA Serial Data Input/Output 4 VDD Digital Supply /

11 Typical Performance Characteristics T A = 5 C, V CC = 3.3V, V DD =.8V, R L = kω to V; G = 76; unless otherwise noted. G =, Vout =.5Vpp 3 G =, Vout =.5Vpp.75.5 Output Voltage (V) Output Voltage (V) Time (µs) Time (µs) Figure 4. Small Signal Pulse Response at G = Figure 5. Large Signal Pulse Response at G = G = 3, Vout =.5Vpp 3 G = 3, Vout =.5Vpp.75.5 Output Voltage (V) Output Voltage (V) Time (µs) Time (µs) Figure 6. Small Signal Pulse Response at G = 3 Figure 7. Large Signal Pulse Response at G = 3 3 G = 3 G = 3 Normalized Gain (db) -3-6 V OUT =.5V pp V OUT = V pp V OUT =.5V pp Normalized Gain (db) -3-6 V OUT =.5V pp V OUT = V pp V OUT =.5V pp Frequency (khz) Figure 8. Frequency Response at G = -. Frequency (khz) Figure 9. Frequency Response at G = 3 /

12 Typical Performance Characteristics T A = 5 C, V CC = 3.3V, V DD =.8V, R L = kω to V; G = 76; unless otherwise noted G = Current Sense Mode Active V CC = 5V Output Voltage (V).5 VLDO (V).5 V CC = 3.3V ILDO (ma) Figure. LDO Current vs. Output Voltage ILDO (ma) Figure. LDO Output Current G = 3 G = Output Voltage (V) 3 Output Voltage (V) G = 76 G = Output Current (ma) Input Common Mode Voltage (V) Figure. Output Offset Voltage vs. Output Current Figure 3. Output Offset vs. Input Common Mode Voltage.5 9 G = 76 Input Voltage Noise (nv/ Hz) Frequency (KHz) Figure 4. Input Voltage Noise vs. Frequency RTI Noise (µv) Time (sec) Figure 5..Hz to Hz RTI Voltage Noise /

13 Typical Performance Characteristics T A = 5 C, V CC = 3.3V, V DD =.8V, R L = kω to V; G = 76; unless otherwise noted. Output Voltage (V).5 G = Stop Time = % Settling DUT OUTPUT SDA.5 Start Time = 5% Acknowledge Time (µs) Output Voltage (V) SDA Stop Time = % Settling.5 DUT OUTPUT Start Time = 5% Acknowledge Time (µs) Figure 6. Sleep to Wake Time (DUT Output) Figure 7. Set-up Time - from G = to G = 3 (DUT Output) Output Voltage (V) SDA LDO Output Stop Time = % Settling Output Voltage (V).5.5 LDO OUTPUT Stop Time = % Settling SDA Start Time = 5% Acknowledge Time (µs) Start Time = 5% Acknowledge Time (µs) Figure 8. LDO Enable to Disable Time Figure 9. LDO Disable to Enable Time 3/

14 Functional Block Diagram VCC LDO Output V Reference LDO Enable LDO Select ( 3V,.65V ) Input +/- AGnd Input +/- Input 3 +/- PGA Input 4 +/- 6: Differential Mux : Differential Mux Output Input 4 +/- Input 5 +/- Input 6 +/- VDD SDA SCL Input [:5] Current Sense Mode DAC [:9], Sign Offset - Offset + bit Offset DAC IC Serial Digital Interface Gain Select LDO Enable LDO Select Power Down Analog DGnd Figure : Functional Block Diagram Application Information The XR9 sensor interface includes a 6: differential multiplexor (mux), a programmable gain instrumentation amplifier, a -bit offset correction DAC and an LDO. An I C interface controls the many functions and features of the XR9. The XR9 is designed to integrate multiple bridge sensors with an ADC/MCU or FPGA. Each bridge sensor connected to the XR9 has its own inherent offset that if not calibrated out can decrease sensitivity and overall performance of the sensor system. The on-board DAC introduces an offset into the instrumentation amplifier to calibrate the offset voltage generated by the sensors. An independent offset can be set for each of the 6 channels. Only the offset voltage of the active channel is applied to the PGA. The programmable gain instrumentation amplifier offers 8 selectable gains from V/V to 76V/V to amplify the signal such that it falls within the input range of the ADC. An integrated LDO provides a regulated voltage to power the input bridge sensors and is selectable, between 3V and.65v. The LDO can be set to turn off when the XR9 is in Sleep Mode to save power. The XR9 also provides the ability to monitor the LDO current. When the XR9 is in Current Sense Mode, an internal : mux allows a voltage proportional to the LDO current to be present at the output. Once all channels have been calibrated, the LDO current can be used to indirectly monitor any voltage or resistive changes seen by the inputs. The XR9 also includes an internal V reference that is used by the internal LDO circuitry and used to set the reference voltage for the programmable gain instrumentation amplifier. During sleep mode, the analog components of the XR9 are powered down for added power savings. The XR9 offers many functions, each controlled by the I C compatible serial interface: Input Selection Gain Selection Offset Correction LDO Enable / Select Current Sense Mode Sleep Mode (Analog Power Down) 4/

15 Application Information (Continued) Power Up After initial system power up, the I C master must provide one SCL clock pulse prior to the first I C access (first start condition). The first access to the XR9 must be a RESET command. SDA SCL I C Bus Interface Figure : I C Power Up The I C-bus interface consists of two lines: serial data (SDA) and serial clock (SCL). The XR9 works as a slave and supports both standard mode transfer rates ( kbps) and fast mode transfer rates (4 kbps) as defined in the I C- Bus specification. The I C-bus interface follows all standard I C protocols. Some information is provided below, for additional information, refer to the I C-bus specifications. Data Cycle After the master detects this acknowledge, the next byte transmitted by the master is the sub-address. This 8-bit sub-address contains the address of the register to access. The XR9 Register List is shown in Table. Depending on the register accessed, there will be up to two additional data bytes transmitted by the master. Refer to the Byte of Parameter column in the Register Table. The XR9 will respond to each write with an acknowledge. Stop Condition To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high, as shown in Figure. Figures 3 and 4 illustrate a write and a read cycle. For complete details, see the I C-bus specifications. S NOTES: SLAVE ADDRESS W A REGISTER ADDRESS White Block = host to XR9, Red Block = XR9 to host A ndata A P Figure 3: Master Writes to Slave (XR9) S SLAVE ADDRESS W A REGISTER ADDRESS A S SLAVE LAST R A ndata A ADDRESS DATA NA P Figure : I C Start and Stop Conditions The basic I C access cycle for the XR9 consists of: A start condition A slave address cycle Zero, one, or two data cycles - depending on the XR9 register accessed A stop condition Start Condition The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure. Slave Address Cycle After the start condition, the first byte sent by the master is the 7-bit address and the read/write direction bit R/W on the SDA line. If the address matches the XR9 s internal fixed address, the XR9 will respond with an acknowledge by pulling the SDA line low for one clock cycle while SCL is high. NOTES: White Block = host to XR9, Red Block = XR9 to host Figure 4: Master Reads from Slave (XR9) I C Bus Addressing The XR9 uses a 7-bit address space. For the standard XR9, the default address is x67 ( ). Table 4: XR9 I C Address Map I C Address x67 Orderable Part Number XR9IL4TR-F A read or write transaction is determined by bit- of the slave address, (shown as an x in Table 4 above). If bit- is, then it is a write transaction. If bit- is, then it is a read transaction. An IC sub-address is sent by the IC master following the slave address. The sub-address contains the XR9 register address being accessed. Table illustrates the available XR9 register addresses. After the last read or write transaction, the IC-bus master will set the SCL signal back to its idle state (HIGH). 5/

16 Application Information (Continued) Inputs and Input Selection The XR9 includes 6 differential inputs and a 6: differential mux that is controlled by an I C compatible wire serial interface. The XR9 is designed to accept 6 differential inputs. If fewer than 6 differential inputs are required, tie the unused inputs to GND. If single ended inputs are required, tie the unused inputs to V. The input common mode range of the XR9 is typically.6v to.4v when running from a 3.3V supply. The XR9 offers a very wide gain range. In most cases, the output voltage swing will be the limiting factor. When the XR9 is powered-up, the default input selected is Channel. Inputs are selected via I C using one of 6 register addresses x thru xf. Refer to the Register List in Table. Example: The example below illustrates how to select Channel 5. Gain Selection The XR9 offers 8 selectable fixed gains ranging from V/V to 76V/V. When the XR9 is powered-up, the default gain is V/V. The gain is selected via I C using the register address x6 followed by another byte of data to select the gain. Refer to the Register List in Table and the Gain Register list in Table 3. Example: The example below illustrates how to select a gain of 5V/V. To start communication with the XR9, repeat steps -3 as shown in the Inputs and Input Selection section on page 6. Step Master sends address of register to access Gain Select register address = x6 Step Step 5 9 Master sends start condition S XR9 sends acknowledge A Step Master sends XR9 address with write bit 7-bit XR9 Address = x67 W Since the Gain Select register was accessed, the XR9 is expecting another byte of data from the master to complete the command. Refer to the Byte of Parameter column in the Register List (Table ). D thru D are used to select the gain. Refer to the Gain Register list in Table 3, 5V/V is D =, D =, and D =. This translates to a hex code of x4, since a full byte of data (8-bits) will be sent. Step 3 9 XR9 sends acknowledge Step Master sends address of register to access A Input 5 register address = x4 Step Master sends gain register data to select G=5 Step 7 9 XR9 sends acknowledge A Gain of 5V/V = x4 Step 5 9 XR9 sends acknowledge A Step 8 Master sends stop condition P Step 6 Master sends stop condition P White Block = host to XR9, Red Block = XR9 to host Grey Block = Notes White Block = host to XR9, Red Block = XR9 to host Grey Block = Notes 6/

17 Application Information (Continued) Offset Correction The XR9 has a -bit offset correction DAC that can be used to provide digital calibration on each of the 6 inputs. Only the offset voltage of the active channel is applied to the PGA. The DAC offset of each channel is controlled by the I C compatible interface. At any time, the master can read or write to any of the DAC offset registers. The DAC offset for each channel is set via I C using the register addresses x thru xf followed by another two bytes of data to set the polarity and value of the offset voltage. Refer to the Register List in Table. A ±56mV offset correction range is available. The full range of the DAC offset is only available at a gain of. At higher gains, the output voltage range of the XR9 will be exceeded if the full range of the DAC offset is used. The internal -bit DAC allows,4 different offset voltage settings between mv and 56mV. The polarity of the offset correction is set with an additional bit. The unit offset is determined by the following: Unit offset = Total Offset = 56mV = DAC outputlevels 4 547nV From Table 3: x (hex) or (binary) applies a mv offset x3ff (hex) or (binary) applies a +56mV offset x7ff (hex) or (binary) applies a -56mV offset Each DAC output level provides an additional 547µV of offset. To determine what DAC output level corresponds to a specific desired offset, use the following equation: Step 5 9 XR9 sends acknowledge Since a DAC Offset register was accessed, the XR9 is expecting another two bytes of data from the master to complete the command. Refer to the Byte of Parameter column in the Register List (Table ). D thru D9 are used to set the offset voltage and D is used to set the sign of the offset voltage, = positive and = negative. Refer to the DAC Offset register list in Table. To determine what DAC output level corresponds to 75mV, use the following equation: DAC Output Level = Desired Offset = 75mV = 37 Unit Offset 547 nv A decimal value of 37 corresponds to 75mV. Therefore: x89 (hex) or (binary) applies a +75mV offset x489 (hex) or (binary) applies a -75mV offset Step Master sends st byte of DAC offset register data to select an offset of +75mV Step 7 9 XR9 sends acknowledge A Sign A MSBs of -bit DAC output level that corresponds to 37 (x89) See example below for additional information. Example: The example below illustrates how to set the DAC offset for channel 4 to a value of 75mV. To start communication with the XR9, repeat steps -3 as shown in the Inputs and Input Selection section on page 6. Step Master sends address of register to access DAC4 register address = x5 Step Master sends nd byte of DAC offset register data to select an offset of +75mV Step 9 9 XR9 sends acknowledge Step Master sends stop condition White Block = host to XR9, Red Block = XR9 to host Grey Block = Notes 8 LSBs of -bit DAC output level that corresponds to 37 (x89) A P 7/

18 Application Information (Continued) LDO Enable / Select (Power to External Bridge Sensors) The XR9 includes an on-board LDO that provides a regulated voltage that can be used to power external input bridge sensors. Two voltage options are available, 3V and.65v. The LDO voltage is selected via the I C compatible two-wire serial interface. When the XR9 is powered-up, the default LDO voltage is 3V. When the XR9 is active (not in sleep mode), the LDO is always on. If the LDO voltage is not used, the LDO output can be left floating. The LDO can either stay on or shut down while the XR9 is in Sleep Mode. Set LDO to shut down while XR9 is in Sleep Mode to save power Set LDO to stay on while XR9 is in Sleep Mode to improve wake-up time The LDO voltage and disable setting are selected via I C using the register address x7 followed by another byte of data to select the voltage and disable setting. Refer to the Register List in Table and the example below for more information. Example: The example below illustrates how to select an LDO voltage of.65v and keep the LDO enabled during Sleep Mode. To start communication with the XR9, repeat steps -3 as shown in the Inputs and Input Selection section on page. Step Master sends address of register to access Step 5 9 XR9 sends acknowledge LDO Settings register address = x7 Since the LDO Settings register was accessed, the XR9 is expecting another byte of data from the master to complete the command. Refer to the Byte of Parameter column in the Register List (Table ). D and D are used to select the LDO voltage and enable/disable the LDO during Sleep Mode. Bit (D) controls the LDO voltage (: 3V; :.65V). Bit (D) is only applicable in Sleep Mode. Bit controls whether the LDO shuts down or stays on during sleep mode (: Enable; : Disable). When the XR9 is active, the LDO is always on. A Step Master sends code to select LDO voltage of.65v and Enable LDO during Sleep Mode Step 7 9 XR9 sends acknowledge Step 8 Master sends stop condition White Block = host to XR9, Red Block = XR9 to host Grey Block = Notes A = Enable Current Sense Mode (Monitoring the LDO Current) P =.65V Current Sense Mode is activated via I C using the register address x8. When activated, the LDO current is sensed and a proportional voltage is present at the output of the XR9 (ILDO = VOUT/RL). Current Sense Mode stays active until the XR9 receives any input select command (x thru xf). Current sense mode can be used to monitor the change over time of the bridge impedance. Sleep Mode (Analog Power Down) Sleep Mode is activated via I C using the register address x5. When activated, the XR9 will enter Sleep Mode. During Sleep Mode, the analog portion of the XR9 is disabled. All register settings are retained during Sleep Mode. During Sleep Mode, the nominal supply current will drop below 7µA (with LDO on) and below 45µA (with LDO off). During Sleep Mode, the master can read the value in any register that saves a value during sleep mode. The only I C commands that can be received or processed is the SLEEP_OUT (wake up) command (x4) or the LDO on/off and voltage command (x7). All other register addresses will be ignored. Register address x4 is used to return to normal operation (exit Sleep Mode). By default, the XR9 is active. 8/

19 Application Information (Continued) Typical Application 6: Bridge Sensor Interface The XR9 was designed to interface multiple bridge sensors with a microcontroller or FPGA as illustrated in Figure 5. The bridge output signal is differential (Vo+ and Vo-). Ideally, the unloaded bridge output is zero (Vo+ and Vo- are identical). However, in-exact resistive values result in a difference between Vo+ and Vo-. This bridge offset voltage can be substantial and vary between sensors. The XR9 provides the ability to calibrate the bridge offset on each of the 6 bridge sensors using the on-board DAC. 6.8μF + V CC 6.8μF + V DD.μF.μF BRDG VCC VDD BRIDGE 6 IN6+ LDO.μF IN6- INA / PGA OUT k ADC µc 6: MUX ±56mV OFFSET TRIM nf BRIDGE IN+ IN- -BIT DAC PGA I C CONTROL V DD V DD 4.7k 4.7k SDA SCL XR9 AGND DGND Figure 5: 6: Bridge Sensor Interface Layout Considerations General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: Include 6.8µF and.µf ceramic capacitors for power supply decoupling Place the 6.8µF capacitor within.75 inches of the power pin Place the.µf capacitor within. inches of the power pin Connection to the exposed pad is not required. Exposed pad can be connected to ground (GND). Minimize all trace lengths to reduce series inductances 9/

20 Mechanical Dimensions QFN-4 Package TOP VIEW BOTTOM VIEW SIDE VIEW TERMINAL DETAILS Drawing No.: POD-4 Revision: B. /

21 Recommended Land Pattern and Stencil QFN-4 Package TYPICAL RECOMMENDED LAND PATTERN TYPICAL RECOMMENDED STENCIL Drawing No.: POD-4 Revision: B. /

22 Ordering Information () Part Number Operating Temperature Range Lead-Free Package Packaging Method XR9IL4-F XR9IL4TR-F XR9IL4EVB -4 C to +85 C Yes () QFN-4 Evaluation Board Tray Tape & Reel NOTES:. Refer to for most up-to-date Ordering Information.. Visit for additional information on Environmental Rating. Revision History Part Part Part A May 5 Initial Release B July 5 Added Typical Performance Characteristics section. C May 6 D March 8 Updated to latest format and added figure numbers. Updated Figures and 5. Added Figure. Updated page number reference in Gain section of Electrical Characteristics table. Updated Figure 4. Added clarity to I C Bus Addressing section. Updated Table 4. Updated Step in Inputs and Input Selection section. Updated to MaxLinear logo. Updated format and Ordering information table. Added I C Power Up section. Corporate Headquarters: 5966 La Place Court Suite Carlsbad, CA 98 Tel.:+ (76) 69-7 Fax: + (76) High Performance Analog: 6 Rincon Circle San Jose, CA 953 Tel.: + (669) 65-6 Fax: + (669) hpatechsupport@exar.com The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by MaxLinear, Inc.. MaxLinear, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this guide. Complying with all applicable copyright laws is the responsibility of the user. Without limiting the rights under copyright, no part of this document may be reproduced into, stored in, or introduced into a retrieval system, or transmitted in any form or by any means (electronic, mechanical, photocopying, recording, or otherwise), or for any purpose, without the express written permission of MaxLinear, Inc. Maxlinear, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless MaxLinear, Inc. receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of MaxLinear, Inc. is adequately protected under the circumstances. MaxLinear, Inc. may have patents, patent applications, trademarks, copyrights, or other intellectual property rights covering subject matter in this document. Except as expressly provided in any written license agreement from MaxLinear, Inc., the furnishing of this document does not give you any license to these patents, trademarks, copyrights, or other intellectual property. Company and product names may be registered trademarks or trademarks of the respective owners with which they are associated. 6-8 MaxLinear, Inc. All rights reserved XR9_DS_378 /