A Low Phase Noise 4.596GHz VCO for Chip-scale Cesium Atomic Clocks Qingyun Ju 1,a, Xinwei Li 1,b, Liang Tang 2,c, Donghai Qiao 2,d

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1 2016 International Conference on Information Engineering and Communications Technology (IECT 2016) ISBN: A Low Phase Noise 4.596GHz VCO for Chip-scale Cesium Atomic Clocks Qingyun Ju 1,a, Xinwei Li 1,b, Liang Tang 2,c, Donghai Qiao 2,d 1 School of Electronic and Information Engineering, Soochow University, Suzhou, China 2 Institute of Acoustics, Chinese Academy of Sciences, Beijing, China a cljqy@126.com, b lxw91@hotmail.com, c tangliang@mail.ioa.ac.cn, d qiaodh@suda.edu.cn Keywords: low phase noise, atomic clock, VCO, SOLT calibration, coaxial resonator Abstract. The chip-scale cesium atomic clock can provide various devices a high accuracy and high stability frequency reference. According to its operating mechanism, a 4.596GHz voltage-controlled oscillator (VCO) with small volume, low power consumption and low phase noise is vital, serving as a microwave signal source to achieve the closed-loop clocking of the whole system. Based on this, an applicative 4.596GHz VCO is designed by using a coaxial resonator with high quality factor. Firstly, the Short-Open-Line-Thru (SOLT) calibration standards for the network analyzer are designed to extract the parameters of the used coaxial resonator and its equivalent circuit model is built. Secondly, the VCO is designed with the modified Clapp circuit topology and then the transient simulation and the harmonic balance simulation are both run to evaluate the oscillation frequency and the phase noise performance of the designed VCO. Finally, the VCO is tested and the test results show that the phase noises are dBc/Hz@300Hz and dBc/Hz@1KHz, the output power is 0.006dBm and the voltage-controlled tuning sensitivity is about 50MHz/V, well meeting the application requirements of the chip-scale cesium atomic clocks. Introduction Nowadays, the rapid development of more and more fields such as the synchronization of the modern communication networks and accurate positioning and navigation systems has created an impending demand for high accuracy and stability timing tools in battery-powered portable devices. Fortunately, the chip-scale atomic clocks based on the coherent population trapping which is a kind of quantum interference phenomenon produced by the interaction between atoms and coherent light can meet the aforementioned requirements well [1,2], making them have broad application prospects in military and commercial fields. Among all kinds of chip-scale atomic clocks, the one made by the cesium atom has higher precision and stability, and many teams in the world have undertaken development efforts to build the chip-scale cesium atomic clock which includes three parts: the physical package, the servo control systems and the microwave oscillator. The microwave oscillator is usually realized by a VCO with its frequency tuning range covering GHz which is approximately equal to half of the ground-state hyperfine splitting frequency of the cesium atom. Besides, the performance of the VCO has a great influence on the precision and the stability of the chip-scale cesium atomic clock. Meanwhile, it requires that the VCO should have appropriate frequency tuning ability to compensate for the frequency drift caused by the device aging and other factors. In this paper, a small volume, low power consumption and low phase noise 4.596GHz VCO using a coaxial resonator with high quality factor is designed. However, the parameters of the used coaxial resonator found in its datasheet do not consider the actual operating environment like the substrate of the PCB. Thus, it s necessary to extract the parameters of the coaxial resonator and then to build an equivalent circuit model for it based on the test results. In order to extract the parameters accurately and conveniently, the proper SOLT calibration standards are designed. Then the circuit of the VCO based on a modified Clapp circuit topology is designed with the negative resistance analysis method. The requirement of small volume is met by using 0402 SMT technology components and laying out the components in a tightly enclosed topology. Finally, the VCO is measured on a spectrum analyzer, and the measuring results show that the designed VCO has good performance and can be used in the chip-scale cesium atomic clocks.

2 Design of the VCO Parameter Extraction of the Used Coaxial Resonator. For an oscillator operating at frequencies higher than the S band, it is typically that a discrete inductor is replaced by a coaxial resonator which has enormous benefits over traditional discrete inductors by offering much higher quality factor, better temperature stability and no microphonics. In this paper, a ceramic coaxial resonator with a self-resonant frequency (SRF) of 5990MHz and one end shorted is chosen and it will exhibit a proper inductive reactance to the VCO when operated close to the frequency of 4.596GHz. However, the parameters of the used coaxial resonator provided by the manufactory are not proper for an accuracy and reliable simulation of the designed VCO because of their ideality without considering the actual operating environment. So on this occasion, the SOLT calibration method is adopted to extract the parameters of the coaxial resonator and then an accurate equivalent circuit model is built based on the results tested by a vector network analyzer (VNA). The designed SOLT calibration standards mainly include four parts: Short, Open, Load and Thru [3], as shown in Fig. 1(a). Firstly, the full two-port calibration of the VNA is conducted to place the test reference planes at the edges of the component pads. Secondly, a 120nH SMD inductor with a SRF of 800MHz and a tolerance of 5% is measured to verify the precision of the designed standards. The equivalent circuit model of an inductor at high frequencies is depicted in Fig. 1(b) [4] and the Fig.1(c) shows the test results of the phase and the magnitude of the S-parameters obtained on the basis of the SOLT calibration method. According to the results of the model fitting, the values of R, L and C in the inductor model and the SRF are 27.7Ohm, 115nH, 355.4fF and 787.9MHz, respectively. That is, the extracted parameters of the 120nH SMD inductor are very close to the nominal values, indicating that the designed SOLT calibration standards have good precision and reliability. R L (a) (b) (c) Figure 1. (a) The SOLT calibration standards; (b) The equivalent RLC model of an inductor; (c) The S-parameter curves of the tested inductor. Then the used coaxial resonator which can be equivalent to a parallel RLC circuit, as shown in Fig. 2(a) [5], is measured using the same way as the inductor above. The curves of the measured and the fitted S-parameters of the coaxial resonator are shown in Fig. 2(b), showing that the SRF is 6181MHz and meanwhile good coincidence in both of the magnitude response and the phase response between the corresponding curves can be achieved. Finally, the extracted parameters in the model of the coaxial resonator are R=5.2046kOhm, L=0.5837nH and C=1.1358pF. Besides, the unloaded quality factor of the coaxial resonator is calculated to be 232 based on the measurement results. Caused by the effects of the equivalent inductances of pads and the parasitic capacitances between the pad and the ground, the tested SRF of 6181MHz is higher than 6050MHz which is the maximum nominal value of the coaxial resonator and the result is more in line with the actual operating environment. R L C C (a) (b) Figure 2. (a) The equivalent parallel RLC model of a coaxial resonator; (b) The curves of the measured and the fitted S-parameters of the used coaxial resonator.

3 Design and Analysis of the Circuit. The circuit of the VCO is designed with the modified Clapp circuit topology as shown in Fig. 3(a). The Fig. 3(b) is the circuit diagram of the resonant network used in the designed VCO. The adjustable capacitor C1 is realized by a varactor using to provide the VCO an appropriate frequency tuning ability. C2 and C3 together form a feedback voltage divider to generator proper phase shift and voltage feedback and thereby enabling the oscillation to occur. C4 and C5 are coupling capacitors and they are also used to prevent the direct currents flowing through the coaxial resonator. L1 is replaced by a ceramic coaxial resonator with high quality factor. Then the Fig. 3(b) can be changed into the form in Fig. 3(c). R1, R2, R3 and R4 serve as the bias resistors to provide the used BJT desired bias voltages, together forming the gain network. In addition, R4 is used for current feedback, providing the BJT a more stable DC operating point that is less dependent on variations in transistor parameters. L1 and L2 are both used as the RF chokes to prevent the DC power supply from interference introduced by the oscillation signal. L3 can offer a high impedance path in the emitter circuit for the oscillation signal so that a majority of the oscillation power can be fed back to the resonant network rather than being consumed in R4. The T-type attenuation network composed by R5, R6, R7 and R8 can realize a degree of isolation between the output of the designed VCO and the load to decrease the effect of the load pull effectively. The values of the resistors in the attenuation network can be calculated from the following equations: A (1) 2 R P Z0 (2) 1 1 R S Z0 (3) 1 where A is the value of the desired attenuation, Z 0 is generally equal to 50Ohm, R P 0.5R6 0. 5R7 and R S R 5 R8. Vtune is connected to the cathode of the varactor whose junction capacitance will decrease with the increase of Vtune so that the oscillation frequency can be tuned. Thus the VCO can be divided into four main parts: a resonant network, a gain network, an output isolation network and a frequency tuning network. (a) (b) (c) Figure 3. (a) The Clapp circuit topology; (b) The modified Clapp circuit topology; (c) The circuit diagram of the designed VCO. Although the tested SRF of the customized coaxial resonator is 6181MHz, much higher than the desired 4.596GHz, the coupling capacitor C5 can be optimized to tune the series resonant frequency. With the use of the extracted circuit model, the coaxial resonator is simulated with different values of C5 while varying the value of L in the model within its tolerance range which is corresponding to the physical length of the coaxial resonator. Finally, an optimum value of 0.5 pf is obtained and the SRF of the resonator circuit is adjusted to the desired 4.596GHz. The schematic of the resonator circuit and the simulation results are shown in Fig. 4(a) and Fig. 4(b), respectively.

4 (a) (b) Figure 4. (a) The resonator circuit; (b) The simulation results of the resonator circuit. The 4.596GHz VCO is designed with the negative resistance analysis method [6,7]. According to its operating principle, an oscillation will be set up when the absolute value of the negative resistance generated by the active device is greater than the positive resistance of the resonator network, that is, the total impedance of the circuit should be negative. Besides, when the oscillation whose frequency is mainly determined by the imaginary part of the total impedance has been in a stable state, the real part of the total impedance will be equal to zero. Simulation of the VCO. With the use of the ADS software, the designed VCO as shown in Fig. 3(c) is simulated in both the time domain and the frequency domain. The transient simulation is used to evaluate the frequency spectrum and the output power of the oscillation signal. And the phase noise performance of the VCO can be observed by the harmonic balance simulation. Because the low phase noise level is the greatest challenge during the processes of design and optimization, it is necessary to well know the key effect factors of the phase noise. The Leeson s equation [8,9] which is usually used to evaluate the phase noise performance of an oscillator can provide enough insight into the influence tendencies of different factors. L f FkT f0 10lg 1 2Pin 2fQ L 2 fc 1 f f, where f is the frequency offset from the center frequency 0 L f is the ratio of the sideband power in a 1Hz bandwidth at the offset of f to the total output power generated by the oscillator in dbc/hz, F is the large signal noise figure of the active device in db, k is the Boltzmann's constant, T is the equivalent noise temperature in K, P in is the power at oscillator input in dbm, Q L is the loaded quality factor and f c is the flicker corner frequency of the active device. It is apparent that the phase noise performance of the VCO can be improved by choosing a active device with a small noise figure and a low flicker corner frequency, increasing the power at the oscillator input and improving the quality factor of the resonant network. The most effective way is the third one due to the quadratic correlation between the phase noise performance and the loaded quality factor which can be increased markedly by using the aforementioned coaxial resonator. The simulation results are shown in Fig. 5. (4) (a) (b) (c) Figure 5. (a) Signal waveform in the time domain; (b) The simulation results of the frequency spectrum; (c) The simulation results of the phase noise performance.

5 As can be seen in Fig. 5(a), the VCO can start up quickly and a stable oscillation can be reached in a short time. The simulated frequency spectrum of the designed VCO, as shown in Fig. 5(b), indicates that the frequency of the fundamental oscillation is 4.596GHz and the output power is -4.95dBm after an attenuation of 4.5dB generated by the T-type resistor attenuator. Fig. 5(c) shows that the phase noises of the VCO are Bc/Hz@300Hz and dBc/Hz@1KHz, meeting the low phase noise specification of the microwave signal source in the chip-scale cesium atomic clocks well. Measurement of the Designed VCO The photograph of the 4.596GHz VCO is shown in Fig. 6, compared by one RMB. The area in the red rectangular is the circuit of the designed VCO. In order to meet the requirement of small volume specified for the chip-scale cesium atomic clock, the passive components used in the VCO are chosen as 0402 SMT technology components and the VCO is laid out in a tightly enclosed topology. These behaviors result in a VCO with the size of 10mm by 9mm, that is, 0.9cm 2, smaller than the size specification of 1cm 2 of the chip-scale cesium atomic clock [10]. The area in the white rectangular is a power module to provide the VCO a supply voltage of 2.80V generated by a high-efficiency and low noise voltage regulator. With the use of the SMA, the oscillation signal is fed to the test line of a spectrum analyzer and then tested. Figure 6. Photograph of the designed 4.596GHz VCO. The test results are shown in Fig. 7(a) and Fig. 7(b), respectively. Fig. 7(a) shows that the phase noises of the VCO are dBc/Hz@100Hz, dBc/Hz@300Hz and dBc/Hz@1KHz, better than -43dBc/Hz@300Hz calculated from the fractional frequency instability requirement of for one second integration time [10] which is specified by the Defense Advanced Research Projects Agency (DARPA). Fig. 7(b) shows that the tuning sensitivity of the VCO is about 50MHz/V, meaning that a large enough frequency tuning range can be expected to compensate for the frequency deviations caused by changes of the operating temperature, device aging and other factors. The output power of the fundamental oscillation signal is 0.006dBm with a power consumption of 20mW. (a) (b) Figure 7. (a) The test results of the phase noise (b) The test results of the voltage-controlled tuning curve.

6 Summary This paper describes the analysis, design, implementation and characterization of a small volume and low phase noise 4.596GHz VCO used for the chip-scale cesium atomic clocks. In order to improve the accuracy of the simulation, the SOLT calibration standards are designed to extract the parameters of the used coaxial resonator and then an equivalent circuit model for it is built. Then the VCO circuit is analyzed with the negative resistance method and designed with the modified Clapp circuit topology. The phase noise level of the VCO is optimized according to the insight provided by the Leeson s equation. The simulations in both time domain and frequency domain are run to evaluate the characterization of the VCO. The test results show that the VCO is tunable over 151MHz, with a phase noise of dBc/Hz@300Hz, and the size of the VCO is 0.9cm 2, meeting the corresponding application requirements specified for the chip-scale cesium atomic clocks well. Acknowledgement This work is supported by Youth Innovation Promotion Association CAS, the National Natural Science Foundation of China (Grant No ) and Sinoprobe The authors are grateful to Q. Sun and M. Qi, both from Institute of Acoustics, Chinese Academy of Sciences, for sharing their laboratory with us. References [1] T.C. Nguyen, J. Kitching, Towards chip-scale atomic clocks, IEEE International Solid-state Circuits Conference. 1 (2005) [2] M. Jankovic, A. Brannon, J. Breitbarth, et al, Design method for low-power, low phase noise voltage-controlled oscillators, Microwave Integrated Circuit Conference, EuMIC European. (2007) [3] R.F. Ye, J. Xu, SOLT Calibration Method and Its Application to Radio-Frequency Measurement, Chinese Journal of Electron Devices. 29(2006) [4] K. Naishadham, T. Durak, Measurement-based closed-form modeling of surface-mounted RF components, IEEE Transactions on Microwave Theory & Techniques. 50 (2002) [5] A. Brannon, Design and Implementation of Microwave VCOs for Chip-Scale Atomic Clocks, Ph.D. Thesis of University of Colorado. (2007). [6] K. Kurokawa, Some Basic Characteristics of Broadband Negative Resistance Oscillator Circuits, Bell Labs Technical Journal. 48 (1969) [7] J. Everard, M. Xu, S. Bale, Simplified phase noise model for negative-resistance oscillators and a comparison with feedback oscillator models, IEEE Transactions on Ultrasonics Ferroelectrics & Frequency Control. 59 (2012) 1-5. [8] D.B. Leeson, A simple model of feedback oscillator noise spectrum, Proceedings of the IEEE. 54 (1966) [9] G. Sauvage, Phase Noise in Oscillators: A Mathematical Analysis of Leeson's Model, IEEE Transactions on Instrumentation & Measurement. 26 (1978) [10] S. Romisch, R. Lutwak, Low-power, 4.6-GHz, Stable Oscillator for CSAC, International Frequency Control Symposium and Exposition. (2006)