Design of a High-Efficiency Class DE Tuned Power Oscillator

Transcription

1 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 47, NO., NOVEMBER which is determined by trial-and-error, yielded the highest convergence rate. V. CONCLUSIONS For a very general nonlinear DAE circuit system of index one, we have presented a new and simple convergence condition on its WR solution. Namely, for a given circuit partition, if the norms of certain matrices derived from the Jacobians of the differential and algebraic parts in the circuit are each less than one, then the WR solution of the circuit will converge to its transient solution. The sufficient condition obtained in this paper includes conditions previously reported as special cases. Thus, the class of circuits, whose WR solution is guaranteed to converge, is broader than what has been published to date. ACKNOWLEDGMENT The authors would like to thank the reviewers for their valuable comments. REFERENCES [] E. Lelarasmee, A. Ruehli, and A. L. Sangiovanni-Vincentelli, The waveform relaxation method for time-domain analysis of large scale integrated circuits, IEEE Trans. on CAD of IC and Systems, vol., no. 3, pp. 3 45, July 982. [2] Z. Jackiewicz and M. Kwapisz, Convergence of waveform relaxation methods for differential-algebraic equations, SIAM J. Numer. Anal., vol. 33, no. 6, pp , December 996. [3] Y. L. Jiang and O. Wing, A note on convergence conditions of waveform relaxation algorithms for nonlinear differential-algebraic equations, Applied Numerical Mathematics, to be published. [4] J. Bahi, E. Griepentrog, and J. C. Miellou, Parallel treatment of a class of differential-algebraic systems, SIAM J. Numer. Anal., vol. 33, no. 5, pp , October 996. [5] A. I. Zečević and N. Gačić, A partioning algorithm for the parallel solution of differential-algebraic equations by waveform relaxation, IEEE Trans. on CAS-I, vol. 46, no. 4, pp , April 999. [6] G. D. Gristede, A. E. Ruehli, and C. A. Zukowski, Convergence properties of waveform relaxation circuit simulation methods, IEEE Trans. on CAS-I, vol. 45, no. 7, pp , July 998. [7] Y. L. Jiang, W. S. Luk, and O. Wing, Convergence-theoretics of classical and Krylov waveform relaxation methods for differential-algebraic equations, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E80-A, no. 0, pp , October 997. [8] Y. L. Jiang and O. Wing, On the spectra of waveform relaxation operators for circuit equations, IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E8-A, no. 4, pp , April 998. [9] J. Janssen and S. Vandewalle, Multigrid waveform relaxation on spatial finite element meshes: The continuous-time case, SIAM J. Numer. Anal., vol. 33, no. 2, pp , April 996. [0] C. A. Zukowski, The Bounding Approach to VLSI Circuit Simulation. Boston: Kluwer Academic Publishers, 986. [] M. P. Desai and I. N. Hajj, On the convergence of block relaxation methods for circuit simulation, IEEE Trans. on CAS, vol. 36, no. 7, pp , July 989. [2] J. K. White and A. L. Sangiovanni-Vincentelli, Relaxation Techniques for the Simulation of VLSI Circuits: Kluwer Academic Publishers, 987. [3] M. L. Crow and M. D. Ilić, The waveform relaxation method for systems of differential-algebraic equations, in Proceedings of the 29th Conference on Decision and Control, HI, December 990, pp [4] A. Lumsdaine, M. W. Reichelt, J. M. Squyres, and J. K. White, Accelerated waveform methods for parallel transient simulation of semiconductor devices, IEEE Trans. on CAD of IC and Systems, vol. 5, no. 7, pp , July 996. [5] J. Janssen and S. Vandewalle, Convolution-based Chebyshev acceleration of waveform relaxation methods, SIAM J. Numer. Anal., to be published. Design of a High-Efficiency Class DE Tuned Power Oscillator Mitsuhiro Matsuo, Hiroo Sekiya, Tadashi Suetsugu, Kokichi Shinoda, and Shinsaku Mori Abstract This paper presents a high-efficiency class DE tuned power oscillator, along with the analysis, design procedure, and experimental results. It consists of a class DE inverter and a feedback-loop for phase matching and is especially applicable for high frequency performance because it minimizes the power dissipated when turning ON each MOSFET. In contrast to conventional inverters, the proposed oscillator needs an additional complicated circuit including a driver circuit to start the oscillation. The measured efficiency was over 90% at the operating frequency of.0 MHz and output of 2.3 W. Index Terms Class DE, resonant inverter, self-oscillation. I. INTRODUCTION Class DE [] [5] is a new family of the MOSFET tuned power inverters. The optimum waveforms can minimize the switching power loss because of class E switching conditions [] and yield an high efficiency operation, of the order of 95%. Class DE inverters have been used as dc/ac inverters in resonant dc/dc power supplies, solid-state electronics bullets for fluorescent lighting, or in industrial applications as high-frequency power sources for high-frequency electric process heating. In the power converters, the MOSFET s act as switches, and all inverters need gate-drive circuits to drive them. Under this background, Class E high-efficiency tuned power oscillator was proposed by Ebert et al. [6]. This circuit has no gate-drive circuit to drive the MOSFET. In this paper, we present an analysis, a design procedure, and experimental results for the proposed circuit. The oscillator needs a additional complicated circuit including a driver circuit to start the oscillation. We show that in a properly designed oscillator circuit, it is possible to achieve the same efficiency as that of a power inverter working at the same frequency and using the same MOSFET. II. CLASSES OF FET Power amplifiers are classified by the operation of their output transistors. In classes A, B, and C, transistors are used in the active region; therefore they are generally suitable for use in low power ac converters. Classes D [7] [0] and E [] [4] amplifiers have been used as high-efficiency power inverters. Manuscript received December 6, 996; revised October 20, 997, August 5, 999, July 6, 2000, and July 24, This work was supported by Nippon Telegraph and Telephone Corporation, Forum Engineering Inc., and Schlumberger Corporation. This paper was recommended by Associate Editor A. Ioinovici. M. Matsuo, was with the Department of Electrical Engineering, Keio University, Yokohama, Japan. He is now with Matsushita Electrical Industrial, Company, Ltd., Osaka, Japan ( mmatsuo@isl.mei.co.jp). H. Sekiya is with the Department of Electrical Engineering, Keio University, Yokohama, Japan. K. Shinoda was with the Department of Electrical Engineering, Keio University, Yokohama, Japan. He is now with DENSO Corporation, Kariya, Aichi, Japan. T. Suetsugu is with the Department of Electronics and Computer Science, Fukuoka University, Fukuoka, Japan. S. Mori is with the Department of Electrical and Electronics Engineering, Nippon Institute of Technology, Minami-Saitama, Saitama, Japan. Publisher Item Identifier S (00) /00$ IEEE

2 646 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 47, NO., NOVEMBER 2000 A class D inverter [Fig. (a)] is composed of two switch devices S and S 2, and a series resonant circuit 0L r 0C f. S and S 2 conduct on alternate half cycles. The voltages v S, v S2 are square waveforms. A series resonant tank converts the square voltage waveform into a sinusoidal load current [Fig. (b)]. The efficiency is reduced by the loss in the inherent device capacitance under RF operation because of non zero-voltage-switching (ZVS). A class E inverter [Fig. 2(a)] consists of a single switch S, a shunt capacitor C s, a load network, and an RF choke (RFC). The load network is composed of a series resonant circuit 0 L r 0 C f. The input current I cc through the RFC is forced to be constant. The output current i r through the series resonant circuit L f 0 C f is sinusoidal [Fig. 2(b)]. The switching loss at the turn on transition is reduced to zero due to ZVS and low (dv=dt) operations. The inverter keeps high efficiency under RF operation. In the optimum class E operation, the switch voltage stress is about 3.6 times of the dc-input voltage [2] higher than that in class D inverters. A class DE inverter is a class D inverter in which class E switching conditions are used [] [5]. The efficiency at high-frequency operation is as high as that of a conventional class D-type under lower-frequency operation. A shunt capacitor is added to each switch for keeping the class E switching conditions. Its switch voltage stress is equal to the dc-input voltage. Consequently, the switch voltage waveforms have the characteristics of both of the classes D and E. III. CLASS DE INVERTER Fig. 3(a) depicts a class DE inverter that is composed of two switches S and S 2, two capacitors C s and C s2 shunting each switch, and a series resonant circuit 0 L r 0 C f. The switches are driven by a pattern shown in Fig. 3(b), which generates a dead-time between the instant when one switch has turned OFF and another switch will turn ON. During the dead-time, the sinusoidal output current i o charges one shunt capacitor and discharges the other shunt capacitor, and the midpoint voltage between two switches becomes V cc or zero at the end of the dead time, allowing class E switching condition. The analysis of class DE inverter was carried out in [] [5], and circuit components with dead time duty ratio of 0.25 are calculated from the following equations: Fig.. Class D inverter. (a) Basic circuit. (b) Waveforms. P out = V 2 cc () 2 2 C s = C s2 = (2) 2! Q =!L r (3) C f = (4)! Q 0 2 where P out output power; V cc dc input voltage;! angular operating frequency; Q load quality factor. IV. CIRCUIT ANALYSIS A. Conditions for Optimum Operation of Class DE Oscillator The purpose of this paper is to derive a suitable feedback circuit for the class DE oscillator and a procedure for determining the values of all circuit components. To achieve this, one must design a two-port network, which fulfills the following assumptions. Fig. 2. Class E inverter. (a) Basic circuit. (b) Waveforms. The energy stored in the oscillator s network should be high enough to ensure the necessary frequency stability. The feedback signal should have the same amplitude and phase as the input signal of the corresponding class DE inverter. To perform these assumptions, the phase-shift circuit should consist of a reactance network (inductor and capacitor). The necessary modification of the inverter circuit may be accomplished by providing an additional phase and amplitude matching circuit to design the proposed oscillator. Feedback voltage is used as driving voltage turned by center-tapped transformer. If the amplitude of driving signals D s and D s2 are larger than the threshold voltage

3 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 47, NO., NOVEMBER Fig. 4. Load network of the proposed oscillator. Fig. 5. Two sinusoids out of phase by 80, threshold voltage V of the device, and the resulting dead time. resulting in Fig. 3. Class DE inverter. (a) Basic circuit. (b) Waveforms of MOSFET, the switches turn on. The feedback sinusoidal wave is used as a driving signal. B. Analysis of Load Network and Phase The load network introduced in [6] is shown in Fig. 4. C g and R g are nonlinear components. But we consider these components as linear to analyze this oscillator more easily. To determine the transmission matrix of the load network including the phase shift circuit, we consider the load network as a two-port network. The load network consists of the series resonant part of the inverter, phase shift part and gate input part of the MOSFET. Transmission matrix [F0] is [F0] =[F][F2][F3] = A 0 B0 C0 D0 where matrices [F], [F2], and [F3] are (5) A0 = + X 0 + C 2 C + sc2x0 + + X 0 sl + sc + sl C2 C R g + + +s 2 LC2 X0 (9) B0 = + X 0 sl + sc + sl C2 C +(+s 2 LC2)X0 (0) C0 = + C 2 C + sc2 + R g + sl + slc2 sc + +(+s 2 LC2) () C D0 = sl + sc + sl C2 +(+s 2 LC2) (2) C where X0 = sl r + sc f : (3) [F] = [F2] = [F3] = + sl r + sc r sl r + sc r + C2 C sc2 sl + sc + slc2 C +s 2 LC2 (6) (7) 0 R g + (8) The output current of the two-port network [F0] is From it is found that A0 = I2 =0: (4) V V2 I =0 (5) V2 = V A0 : (6)

4 648 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 47, NO., NOVEMBER 2000 TABLE I CHARACTERISTICS OF IRF50 MOSFET In the steady state of the ac mode, s = j!. Therefore from (9) and (5) V 2 = V V = A 0 Re(A 0 )+jim(a 0 ) : (7) where Re(A o ) means real part of A o and Im(A o ) means imaginary part of A o. Furthermore, Fourier analysis of switch voltage v S across S and its driving signal D s gives the fundamental components V (fund) = V cc 0 cos(!t) + 2 V 2(fund) = 0 p 2V t sin!t 0 4 sin(!t) (8) (9) where V t is the threshold voltage of MOSFET. Therefore ja 0 j = jv (fund)j jv 2(fund) j =0:49 V cc V t : (20) By the way, phase angle in the resonant inverter is 90 because class DE inverter has inductive resistance. And phase angle between output sinusoidal voltage and driving signal is 45. Therefore the phase angle between the input and output in the two-port network is 35. And from (7) Im(A o) =tan 0 Re(A = 35 (2) o) Furthermore, L 0 C g is the gate resonant circuit, which means Fig. 6. Experimental circuit of the Class DE Oscillator. L C g! 2 =: (22) Consequently, if we specify the values of!, V cc,, and Q, the circuit elements in the DE inverter (C s, L r, and C r ) are calculated from () (4). If we give the MOSFET s specifications R g and C g from the data sheet, the circuit elements in the phase shift circuit (C, C 2, and L ) are calculated from (7), (20), and (22). C. Sinusoidal Gate Drive with Dead-Time Control In the case of a power MOSFET, the turn-on transition occurs very fast once the drive signal has crossed the threshold. We use a sinusoidal input voltage because it is easy to control the dead time between the two devices by changing the amplitude of the sinusoidal wave. The gate voltages are sinusoidal out of phase by 80 (Fig. 5). One device will be turning off if the gate voltage decreases below the threshold level. This device is off until the gate voltage is over the threshold level. At the same time, the other device will be off if the gate voltage is below the threshold level. Thus, during this period, the two devices are off, resulting in the dead-time. Given the threshold voltage of the devices, we can determine the gate drive voltage required for a specific dead time. The voltage V gs across the gate source capacitance is V gs (t) =V gs sin(! s t): (23) Fig. 7. Waveforms for the optimum operation at f = :0 MHz, V =20 V, R =2:5. Vertical : 20 V/div; horizontal: 200 ns/div. where! s is the angular switching frequency. The gate voltage is equal to the threshold voltage V t at time t d =2 i.e., V t = V gs sin! s t d 2 V gs = V t sin! s t d 2 (24) : (25) From (25), we have the required gate voltage for a given deadtime. However, it is important to examine the range of the dead time achievable using a sinusoidal wave. In order to do this, (25) is rearranged as follows: t d = 2 V sin 0 t : (26)! s V gs At the operating frequency of.0 MHz, V t =5:0Vand peak gate voltage limited to 20.0 V, the deadtime is 6 ns at V gs =7:V. The

5 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 47, NO., NOVEMBER dependence of the dead time on the amplitude of the gate drive voltage makes the feedback circuit design very simple. V. DESIGN PROCEDURE We perform the design for the specifications: operating frequency f o =:0MHz, deadtime duty-ratio = 0.25, load resistance =2:5, quality factor Q = 0 and input dc voltage V cc = 20 V (see, Fig. 7). From [2], the relationship between the input dc voltage and output sinusoidal voltage is jv oj = V cc : (27) Therefore, the output voltage v o is 6.37 V. Using () (4) and (9) (9), we find the values of the circuit elements of the inverter part as C s = C s2 = 2 (2 :0 0 6 ) 2:5 = 2:03 [nf] (28) 2:5 L r =0 2 :0 0 6 = 9:89 [H] (29) C f = (2 :0 0 6 ) :5 = 5 [pf]: (30) IRF50 MOSFET s were used as switches S and S 2. Their characteristics of are shown in Table I. Using (9) (22) and (28) (30), we find the values of the circuit elements of the phase-shift part of the oscillator as [2] H. Koizumi, T. Suetsugu, M. Fujii, K. Shinoda, S. Mori, and K. Ikeda, Class DE high-efficiency tuned power amplifer, IEEE Trans. Circuits Syst., Part I, vol. 43, pp. 5 60, Jan [3] S. A. El-Hamamsy, Design of high-efficiency RF class-d power amplifier, IEEE Trans. Power Electron., vol. 9, pp , May 994. [4] D. C. Hamill, Class DE inverters and rectifiers for DC-DC converter, in IEEE Proc., Power Electron. Specialist Conf. (PESC 96), June 996, pp [5] K. Shinoda, M. Fujii, M. Matsuo, T. Suetsugu, and S. Mori, Idealized operation of Class DE frequency multipliers, IEEE Proc., Int. Symp. Circuits Syst. (ISCAS 96), vol., pp , May 996. [6] J. Ebert and M. K. Kazimierczuk, Class E high-efficiency tuned power oscillator, J. Solid-State Circuits, vol. SC-6, no. 2, pp , Apr. 98. [7] P. J. Baxandall, Transistor sine-wave LC oscillators, some general considerations and new developments, Proc. IEE, pt. B, vol. 06, pp , May 959. [8] W. J. Chudobiak and D. F. Page, Frequency and power limitations of class-d transistor amplifier, IEEE J. Solid-State Circuits, vol. SC-4, pp , Feb [9] M. K. Kazimierczuk and J. S. Modzelewski, Drive-transformerless class-d voltage-switching tuned power amplifier, Proc. IEEE, vol. 68, pp , June 980. [0] D. Czarkowski and M. K. Kazimierczuk, Simulation and experimental results for class D series resonant inverter, in IEEE Int. Telecom. Energy Conf. (INTELEC 92), Oct. 992, pp [] N. O. Sokal and A. D. Sokal, Class E-A new class of high-efficiency tuned single-ended switching power amplifiers, IEEE J. Solid-State Circuits, vol. SC-0, pp , June 975. [2] F. H. Raab, Idealized operation of the class E tuned power amplifier, IEEE Trans. Circuit Syst., vol. CAS-24, pp , Dec [3] N. O. Sokal and F. H. Raab, Harmonic output of class E RF power amplifiers and load coupling network design, IEEE J. Solid-State Circuits, vol. SC-3, pp , Apr [4] F. H. Raab, Effects of circuit variations on the class E tuned power amplifier, IEEE J. Solid-State Circuits, vol. SC-3, pp , Apr C =264 [pf] (3) C 2 =50 [pf] (32) L = 26:65 [H]: (33) Self-Control of Chaotic Dynamics using LTI Filters Pabitra Mitra VI. EXPERIMENTAL RESULTS An experimental circuit designed in Section V was tested. For starting, we gave the driving signals D s and D s2 from reference inverter because the circuit needs an external trigger signal to start the oscillation. Fig. 6 shows the waveforms of the switch voltage v s and output voltage v o. They agreed well with theoretical predictions. The measured efficiency was 93.3% at the output of 2.3 W and operating frequency of.0 MHz. VII. CONCLUSION In this paper, a high-efficiency class DE tuned power oscillator was introduced. The proposed circuit can be used as a simple high-efficiency tuned power inverter. The analysis, design examples, and experimental results were presented. The measured performance showed good agreement with the theoretical predictions. REFERENCES [] S. A. Zhukov and V. B. Kozyrev, Double-ended switching generator without commutating loss (in Russian), Poluprovodnikovye Pribory v Tekhnike Elektrosvyazi, vol. 5, pp , 975. Abstract In this brief, an algorithm for controlling chaotic systems using small, continuous-time perturbations is presented. Stabilization is achieved by self controlling feedback using low order LTI filters. The algorithm alleviates the need of complex calculations or costly delay elements and can be implemented in a wide variety of systems using simple circuit elements only. Index Terms Feedback control of chaos, linear time invariant filters, unstable periodic orbits. I. INTRODUCTION There has been some increasing interest in recent years in the study of controlling chaotic nonlinear systems [2], [7]. The possibility of obtaining periodic waveforms from a chaotic system by stabilizing any of the numerous embedded unstable periodic orbits (UPO s) has been the guiding control philosophy. The breakthrough in this direction is the Manuscript received October 2, 999; revised May 9, This paper was recommended by Associate Editor C. K. Tse. The author is with the Machine Intelligence Unit, Indian Statistical Institute, Calcutta, India ( pabitra_r@isical.ac.in). Publisher Item Identifier S (00) /00$ IEEE