Analysis of Class-DE Amplifier With Linear and Nonlinear Shunt Capacitances at 25% Duty Ratio

Transcription

1 2334 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 57, NO. 9, SEPTEMBER 2010 Analysis of Class-DE Amplifier With Linear and Nonlinear Shunt Capacitances at 25% Duty Ratio Hiroo Sekiya, Member, IEEE, Natsumi Sagawa, and Marian K. Kazimierczuk, Fellow, IEEE Abstract The class-e zero-voltage switching/zero-derivative switching operation within class-de amplifiers can be easily achieved by adding external shunt capacitances. This paper gives the analytical expressions for the designs of the class-de amplifiers with the shunt capacitances composed of linear and nonlinear capacitances for any grading coefficient of MOSFET body junction diodes at the switch-on duty ratio.in the analysis, an equivalent linear shunt capacitance of the nonlinear MOSFET drain source parasitic capacitances is derived. Analytical results show good agreements with the simulation and experimental ones, which validate our analysis. Index Terms Class-DE power amplifier, class-e zero-voltage switching (ZVS)/zero-derivative switching (ZDS) conditions, equivalent linear shunt capacitance, high efficiency, nonlinear MOSFET drain source parasitic capacitance. I. INTRODUCTION T HE CLASS-DE power amplifier [1] [10] is one of the high-efficiency power amplifiers. By adding shunt capacitances to MOSFETs of the class-d amplifier, the class-de amplifier satisfies the class-e zero-voltage switching (ZVS) and zero-derivative switching (ZDS) conditions, yielding high efficiency at high frequencies. It is known that the highest operating frequency of the class-de amplifier is obtained for the 25% switch-on duty ratio [4]. For the design of the class-de amplifiers, the operating frequency is one of the most important specifications. In the case of low-frequency operation, the shunt-capacitance values should be very high. Conversely, the shunt capacitances should be low for high-frequency operation. The minimum shunt capacitances are the drain source parasitic capacitances of MOSFETs, which depend on the kind of MOSFETs. However, the degrees of freedom for the design are reduced when the shunt capacitances consist of only the parasitic capacitances of the MOSFETs. For example, when the operating frequency, dc-supply voltage, and output power are specified, the values Manuscript received August 12, 2009; revised December 15, 2009; accepted January 26, Date of publication March 15, 2010; date of current version October 01, The work of H. Sekiya was supported by the Japan Society for the Promotion of Science. This paper was recommended by Associate Editor E. Alarcon. H. Sekiya and N. Sagawa are with the Graduate School of Advanced Integration Science, Chiba University, Chiba , Japan, ( sekiya@faculty.chiba-u.jp). M. K. Kazimierczuk is with the Department of Electrical Engineering, Wright State University, Dayton, OH USA. Digital Object Identifier /TCSI of shunt capacitances are determined uniquely [8], [10]. Therefore, designers have to look for MOSFETs whose drain source parasitic capacitances are matched with the required values. However, it is not an easy task. For this reason, generally, external capacitances are added in parallel to the MOSFETs in order to adjust the shunt-capacitance values. Because of the adjustment of the shunt capacitance, it becomes easy to design the class-de amplifiers with fixed operating frequency, dc-supply voltage, and output power. For low-frequency operation, the shunt-capacitance values are large. In this case, the effects of the MOSFET drain source parasitic capacitances can be neglected because the values of MOSFET drain source parasitic capacitances are small. On the other hand, the effects of the MOSFET drain source parasitic capacitances increase as the operating frequency becomes high. The problem is that the MOSFET drain source parasitic capacitances are nonlinear and the external ones are linear [8] [20]. We should consider both the nonlinearity and linearity of the shunt capacitances in order to design the class-de amplifiers for high-frequency operation. The class-de amplifiers analyzed until now have only the linear shunt capacitances [1], [2] or only the nonlinear ones [7] [10]. It is important to derive analytical expressions for the class-de amplifier with the shunt capacitances composed of the linear and nonlinear shunt capacitances. A similar problem appears in the class-e amplifier. References [11] [18] gave the analytical expressions for the class-e amplifier with the nonlinear shunt capacitance only and the linear and nonlinear shunt capacitances, which present the effective analytical techniques for the problem of this paper. This paper, which was previously presented in part at the 2009 IEEE International Symposium on Circuits and Systems (ISCAS 2009) [20] 1, gives analytical expressions for the designs of the class-de amplifiers with the shunt capacitances composed of linear and nonlinear capacitances for any grading coefficient at the 25% switch-on duty ratio. The obtained expressions include the results for the case of not only both the linear and nonlinear shunt capacitances, but also the linear or nonlinear shunt capacitances only. In the analysis, an equivalent linear shunt capacitance of the nonlinear MOSFET drain source parasitic capacitances is obtained. By using the value of the equivalent linear shunt capacitance, the values of the external shunt capacitances are determined easily. In the design equations, a numerical calculation is needed for obtaining the resonant-inductor value. However, this numerical calculation is replaced with an approximate fixedvalue.byusingthefixed value, it 1 In the paper of ISCAS 2009, only the analysis for was presented. In this paper, the analysis is carried out for any grading coefficient along with new design examples and experimental results /$ IEEE

2 SEKIYA et al.: ANALYSIS OF CLASS-DE AMPLIFIER WITH SHUNT CAPACITANCES AT 25% DUTY RATIO 2335 Fig. 1. Class-DE amplifier. (a) Circuit topology. (b) Equivalent circuit. is possible to obtain the design values from only the analytical expressions. Analytical results show good agreements with the simulation and experimental ones, which indicate the validity of our analysis. In the Appendix, perturbation analysis is presented in order to obtain the power conversion efficiency for the class-de amplifier with linear and nonlinear shunt capacitances, following the analysis procedure in [1] and [5] [8]. II. FUNDAMENTAL OPERATION OF THE CLASS-DE AMPLIFIER Fig. 1 shows the circuit topology of the class-de amplifier [1] [10]. This amplifier consists of two switching devices and, e.g., MOSFETs, the shunt capacitances and, and series-resonant circuit. The inductance is divided into and. The elements and realize a series tuned circuit with its resonant frequency equal to the operating frequency. The phase shift of the output current is obtained by. Fig. 2 shows the example waveforms of the class-de amplifier for the nominal operation at the duty ratio. Both the switches turn ON and OFF alternately. During one cycle of class-de amplifier operation, there are two dead-time intervals when both switches are OFF. In the dead-time intervals, the voltage across one switch decreases and reaches zero when the switch turns ON. In addition, the slope of the voltage across each switch is also zero at the turn-on instant, i.e., These conditions are called the class-e ZVS and ZDS conditions. The dead-time intervals are required to recharge the shunt capacitances. Because of the dead-time and the class-e ZVS/ZDS conditions, the switching power losses of the MOS- FETs of class-de amplifier are zero. Therefore, the high drain efficiency can be achieved at high frequencies. The class-de amplifier satisfies the class-e ZVS/ZDS conditions by adding the shunt capacitances and to the MOSFETs in the (1) (2) Fig. 2. Nominal waveform of the class-de amplifier for. class-d amplifier. Usually, the shunt capacitances are realized by the sum of the external linear capacitances and the MOSFET nonlinear drain source parasitic capacitances. III. CIRCUIT ANALYSIS A. Assumptions The analysis in this paper is based on the following assumptions. 1) Both MOSFETs are identical, and each MOSFET is modeled as an ideal switch and a drain source parasitic capacitance connected in parallel. The drain source parasitic capacitances of the MOSFETs are expressed as and (3) In (3), is the drain-to-source voltage; is the built-in potential, which typically ranges from 0.5 to 0.9 V; is the capacitance at ;and is the grading coefficient of the diode junction of the MOSFET [7] [14], which is in the range. According to the assumption of the identical MOS- FETs,,,and are valid. 2) The identical linear shunt capacitances are connected to both MOSFETs in parallel, which are expressed as. 3) All passive elements except the MOSFET drain source parasitic capacitances are linear elements and do not have parasitic resistances.

3 2336 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 57, NO. 9, SEPTEMBER 2010 TABLE I SWITCHING PATTERN IN CLASS-DE AMPLIFIER From (4) and (7) (9), the current through switch as is obtained (10) Time Interval: interval. Therefore : Both switches are OFF in this 4) The loaded-quality factor of the resonant circuit is high enough to generate pure sinusoidal output current. The current through the circuit and load resistance is sinusoidal at the operating frequency From (3), (5), (6), and,wehave (11) (4) where represents the angular time. Usually, the loaded quality factor is defined as. In this paper, however, the definition of is used because of the simple derivations of the load-network-component values. 5) The ideal resonant filter with the resonant frequency is realized by and. 6) The switch-on duty ratio is 0.25, and the switching patternisgivenintablei. Using the aforementioned assumptions, the equivalent circuit of the class-de amplifier is obtained, as shown in Fig. 1(b). From (12), the following can be derived: (12) (13) B. Expressions for Waveforms The analysis for a steady state is performed in the interval. The following relation between and is always valid: The switch voltage is zero at due to the class-e ZVS condition in (2). Therefore, from (13), the amplitude is obtained as The slope of the switch voltage expressed as (5) at dead-time intervals is By substituting (14) into (13), we can obtain (14) (6) Hence, using the class-e ZDS condition in (1), we obtain and. Since the amplitude of the output current is positive, the phase difference is (7) Similarly, (7) is valid for to satisfy the class-e ZDS condition in (2). Time Interval: : Since is ON and is OFF, the switch voltages in this interval are constant and shunt capaci- In addition, the current through switch tances is (8) (9) (15) It is impossible to solve (15) for analytically, but possible to do that numerically. From (15), we can obtain important information that the normalized switch voltages and are expressed as functions of the ratio of the dc-supply voltage to the built-in potential, the ratio of the linear shunt capacitances and the drain source parasitic capacitances, the grading coefficient, and the angular time.

4 SEKIYA et al.: ANALYSIS OF CLASS-DE AMPLIFIER WITH SHUNT CAPACITANCES AT 25% DUTY RATIO 2337 The output power is obtained from (14) (19) Fig. 3. Example waveforms of normalized switch voltage for and. Time Interval: : Because of the symmetrical operations of the switches with respect to,theswitch voltages and currents have the following relationships for : (16) Fig. 3 shows the example waveforms of the normalized switch voltage for and,whichis computed by applying Newton s method to (15). In this figure, makes the shunt capacitances practically linear. The waveforms in Fig. 3 can be obtained for the proper designs. The purpose of the designs is to obtain the elemental values that provide the waveforms in Fig. 3. C. Power Relations and Equivalent Linear Capacitances of MOSFET Drain Source Parasitic Capacitances Note that the average value of the current through the shunt capacitance is always zero at any. Therefore, the dc-supply current is analytically obtained from the average value of the supply current flowing from the dc voltage source as where is the amplitude of the output voltage. The power losses never occur because of the assumptions of ideal switching operations and no parasitic resistance. Therefore, we can write (20) From (18) (20), we can obtain the relation between the dc-supply voltage and the amplitude of the output voltage as (21) This equation means that the amplitude of the output voltage increases in proportion to the increase of the dc-supply voltage and is independent of the grading coefficient. From (21), the output power can be rewritten using From (19) and (22), the following relation is obtained: (22) (23) Here, we define the equivalent linear capacitance as a linear shunt capacitance, which can be substituted for the nonlinear MOSFET drain source parasitic capacitance to satisfy the class-e ZVS/ZDS at the same values of,, and [11], [13], [14]. From (23), it is obtained (24) Generally,,,and are uniquely determined by the MOSFET. In addition,,,and are obtained from the specified conditions. From (23) and (24), we can calculate that satisfies the class-e ZVS/ZDS conditions. It is shown that the external linear shunt capacitances are very useful to adjust the waveforms for satisfying the class-e ZVS/ZDS conditions. D. Voltage Across Resonant-Circuit Reactance The fundamental component of the voltage reactance is across the (17) (25) From (17), the dc-supply power is obtained as where (18) (26)

5 2338 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 57, NO. 9, SEPTEMBER 2010 TABLE II PARAMETERS OF EACH MOSFET Fig. 5. Normalized nonlinear shunt capacitances and normalized equivalent linear shunt capacitances as a function of the switch voltage for V. Fig. 4. Characteristics of for, 0.25, 0.5, and (a) As a function of for fixed. (b) As a function of for. Because of the assumptions on the high- and the ideal resonant filter, the fundamental-frequency component of the switch voltage is Hence the normalized magnitude analysis (27) (28) is obtained from the Fourier (29) We cannot obtain the analytical expression of this integration. Here, the coefficient is defined as functions of and at fixed. From Fig. 4(a), the value of increases with the increase in and. However, the differences among them are small. In Fig. 4(a), all plots are within the 5% difference of the linear-shunt-capacitance case, i.e.,. From Fig. 4(b), it is shown that increases with the decrease in for fixed, which is also confirmed in Fig. 4(a). When increases, the values of for any converge to that for.this is because nonlinearities of shunt capacitances are suppressed with the increase in. E. Load Network Components From (22), the load resistance is given as Using the definition of the loaded-quality factor the resonant capacitance as (31),weobtain The external shunt capacitance is obtained from (23) and (24) (32) (30) (33) which is obtained numerically. Since the normalized switch voltage is a function of,,and, is also a function of them. Fig. 4 shows the plots for as From,,and, we can obtain numerically. From Assumption 5), the ideal resonant filter with the resonant frequency is realized by and.from

6 SEKIYA et al.: ANALYSIS OF CLASS-DE AMPLIFIER WITH SHUNT CAPACITANCES AT 25% DUTY RATIO 2339 TABLE III ANALYTICAL PREDICTIONS AND EXPERIMENTAL MEASUREMENTS Fig. 6. Normalized equivalent linear shunt capacitances as a function of. The measured efficiencies. values are used for the calculations of power conversion Fig. 8. Driver circuit for 25% duty ratio. From (21), (26), and (30), the inductance is given as (35) From (34) and (35), the resonant inductance is obtained as (36) Fig. 7. External shunt capacitances. (a) As a function of the switch voltage at MHz. (b) As a function of the operating frequency for V. and (32), the resonant capacitance expressed analytically as is (34) If the loaded-quality factor is defined as, is needed in order to obtain. However, the value of is a function of.whenwedefine the loaded-quality factor as, we can obtain without. This is a reason for the change in the definition of. In these design equations, only should be obtained numerically, which affects the value of. We should note that the analysis in this paper is based on the assumption of high-, which is usually. In addition, the values of are within a few percent difference from. Therefore, for simplicity, it is allowed to put for all cases.

7 2340 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 57, NO. 9, SEPTEMBER 2010 Fig. 9. Waveforms by PSPICE simulations and circuit experiments. (i) 2SK2504 MOSFETs. (ii) IRFZ24N MOSFETs. (iii) IRF530 MOSFETs. (a) PSPICEsimulation results. (b) Experimental results. (Horizontal) 100 ns/div. (Vertical) :5V/div; and : 20 V/div; and : 10 V/div. IV. DISCUSSIONS AND DESIGN EXAMPLES The design examples by using three kinds of the discrete MOSFET devices are given. In the design examples, the MOSFETs of 2SK2504 manufactured by Rohm, IRFZ24N, and IRF530 by International Rectifier are used as the switching devices. The built-in potentials, the grading coefficients,and can be obtained from the SPICE model [19], as shown in TableII.Thevaluesof,,,and correspond to those of VJ, M, CJ0, and RS in the MOSFET SPICE models, respectively. Note that each MOSFET has a different value of.the load resistance is given as a design specification. Fig. 5 shows the normalized nonlinear shunt capacitances and the normalized equivalent linear shunt capacitances as a function of the switch voltage for V. is symmetrical with respect to V. This symmetry generally occurs because is always valid. From this figure, it is shown that the normalized shunt capacitances decrease with the Fig. 10. Equivalent circuit of the class-de amplifier with ESRs. increase in the grading coefficient. The grading coefficient is an important parameter to design the class-de amplifier. Fig. 6 shows the normalized equivalent linear shunt capacitance as a function of the ratio of dc-supply voltage to the built-in potential for satisfying the class-e ZVS/ZDS conditions. These plots are obtained from (24). From

8 SEKIYA et al.: ANALYSIS OF CLASS-DE AMPLIFIER WITH SHUNT CAPACITANCES AT 25% DUTY RATIO 2341 this figure, it is shown that the normalized equivalent linear shunt capacitances decrease as the dc-supply voltage increases. In particular, they vary rapidly for small. Fig. 7(a) shows the external shunt capacitances as a function of for satisfying the class-e ZVS/ZDS conditions at MHz. These plots are obtained from (33). The total shunt capacitances are independent of the dc-supply voltage from (33). In addition, the equivalent linear shut capacitances decrease as the dc-supply voltage increases, as shown in Fig. 6. Therefore, the external shunt capacitances increase with the increase in the dc-supply voltage. From Fig. 7(a), we can confirm that the value of external shunt capacitance depends on the MOSFETs. The external shunt capacitances become almost constant for large. Fig. 7(b) shows the external shunt capacitances as a function of the operating frequency for satisfying the class-e ZVS/ZDS conditions at V. The external shunt capacitances decrease with the increase in the operating frequency. It can be seen that the maximum frequency is obtained when the external shunt capacitance is zero. From (23) and (24), the maximum frequency is obtained as (37) This expression is very similar to that for the class-e amplifier [18]. The maximum frequency depends on the MOSFETs, which are 10.6 MHz for 2SK2504, 9.55 MHz for IRFZ24N, and 3.75 MHz for IRF530. For the circuit experiments, the class-de amplifiers were designed for the operating frequency MHz, the dc-supply voltage V, the load resistance,andthe loaded-quality factor. Using these specifications, we can obtain pf from (32). Here, the design with 2SK2504 is considered. The external capacitance is obtained as pf from (24). From,,and, is obtained numerically. By using this value, is determined from (36). Table III gives the elemental values for all MOSFETs. In these design specifications, the resonant inductances for all MOSFETs are within since the values of are almost the same as 0.5. In addition, the driver signals with 25% switch-on duty ratio are generated from the driver circuit, as shown in Fig. 8, in the circuit experiments. Fig. 9 shows the simulated waveforms obtained by PSPICE and the experimental ones. In addition, Table III gives the analytical predictions and experimental measurements. In this table, the element values were measured by the HP-4284A LCR meter. Both the simulated and experimental waveforms are satisfied with the class-e ZVS/ZDS conditions. These results indicate the validity of the analysis in this paper. The laboratory measurements showed more than 94% efficiency for all MOSFETs. The analytical derivation of the power conversion efficiencies is shown in the Appendix. V. CONCLUSION This paper has presented the analytical expressions for the designs of class-de amplifier with shunt capacitances composed of linear and nonlinear capacitances for any grading coefficient at the 25% switch-on duty ratio. In the analysis, an equivalent linear shunt capacitance of nonlinear MOSFET drain source parasitic capacitance is defined. The analytical results have shown good agreements with the simulation and experimental ones, which validate our analysis. APPENDIX PERTURBATION ANALYSIS In real circuits, power losses occur in the equivalent series resistance (ESR) of each component. Fig. 10 shows the equivalent circuit of the class-de amplifier with ESRs, where and are the MOSFET on-resistances and the ESR of the series-resonant-circuit elements and, respectively. Generally, the ESRs of the MOSFET drain source parasitic capacitances and the external shunt capacitances and are much lower than the other ESRs. In addition, the current through the shunt capacitances is shared by the MOSFET drain source parasitic capacitances and the external shunt capacitances. Therefore, the power dissipations at the ESRs of shunt capacitances are negligible. It is assumed that the ESR of the resonant inductor and the switch on-resistances are much lower than the load resistance [1], [8]. In this case, the voltage and current waveforms are not significantly affected by the ESR and the switch on-resistance. The power losses in ESRs of the switch on-resistance and the series-resonant circuit are From (38), the power conversion efficiency obtained (38) is approximately (39) REFERENCES [1] H. Koizumi, T. Suetsugu, M. Fujii, K. Shinoda, S. Mori, and K. Ikeda, Class DE high-efficiency tuned power amplifier, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 43, no. 1, pp , Jan [2] S. A. El-Hamamsy, Design of high-efficiency RF class-d power amplifier, IEEE Trans. Power Electron., vol. 9, no. 3, pp , May 1994.

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Bernal, Design of class E amplifier with nonlinear and linear shunt capacitances for any duty cycle, IEEE Trans. Microw. Theory Tech., vol. 55, no. 3, pp , Mar [18] A. Mediano and P. Molina, Frequency limitation of a high-efficiency class E tuned RF power amplifier due to a shunt capacitance, in IEEE MTT-S Int. Microw. Symp., Anaheim, CA, Jun. 1999, pp [19] R. M. Kielkowski, SPICE: Practical Device Modeling. New York: McGraw-Hill, [20] H. Sekiya, R. Miyahara, and M. K. Kazimierczuk, Design of class-de amplifier with linear and nonlinear shunt capacitances for 25% duty ratio, in Proc. IEEE ISCAS, Taipei, Taiwan, May 2009, pp Hiroo Sekiya (S 97 M 01) was born in Tokyo, Japan, on July 5, He received the B.E., M.E., and Ph.D. degrees in electrical engineering from Keio University, Yokohama, Japan, in 1996, 1998, and 2001, respectively. Since April 2001, he has been with Chiba University, Chiba, Japan, where he is currently an Assistant Professor with the Graduate School of Advanced Integration Science. From 2008 to 2010, he was a Visiting Scholar at the Department of Electrical Engineering, Wright State University, Dayton, OH. His research interests include high-frequency high-efficiency tuned power amplifiers, resonant dc/dc power converters, dc/ac inverters, and digital signal processing for wireless communication. Dr. Sekiya is a member of the Institute of Electronics, Information and Communication Engineers (IEICE), Japan, the Information Processing Society of Japan, the Society Information Theory and Its Application, Japan, and the Research Institute of Signal Processing, Japan. Natsumi Sagawa was born in Fukushima, Japan, on January 26, She received the B.E. degree from Chiba University, Chiba, Japan, in 2008, where she is currently working toward the M.E. degree in the Graduate School of Advanced Integration Science. Her research interests include high-frequency resonant dc/dc power converter and dc/ac inverter. Marian K. Kazimierczuk (M 91 SM 91 F 04) received the M.S., Ph.D., and D.Sci. degrees in electronics engineering from the Department of Electronics, Technical University of Warsaw, Warsaw, Poland, in 1971, 1978, and 1984, respectively. He was a Teaching and Research Assistant from 1972 to 1978 and an Assistant Professor from 1978 to 1984 with the Institute of Radio Electronics, Department of Electronics, Technical University of Warsaw. In 1984, he was a Project Engineer with Design Automation, Inc., Lexington, MA. From 1984 to 1985, he was a Visiting Professor at the Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg. Since 1985, he has been with the Department of Electrical Engineering, Wright State University, Dayton, OH, where he is currently a Professor. His research interests are in high-frequency high-efficiency switching-mode tuned power amplifiers, resonant and pulsewidth modulation dc/dc power converters, dc/ac inverters, high-frequency rectifiers, electronic ballasts, modeling and control of converters, high-frequency magnetics, and power semiconductor devices. He was an Associate Editor for the Journal of Circuits, Systems, and Computers. Prof. Kazimierczuk was the recipient of the IEEE Harrell V. Noble Award for his contributions to the fields of aerospace, industrial, and power electronics in He is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS (CAS) I: REGULAR PAPERS. He was a member of the Superconductivity Committee of the IEEE Power Electronics Society. He was the Chair of the CAS Technical Committee of Power Systems and Power Electronics Circuits in He is a member of Tau Beta Pi.