FEATURES DESCRIPTIO. LTC Bit, 100ksps, Sampling ADC APPLICATIO S TYPICAL APPLICATIO

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1 LTC6 6-Bit, ksps, Sampling ADC FEATRES Single V Supply Bipolar Input Range: ±V Power Dissipation: mw Typ Guaranteed No Missing Codes Sample Rate: ksps Integral Nonlinearity: ±.LSB Max Signal-to-Noise Ratio: 86dB Typ Operates with Internal or External Reference Internal Synchronized Clock Improved nd Source to ADS78 and AD976 8-Pin. PDIP, SSOP and SW Packages APPLICATIO S Industrial Process Control Multiplexed Data Acquisition Systems High Speed Data Acquisition for PCs Digital Signal Processing DESCRIPTIO The LTC 6 is a ksps, sampling 6-bit A/D converter that draws only mw (typical) from a single V supply. This easy-to-use device includes sample-andhold, precision reference, switched capacitor successive approximation A/D and trimmed internal clock. The LTC6 s input range is an industry standard ±V. Maximum DC specs include ±.LSB INL and 6-bits no missing codes over temperature. An external reference can be used if greater accuracy over temperature is needed. The ADC has a microprocessor compatible, 6-bit or two byte parallel output port. A convert start input and a data ready signal (BSY) ease connections to FIFOs, DSPs and microprocessors., LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATIO Low Power, khz, 6-Bit Sampling ADC on V Supply V. Typical INL Curve 8 7 V DIG V ANA µf.µf.. ±V INPT Ω.k V IN k k k 6-BIT SAMPLING ADC D TO D 6 TO TO 6-BIT OR BYTE PARALLEL BS INL (LSBs)....µF.µF CAP REF BFFER k AGND REFERENCE AGND DGND CONTROL LOGIC AND TIMING BSY CS R/C BYTE 6 TA 6 DIGITAL CONTROL SIGNALS CODE 6 TA 6fc

2 LTC6 ABSOLTE AXI RATI GS (Notes, ) W W W V ANA... 7V V DIG to V ANA....V V DIG... 7V Ground Voltage Difference DGND, AGND and AGND... ±.V Analog Inputs (Note ) V IN... ±V CAP... V ANA +.V to AGND.V REF...Indefinite Short to AGND Momentary Short to V ANA Digital Input Voltage (Note )... DGND.V to V Digital Output Voltage... V DGND.V to V DIG +.V Power Dissipation... mw Operating Ambient Temperature Range LTC6C... C to 7 C LTC6I... C to 8 C Storage Temperature Range... 6 C to C Lead Temperature (Soldering, sec)... C PACKAGE/ORDER I FOR V IN AGND REF CAP AGND D (MSB) 6 D 7 D 8 D 9 D D D9 D8 DGND N PACKAGE 8-LEAD PDIP LTC6ACG LTC6ACSW LTC6AIG LTC6AISW LTC6CG TOP VIEW G PACKAGE 8-LEAD PLASTIC SSOP T JMAX = C, θ JA = 9 C/W (G) T JMAX = C, θ JA = C/W (N) T JMAX = C, θ JA = C/W (SW) W 8 V DIG 7 V ANA 6 BSY CS R/C BYTE D D D 9 D 8 D 7 D 6 D6 D7 ORDER PART NMBER ATIO Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: Consult LTC Marketing for parts specified with wider operating temperature ranges. SW PACKAGE 8-LEAD PLASTIC SO WIDE LTC6CN LTC6CSW LTC6IG LTC6IN LTC6ISW CONVERTER CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. With external reference (Notes, 6). LTC6 LTC6A PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS Resolution 6 6 Bits No Missing Codes 6 Bits Transition Noise.. LSB Integral Linearity Error (Note 7) ± ± LSB Bipolar Zero Error Ext. Reference =.V (Note 8) ± ± mv Bipolar Zero Error Drift ± ± ppm/ C Full-Scale Error Drift ±7 ± ppm/ C Full-Scale Error Ext. Reference =.V (Notes, ) ±. ±. % Full-Scale Error Drift Ext. Reference =.V ± ± ppm/ C Power Supply Sensitivity V ANA = V DIG = V DD V DD = V ±% (Note 9) ±8 ±8 LSB 6fc

3 ANALOG INPT (Notes, ) LTC6 The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. (Note ) LTC6/LTC6A SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V IN Analog Input Range (Note 9).7V V ANA.V,.7V V DIG.V ± V C IN Analog Input Capacitance pf R IN Analog Input Impedance kω DYNAMIC ACCRACY W LTC6/LTC6A SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS S/(N + D) Signal-to-(Noise + Distortion) Ratio khz Input Signal (Note ) 87. db khz Input Signal 87 db khz, 6dB Input Signal db THD Total Harmonic Distortion khz Input Signal, First Harmonics db khz Input Signal, First Harmonics 9 db Peak Harmonic or Spurious Noise khz Input Signal db khz Input Signal 9 db Full-Power Bandwidth (Note ) 7 khz Aperture Delay ns Aperture Jitter Sufficient to Meet AC Specs Transient Response Full-Scale Step (Note 9) µs Overvoltage Recovery (Note 6) ns INTERNAL REFERENCE CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. (Note ) LTC6/LTC6A PARAMETER CONDITIONS MIN TYP MAX NITS V REF Output Voltage I OT =.7.. V V REF Output Tempco I OT = ± ppm/ C Internal Reference Source Current µa External Reference Voltage for Specified Linearity (Notes 9, )...7 V External Reference Current Drain Ext. Reference =.V (Note 9) µa CAP Output Voltage I OT =. V DIGITAL INPTS AND DIGITAL OTPTS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. (Note ) LTC6/LTC6A SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V IH High Level Input Voltage V DD =.V. V V IL Low Level Input Voltage V DD =.7V.8 V I IN Digital Input Current V IN = V to V DD ± µa C IN Digital Input Capacitance pf V OH High Level Output Voltage V DD =.7V I O = µa. V I O = µa. V 6fc

4 LTC6 DIGITAL INPTS AND DIGITAL OTPTS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. (Note ) LTC6/LTC6A SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OL Low Level Output Voltage V DD =.7V I O = 6µA. V I O =.6mA.. V I OZ Hi-Z Output Leakage D to D V OT = V to V DD, CS High ± µa C OZ Hi-Z Output Capacitance D to D CS High (Note 9) pf I SORCE Output Source Current V OT = V ma I SINK Output Sink Current V OT = V DD ma TIMING CHARACTERISTICS W The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. (Note ) LTC6/LTC6A SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS f SAMPLE(MAX) Maximum Sampling Frequency khz t CONV Conversion Time 8 µs t ACQ Acquisition Time µs t Convert Pulse Width (Note ) ns t Data Valid Delay After R/C (Note 9) 8 µs t BSY Delay from R/C C L = pf 6 ns t BSY Low 8 µs t BSY Delay After End of Conversion ns t 6 Aperture Delay ns t 7 Bus Relinquish Time 8 ns t 8 BSY Delay After Data Valid ns t 9 Previous Data Valid After R/C 7. µs t R/C to CS Setup Time (Notes 9, ) ns t Time Between Conversions µs t Bus Access and Byte Delay (Notes 9, ) 8 ns POWER REQIREMENTS W The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. (Note ) LTC6/LTC6A SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V DD Positive Supply Voltage (Notes 9, ).7. V I DD Positive Supply Current 6 ma P DIS Power Dissipation 8 mw Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note : All voltage values are with respect to ground with DGND, AGND and AGND wired together (unless otherwise noted). Note : When these pin voltages are taken below ground or above V ANA = V DIG = V DD, they will be clamped by internal diodes. This product can handle input currents of greater than ma below ground or above V DD without latch-up. Note : When these pin voltages are taken below ground, they will be clamped by internal diodes. This product can handle input currents of 9mA below ground without latchup. These pins are not clamped to V DD. Note : V DD = V, f SAMPLE = khz, t r = t f = ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a V IN input with respect to ground. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual end points of the transfer curve. The deviation is measured from the center of the quantization band. 6fc

5 LTC6 ELECTRICAL CHARACTERISTICS Note 8: Bipolar offset is the offset voltage measured from. LSB when the output code flickers between and. Note 9: Guaranteed by design, not subject to test. Note : Recommended operating conditions. Note : With CS low the falling R/C edge starts a conversion. If R/C returns high at a critical point during the conversion it can create small errors. For best results ensure that R/C returns high within µs after the start of the conversion. Note : As measured with fixed resistors shown in Figure. Adjustable to zero with external potentiometer. Note : Full-scale error is the worst-case of FS or +FS untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. Note : All specifications in db are referred to a full-scale ±V input. Note : Full-power bandwidth is defined as full-scale input frequency at which a signal-to-(noise + distortion) degrades to 6dB or bits of accuracy. Note 6: Recovers to specified performance after ( FS) input overvoltage. TYPICAL PERFORMANCE CHARACTERISTICS W SPPLY CRRENT (ma) Supply Current vs Supply Voltage f SAMPLE = khz.7... SPPLY VOLTAGE (V) 6 TPC POSITIVE SPPLY CRRENT (ma)..... Supply Current vs Temperature f SAMPLE = khz TEMPERATRE ( C) 7 6 TPC CHANGE IN CAP VOLTAGE (mv) Change in CAP Voltage vs Load Current LOAD CRRENT (ma) 6 TPC. Typical INL Curve. Typical DNL Curve Power Supply Feedthrough vs Ripple Frequency INL (LSBs) DNL (LSBs) POWER SPPLY FEEDTHROGH (db) CODE CODE 6 7 k k k RIPPLE FREQENCY (Hz) M 6 TPC 6 TPC 6 TPC6 6fc

6 LTC6 TYPICAL PERFORMANCE CHARACTERISTICS MAGNITDE (db) W LTC6 Nonaveraged 96 Point FFT Plot f SAMPLE = khz f IN = khz SINAD = 87.dB THD =.7dB FREQENCY (khz) 6 TPC7 9 SINAD vs Input Frequency 7 Total Harmonic Distortion vs Input Frequency SINAD (db) TOTAL HARMONIC DISTORTION (db) INPT FREQENCY (khz) INPT FREQENCY (khz) 6 TPC8 6 TPC9 PIN FNCTIONS 6 V IN (Pin ): Analog Input. Connect through a Ω resistor to the analog input. Full-scale input range is ±V. AGND (Pin ): Analog Ground. Tie to analog ground plane. REF (Pin ):.V Reference Output. Bypass with.µf tantalum capacitor. Can be driven with an external reference. CAP (Pin ): Reference Buffer Output. Bypass with.µf tantalum capacitor. AGND (Pin ): Analog Ground. Tie to analog ground plane. D to D8 (Pins 6 to ): Three-State Data Outputs. Hi-Z state when CS is high or when R/C is low. DGND (Pin ): Digital Ground. D7 to D (Pins to ): Three-State Data Outputs. Hi-Z state when CS is high or when R/C is low. BYTE (Pin ): Byte Select. With BYTE low, data will be output with Pin 6 (D) being the MSB and Pin (D) being the LSB. With BYTE high the upper eight bits and the lower eight bits will be switched. The MSB is output 6fc

7 LTC6 PIN FNCTIONS on Pin and bit 8 is output on Pin. Bit 7 is output on Pin 6 and the LSB is output on Pin. R/C (Pin ): Read/Convert Input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the hold state and starts a conversion. With CS low, a rising edge on R/C enables the output data bits. CS (Pin ): Chip Select. Internally OR d with R/C. With R/C low, a falling edge on CS will initiate a conversion. With R/C high, a falling edge on CS will enable the output data. TEST CIRCITS Load Circuit for Access Timing V BSY (Pin 6): Output Shows Converter Status. It is low when a conversion is in progress. Data valid on the rising edge of BSY. CS or R/C must be high when BSY rises or another conversion will start without time for signal acquisition. V ANA (Pin 7): V Analog Supply. Bypass to ground with a.µf ceramic and a µf tantalum capacitor. V DIG (Pin 8): V Digital Supply. Connect directly to Pin 7. Load Circuit for Output Float Delay V k k DBN DBN DBN DBN k C L C L k pf pf LTC6 TC LTC6 TC A. HI-Z TO V OH AND V OL TO V OH B. HI-Z TO V OL AND V OH TO V OL A. V OH TO HI-Z B. V OL TO HI-Z FNCTIONAL BLOCK DIAGRA W V IN k C SAMPLE k k C SAMPLE V ANA REF k.v REF ZEROING SWITCHES V DIG REF BF 6-BIT CAPACITIVE DAC + COMP CAP (.V) AGND AGND DGND INTERNAL CLOCK SCCESSIVE APPROXIMATION REGISTER CONTROL LOGIC 6 OTPT LATCHES D D CS R/C BYTE BSY LTC6 BD 6fc 7

8 LTC6 APPLICATIONS INFORMATION Conversion Details W The LTC6 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 6-bit or two byte parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and R/C inputs. At the start of conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During the conversion, the internal 6-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure, V IN is connected through the resistor divider to the sample-and-hold capacitor during the acquire phase and the comparator offset is nulled by the autozero switches. In this acquire phase, a minimum delay of µs will provide enough time for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the autozero switches open, putting the comparator into the compare mode. The input switch switches C SAMPLE to ground, injecting the analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output balances the V IN input charge. The SAR contents (a 6-bit data word) that represents the V IN are loaded into the 6-bit output latches. V IN R IN R IN SAMPLE HOLD C SAMPLE C DAC V DAC DAC SAMPLE + SI COMPARATOR S A R 6-BIT LATCH Driving the Analog Inputs The nominal input range for the LTC6 is ±V or (± V REF ) and the input is overvoltage protected to ±V. The input impedance is typically kω, therefore, it should be driven with a low impedance source. Wideband noise coupling into the input can be minimized by placing a pf capacitor at the input as shown in Figure. An NPO-type capacitor gives the lowest distortion. Place the capacitor as close to the device input pin as possible. If an amplifier is to be used to drive the input, care should be taken to select an amplifier with adequate accuracy, linearity and noise for the application. The following list is a summary of the op amps that are suitable for driving the LTC6. More detailed information is available in the Linear Technology data books and LinearView TM CD-ROM. A IN Ω pf.k V IN CAP Figure. Analog Input Filtering 6 F LT7 - Low noise precision amplifier..7ma supply current ±V to ±V supplies. Gain bandwidth product 8MHz. DC applications. LT97 - Low cost, low power precision amplifier. µa supply current. ±V to ±V supplies. Gain bandwidth product.7mhz. DC applications. LT7 - MHz video current feedback amplifier. ma supply current. ±V to ±V supplies. Low noise and low distortion. LT6-7MHz voltage feedback amplifier..8ma supply current. ±V to ±V supplies. Good AC/DC specs. LT6 - MHz voltage feedback amplifier. 6.mA supply current. Good AC/DC specs. LT6/LT6 - Dual and quad MHz voltage feedback amplifiers. 6.mA supply current per amplifier. Good AC/ DC specs. 6 F 8 Figure. LTC6 Simplified Equivalent Circuit LinearView is a trademark of Linear Technology Corporation 6fc

9 LTC6 APPLICATIONS INFORMATION Internal Voltage Reference W The LTC6 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to.v. The full-scale range of the ADC is equal to (± V REF ) or nominally ±V. The output of the reference is connected to the input of a unity-gain buffer through a k resistor (see Figure ). The input to the buffer or the output of the reference is available at REF (Pin ). The internal reference can be overdriven with an external reference if more accuracy is needed. The buffer output drives the internal DAC and is available at CAP (Pin ). The CAP pin can be used to drive a steady DC load of less than ma. Driving an AC load is not recommended because it can cause the performance of the converter to degrade. applied to V IN and R is adjusted until the output code is changing between and. Figure 6 shows the bipolar transfer characteristic of the LTC6. ±V INPT Ω % +.k %.µf +.µf Figure. ±V Input Without Trim V IN AGND REF CAP AGND LTC6 6 F REF (.V).µF CAP (.V).µF S S + k V ANA BANDGAP REFERENCE INTERNAL CAPACITOR DAC ±V INPT Ω %.k % V R k R k +.µf + 76k V IN AGND REF LTC6 CAP.µF AGND 6 F 6 F Figure. ±V Input with Offset and Gain Trim Figure. Internal or External Reference Source For minimum code transition noise the REF pin and the CAP pin should each be decoupled with a capacitor to filter wideband noise from the reference and the buffer (.µf tantalum). Offset and Gain Adjustments The LTC6 offset and full-scale errors have been trimmed at the factory with the external resistors shown in Figure. This allows for external adjustment of offset and full scale in applications where absolute accuracy is important. See Figure for the offset and gain trim circuit. First adjust the offset to zero by adjusting resistor R. Apply an input voltage of.6mv (.LSB) and adjust R so the code is changing between and. The gain error is trimmed by adjusting resistor R. An input voltage of 9.999V (+FS.LSB) is OTPT CODE FS/ BIPOLAR ZERO V LSB LSB INPT VOLTAGE (V) FS = V LSB = FS/66 FS/ LSB 6 F6 Figure 6. LTC6 Bipolar Transfer Characteristics DC Performance One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC 6fc 9

10 LTC6 APPLICATIONS INFORMATION W signal is applied to the input of the ADC and the resulting output codes are collected over a large number of conversions. For example in Figure 7 the distribution of output code is shown for a DC input that has been digitized times. The distribution is Gaussian and the RMS code transition is about LSB. CONT CODE 6 F7 Figure 7. Histogram for Conversions DIGITAL INTERFACE Internal Clock The ADC has an internal clock that is trimmed to achieve a typical conversion time of 7µs. No external adjustments are required and, with the typical acquisition time of µs, throughput performance of ksps is assured. Timing and Control Conversion start and data read are controlled by two digital inputs: CS and R/C. To start a conversion and put the sample-and-hold into the hold mode bring CS and R/C low for no less than ns. Once initiated it cannot be restarted until the conversion is complete. Converter status is indicated by the BSY output and this is low while the conversion is in progress. There are two modes of operation. The first mode is shown in Figure 8. The digital input R/C is used to control the start of conversion. CS is tied low. When R/C goes low the sample-and-hold goes into the hold mode and a conversion is started. BSY goes low and stays low during the conversion and will go back high after the conversion has been completed and the internal output shift registers have been updated. R/C should remain low for no less than ns. During the time R/C is low the digital outputs are in a Hi-Z state. R/C should be brought back high within µs after the start of the conversion to ensure that no errors occur in the digitized result. The second mode, shown in Figure 9, uses the CS signal to control the start of a conversion and the reading of the digital output. In this mode the R/C input signal should be brought low no less than ns before the falling edge of CS. The minimum pulse width for CS is ns. When CS falls, BSY goes low and will stay low until the end of the conversion. BSY will go high after the conversion has been completed. The new data is valid when CS is brought back low again to initiate R/C t t t t BSY t t 6 t MODE ACQIRE CONVERT ACQIRE CONVERT t CONV t ACQ t 9 DATA MODE PREVIOS DATA VALID PREVIOS HI-Z NOT VALID DATA HI-Z DATA VALID VALID DATA VALID t 7 t 8 6 F8 Figure 8. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low) 6fc

11 LTC6 APPLICATIONS INFORMATION W t t t t R/C t t CS t t BSY t 6 MODE ACQIRE CONVERT ACQIRE t CONV DATA BS HI-Z DATA VALID HI-Z t t 7 6 F9 Figure 9. sing CS to Control Conversion and Read Timing t t R/C CS BYTE PINS 6 TO HI-Z HIGH BYTE LOW BYTE HI-Z t t t 7 PINS TO HI-Z LOW BYTE HIGH BYTE HI-Z 6 F Figure. sing CS and BYTE to Control Data Bus Read Timing MAGNITDE (db) f SAMPLE = khz f IN = khz SINAD = 87.dB THD =.7dB FREQENCY (khz) 6 F Figure. LTC6 Nonaveraged 96 Point FFT Plot 6fc

12 LTC6 APPLICATIONS INFORMATION W a read. Again it is recommended that both R/C and CS return high within µs after the start of the conversion. Output Data The output data can be read as a 6-bit word or it can be read as two 8-bit bytes. The format of the output data is two s complement. The digital input pin BYTE is used to control the two byte read. With the BYTE pin low the first eight MSBs are output on the D to D8 pins and the eight LSBs are output on the D7 to D pins. When the BYTE pin is taken high the eight LSBs replace the eight MSBs (Figure ). Dynamic Performance FFT (Fast Fourier Transform) test techniques are used to test the ADC s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC s spectral content can be examined for frequencies outside the fundamental. Figure shows a typical LTC6 FFT plot which yields a SINAD of 87.dB and THD of db. Signal-to-Noise Ratio The Signal-to-Noise and Distortion Ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure shows a typical SINAD of 87.dB with a khz sampling rate and a khz input. Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = log V + V + V... + V N V where V is the RMS amplitude of the fundamental frequency and V through V N are the amplitudes of the second through Nth harmonics. Board Layout, Power Supplies and Decoupling Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC6, a printed circuit board is required. Layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by AGND. Figures through show a layout for a suggested evaluation circuit which will help obtain the best performance from the 6-bit ADC. Pay particular attention to the design of the analog and digital ground planes. The DGND pin of the LTC6 can be tied to the analog ground plane. Placing the bypass capacitor as close as possible to the power supply, the reference and reference buffer output is very important. Low impedance common returns for these bypass capacitors are essential to low noise operation of the ADC, and the foil width for these tracks should be as wide as possible. Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedance as much as possible. The digital output latches and the onboard sampling clock have been placed on the digital ground plane. The two ground planes are tied together at the power supply ground connection. 6fc

13 LTC6 APPLICATIONS INFORMATION W Figure. Component Side Silkscreen for the Suggested LTC6 Evaluation Circuit ANALOG GROND PLANE DIGITAL GROND PLANE ANALOG GROND PLANE Figure. Bottom Side Showing Analog Ground Plane Figure. Component Side Showing Separate Analog and Digital Ground Plane 6fc

14 LTC6 APPLICATIONS INFORMATION W V IN 7V TO V E GND E VIN VIN LT D6 GND MBR VKK VCC VDD + C6 µf V DIGITAL I.C. BYPASSING R6 C9.µF C.µF C.µF VCC C.µF C.µF C.µF C µf J A IN VKK NC INPT TEMP GND 9 LT9-. NC HEATER OT TRIM EXT INT C7 µf R8 Ω % VREF JP C.µF C6 pf C.µF C.µF R9.k % C.µF LTC6 D D D D D D D D D D D D D D D D D D9 D D8 D VIN Q AGND REF CAP AGND DGND BYTE D HC7 D D D D D D D6 D7 OC CLK 9 Q 8 Q 7 Q 6 Q Q Q6 Q7 A 7HC EXT_CLK J R7 8 MHz, OSC NA GND 9 OT VCC D 7HC CLR LOAD CLK ENT ENP R, k A B 6A 7HC CLK CEXT RCEXT Q Q D C B A 8 7 7HC6 E 7HC RCO QD QC QB QA EXT CLK INT JP VCC REVERSE BYTE NORNAL VCC JP V CC CS VCC JP VKK C7 µf C8.µF R/C CS BSY VANA VDIG D8 D7 D6 D D D D D D D8 D7 D6 D D D D D D B 7HC R K D D D D D D D6 D7 C PF HC7 D D D D D D D6 D7 OC CLK C 7HC 6 9 Q Q 8 Q 7 Q 6 Q Q Q6 Q7 GND Figure. LTC6 Suggested Evaluation Circuit Schematic R,.k D R,.k D R,.k D R,.k D R,.k D R,.k D R9,.k D9 R8,.k D R7,.k D7 R6,.k D6 R,.k D R,.k D R,.k D R,.k D R,.k D R,.k D D D D D D D D9 D8 D7 D6 D D D D D D D CLK GND GND JP LED ENABLE 6_7d.eps 6fc

15 LTC6 PACKAGE DESCRIPTION G Package 8-Lead Plastic SSOP (.mm) (Reference LTC DWG # -8-6). ± * (.9.) (.9.). ±..6 BSC RECOMMENDED SOLDER PAD LAYOT ** (.97.). (.79) 8.9. (..)..9 (..7) NOTE:. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS. DIMENSIONS ARE IN (INCHES). DRAWING NOT TO SCALE * DIMENSIONS DO NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.mm (.6") PER SIDE ** DIMENSIONS DO NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED.mm (.") PER SIDE.6 (.6) BSC..8 (.9.). (.) G8 SSOP 8 N Package 8-Lead PDIP (Narrow. Inch) (Reference LTC DWG # -8-).7* (.789) MAX ±.* (6.77 ±.8) (7.6 8.). ±. (. ±.7)..6 (..6).8. (..8) ( ). (.8) MIN. (.8) MIN. (.7) MIN NOTE: INCHES. DIMENSIONS ARE MILLIMETERS *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm). (.) BSC.8 ±. (.7 ±.76).6 (.6) TYP N8 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 6fc

16 LTC6 PACKAGE DESCRIPTION SW Package 8-Lead Plastic Small Outline (Wide. Inch) (Reference LTC DWG # -8-6). ±. TYP N. BSC. ± ( ) NOTE MIN. ±. N NOTE.9.9 (.7.6) N/ N/ RECOMMENDED SOLDER PAD LAYOT. (.7) RAD MIN.9.99 ( ) NOTE..9 (..77) 8 TYP.9. (.6.6) (.9.)..9. (.7) (.9.) NOTE BSC (.6.8) (.6.7) TYP NOTE: INCHES. DIMENSIONS IN (MILLIMETERS). DRAWING NOT TO SCALE. PIN IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANFACTRING OPTIONS. THE PART MAY BE SPPLIED WITH OR WITHOT ANY OF THE OPTIONS. THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED.6" (.mm).. (..) S8 (WIDE) RELATED PARTS PART NMBER DESCRIPTION COMMENTS LT 9-. Precision Bandgap Reference.% Max, ppm/ C Max LTC7/LTC77 Low Power -Bit, ksps ADCs mw Power Dissipation, Parallel/Byte Interface LTC Single V, -Bit,.Msps ADC mw Power Dissipation, 7dB SINAD LTC9 Low Power -Bit, 8ksps ADC True -Bit Linearity, 8.dB SINAD, mw Dissipation LT6-. Micropower Precision Series Reference.7% Max, ppm/ C Max, Only µa Supply Current LTC9/LTC98 Micropower -/8-Channel -Bit ADCs Serial I/O, V and V Versions 6 Linear Technology Corporation 6 McCarthy Blvd., Milpitas, CA 9-77 (8) -9 FAX: (8) fc LT 6 REV C PRINTED IN THE SA LINEAR TECHNOLOGY CORPORATION