DESCRIPTIO TYPICAL APPLICATIO. LTC Bit, 800ksps Sampling A/D Converter with Shutdown FEATURES APPLICATIO S

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1 FEATRES Sample Rate: 8ksps Power Dissipation: mw 8.dB S/(N + D) and 9dB THD No Missing Codes No Pipeline Delay Nap and Sleep Shutdown Modes Operates with.v Internal ppm/ C Reference or External Reference True Differential Inputs Reject Common Mode Noise MHz Full-Power Bandwidth Sampling Bipolar Input Range: ±.V 8-Pin SSOP and SO Packages APPLICATIO S Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems LTC9 -Bit, 8ksps Sampling A/D Converter with Shutdown DESCRIPTIO The LTC 9 is a µs, 8ksps, -bit sampling A/D converter that draws only mw from ±V supplies. This easy-to-use device includes a high dynamic range sample-and-hold and a precision reference. Two digitally selectable power shutdown modes provide flexibility for low power systems. The LTC9 has a full-scale input range of ±.V. Outstanding AC performance includes 8.dB S/(N + D) and 9dB THD with a khz input; 8dB S/(N + D) and 86dB THD at the Nyquist input frequency of khz. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its MHz bandwidth. The 6dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The ADC has a µp compatible, -bit parallel output port. There is no pipeline delay in the conversion results. A separate convert start input and data ready signal (BSY) ease connections to FIFOs, DSPs and microprocessors., LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by.s. Patents including 8. TYPICAL APPLICATIO V REF OTPT.V DIFFERENTIAL ANALOG INPT (.V TO.V) µf µf 8kHz, -Bit Sampling A/D Converter -BIT PARALLEL BS LTC9 +A IN AV DD A IN DV DD V REF V SS REFCOMP BSY AGND CS 6 D(MSB) CONVST 7 D RD 8 D SHDN 9 D D D9 D D8 D D7 D D6 D DGND D V µf µp CONTROL LINES V µf Effective Bits and Signal-to-(Noise + Distortion) vs Input Frequency EFFECTIVE BITS f SAMPLE = 8kHz k k k INPT FREQENCY (Hz) M M SIGNAL/(NOISE + DISTORTION) (db) 9 TA 9 TA

2 ABSOLTE AXI RATI GS W W W AV DD = V DD = DV DD (Notes, ) Supply Voltage (V DD )... 6V Negative Supply Voltage (V SS )... 6V Total Supply Voltage (V DD to V SS )... V Analog Input Voltage (Note )...(V SS.V) to (V DD +.V) Digital Input Voltage (Note )... (V SS.V) to V Digital Output Voltage... (V SS.V) to (V DD +.V) Power Dissipation... mw Operating Temperature Range LTC9C... C to 7 C LTC9I... C to 8 C Storage Temperature Range... 6 C to C Lead Temperature (Soldering, sec)... C W PACKAGE/ORDER I FOR ATIO +A IN A IN V REF REFCOMP AGND D(MSB) 6 D 7 D 8 D 9 D9 D8 D7 D6 DGND G PACKAGE 8-LEAD PLASTIC SSOP TOP VIEW 8 AV DD 7 DV DD 6 V SS BSY CS CONVST RD SHDN D 9 D 8 D 7 D 6 D D SW PACKAGE 8-LEAD PLASTIC SO T JMAX = C, θ JA = 9 C/W (G) T JMAX = C, θ JA = C/W (SW) ORDER PART NMBER LTC9ACG LTC9ACSW LTC9AIG LTC9AISW LTC9CG LTC9CSW LTC9IG LTC9ISW Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: Consult factory for Military grade parts. CO VERTER CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. With Internal Reference (Notes, 6) LTC9 LTC9A PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS Resolution (No Missing Codes) Bits Integral Linearity Error (Note 7) ±.8 ± ±.6 ±. LSB Differential Linearity Error ±.7 ±. ±. ± LSB Offset Error (Note 8) ± ± ± ± LSB Full-Scale Error Internal Reference ± ±6 ± ±6 LSB External Reference =.V ± ± LSB Full-Scale Tempco I OT(REF) = ± ± ppm/ C SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V IN Analog Input Range (Note 9).7V V DD.V,. V SS.7V ±. V I IN Analog Input Leakage Current CS = High ± µa C IN Analog Input Capacitance Between Conversions pf During Conversions pf t ACQ Sample-and-Hold Acquisition Time 9 ns t AP Sample-and-Hold Aperture Delay Time. ns t jitter Sample-and-Hold Aperture Delay Time Jitter ps RMS CMRR Analog Input Common Mode Rejection Ratio.V < ( A IN = A IN ) <.V 6 db A ALOG I PT The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. (Note )

3 DY A IC ACCRACY W The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. (Note ) LTC9 SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS S/(N + D) Signal-to-(Noise + Distortion) Ratio khz Input Signal db 9kHz Input Signal 8. db THD Total Harmonic Distortion khz Input Signal, First Harmonics 9 86 db 9kHz Input Signal, First Harmonics 86 db SFDR Spurious Free Dynamic Range khz Input Signal 9 86 db IMD Intermodulation Distortion f IN = 9.7kHz, f IN =.6kHz 86 db Full-Power Bandwidth MHz Full-Linear Bandwidth S/(N + D) 77dB MHz I TER AL REFERE CE CHARACTERISTICS PARAMETER CONDITIONS MIN TYP MAX NITS V REF Output Voltage I OT =.8.. V V REF Output Tempco I OT = ± ppm/ C V REF Line Regulation.7V V DD.V,. V SS.7V. LSB/V V REF Output Resistance.mA I OT.mA kω REFCOMP Output Voltage I OT =.6 V DIGITAL I PTS A D DIGITAL OTPTS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V IH High Level Input Voltage V DD =.V. V V IL Low Level Input Voltage V DD =.7V.8 V I IN Digital Input Current V IN = V to V DD ± µa C IN Digital Input Capacitance pf V OH High Level Output Voltage V DD =.7V I O = µa. V I O = µa. V V OL Low Level Output Voltage V DD =.7V I O = 6µA. V I O =.6mA.. V I OZ Hi-Z Output Leakage D to D V OT = V to V DD, CS High ± µa C OZ Hi-Z Output Capacitance D to D CS High (Note 9 ) pf I SORCE Output Source Current V OT = V ma I SINK Output Sink Current V OT = V DD ma POWER REQIRE E TS W (Note ) The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V DD Positive Supply Voltage (Note ).7. V V SS Negative Supply Voltage (Note ).7. V I DD Positive Supply Current ma Nap Mode SHDN = V, CS = V. ma Sleep Mode SHDN = V, CS = V µa I SS Negative Supply Current 9 ma Nap Mode SHDN = V, CS = V µa Sleep Mode SHDN = V, CS = V µa

4 POWER REQIRE E TS W The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS P DIS Power Dissipation mw Nap Mode SHDN = V, CS = V 7. mw Sleep Mode SHDN = V, CS = V. mw W TI I G CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS f SAMPLE(MAX) Maximum Sampling Frequency 8 khz t CONV Conversion Time 9 ns t ACQ Acquisition Time 9 ns t ACQ + CONV Acquisition + Conversion Time ns t CS to RD Setup Time (Notes 9, ) ns t CS to CONVST Setup Time (Notes 9, ) ns t CS to SHDN Setup Time (Notes 9, ) ns t SHDN to CONVST Wake-p Time (Note ) ns t CONVST Low Time (Notes, ) ns t 6 CONVST to BSY Delay C L = pf ns ns t 7 Data Ready Before BSY ns ns t 8 Delay Between Conversions (Note ) ns t 9 Wait Time RD After BSY (Note 9) ns t Data Access Time After RD C L = pf ns ns C L = pf ns ns t Bus Relinquish Time ns C T A 7 C ns C T A 8 C ns t RD Low Time t ns t CONVST High Time ns Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliabilty and lifetime. Note : All voltage values are with respect to ground with DGND and AGND wired together unless otherwise noted. Note : When these pin voltages are taken below V SS or above V DD, they will be clamped by internal diodes. This product can handle input currents greater than ma below V SS or above V DD without latchup. Note : When these pin voltages are taken below V SS, they will be clamped by internal diodes. This product can handle input currents greater than ma below V SS without latchup. These pins are not clamped to V DD. Note : V DD = V, V SS = V, f SAMPLE = 8kHz, t r = t f = ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended +A IN input with A IN grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from.lsb when the output code flickers between and. Note 9: Guaranteed by design, not subject to test. Note : Recommended operating conditions. Note : The falling edge of CONVST starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best performance ensure that CONVST returns high either within 6ns after the start of the conversion or after BSY rises.

5 TYPICAL PERFORMANCE CHARACTERISTICS W SIGNAL/(NOISE + DISTORTION) (db) S/(N + D) vs Input Frequency and Amplitude V IN = db V IN = db V IN = 6dB k k k M M INPT FREQENCY (Hz) SIGNAL-TO -NOISE RATIO (db) k Signal-to-Noise Ratio vs Input Frequency k k M M INPT FREQENCY (Hz) AMPLITDE (db BELOW THE FNDAMENTAL) Distortion vs Input Frequency THD 9 ND RD k k k M M INPT FREQENCY (Hz) 9 G 9 G 9 G SPRIOS-FREE DYNAMIC RANGE (db) k Spurious-Free Dynamic Range vs Input Frequency k M M INPT FREQENCY (Hz) 9 G AMPLITDE (db) 6 8 Intermodulation Distortion Plot f SAMPLE = 8kHz f IN = kHz f IN =.6kHz FREQENCY (khz) 9 G DNL ERROR (LSBs).... Differential Nonlinearity vs Output Code OTPT CODE 9 G6 INL ERROR (LSBs).... Integral Nonlinearity vs Output Code OTPT CODE AMPLITDE OF POWER SPPLY FEEDTHROGH (db) 6 7 Power Supply Feedthrough vs Ripple Frequency 8 V DD V SS 9 DGND k k k M M RIPPLE FREQENCY (Hz) COMMON MODE REJECTION (db) Input Common Mode Rejection vs Input Frequency INPT FREQENCY (Hz) 9 G7 9 G8 9 G9

6 PI F CTIO S +A IN (Pin ): ±.V Positive Analog Input. A IN (Pin ): ±.V Negative Analog Input. V REF (Pin ):.V Reference Output. Bypass to AGND with µf. REFCOMP (Pin ):.6V Reference Output. Bypass to AGND with µf tantalum in parallel with.µf or µf ceramic. AGND (Pin ): Analog Ground. D to D6 (Pins 6 to ): Three-State Data Outputs. The output format is s complement. DGND (Pin ): Digital Ground for Internal Logic. Tie to AGND. D to D (Pins to ): Three-State Data Outputs. The output format is s complement. SHDN (Pin ): Power Shutdown Input. Low selects shutdown. Shutdown mode selected by CS. CS = for nap mode and CS = for sleep mode. RD (Pin ): Read Input. This enables the output drivers when CS is low. CONVST (Pin ): Conversion Start Signal. This active low signal starts a conversion on its falling edge. CS (Pin ): Chip Select. The input must be low for the ADC to recognize CONVST and RD inputs. CS also sets the shutdown mode when SHDN goes low. CS and SHDN low select the quick wake-up nap mode. CS high and SHDN low select sleep mode. BSY (Pin ): The BSY output shows the converter status. It is low when a conversion is in progress. Data valid on the rising edge of BSY. V SS (Pin 6): V Negative Supply. Bypass to AGND with µf tantalum in parallel with.µf or µf ceramic. DV DD (Pin 7): V Positive Supply. Short to Pin 8. AV DD (Pin 8): V Positive Supply. Bypass to AGND with µf tantalum in parallel with.µf or µf ceramic. W F CTIO AL BLOCK DIAGRA C SAMPLE +A IN C SAMPLE AV DD A IN V REF k.v REF ZEROING SWITCHES DV DD V SS REF AMP -BIT CAPACITIVE DAC + COMP REFCOMP (.96V) AGND DGND SCCESSIVE APPROXIMATION REGISTER OTPT LATCHES D D INTERNAL CLOCK CONTROL LOGIC SHDN CONVST RD CS BSY 9 BD 6

7 TEST CIRCITS Load Circuits for Access Timing Load Circuits for Output Float Delay V V k k DBN DBN DBN DBN k C L C L k pf pf (A) Hi-Z TO V OH (B) Hi-Z TO V O (A) V OH TO Hi-Z (B) V OL TO Hi-Z 9 TC 9 TC CONVERSION DETAILS W The LTC9 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a -bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs (please refer to Digital Interface section for the data format). Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion, the successive approximation register (SAR) is reset. Once a conversion cycle has begun, it cannot be restarted. +A IN A IN SAMPLE SAMPLE +V DAC V DAC HOLD HOLD +C SAMPLE C SAMPLE +C DAC C DAC SAR ZEROING SWITCHES HOLD HOLD COMP Figure. Simplified Block Diagram + OTPT LATCHES 9 F D D During the conversion, the internal differential -bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure, the +A IN and A IN inputs are connected to the sample-and-hold capacitors (C SAMPLE ) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of ns will provide enough time for the sampleand-hold capacitors to acquire the analog signal. During the convert phase, the comparator zeroing switches open, putting the comparator into compare mode. The input switches the C SAMPLE capacitors to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the +A IN and A IN input charges. The SAR contents (a -bit data word) which represents the difference of +A IN and A IN are loaded into the -bit output latches. DYNAMIC PERFORMANCE The LTC9 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC s spectral content can be examined for 7

8 8 W frequencies outside the fundamental. Figure shows a typical LTC9 FFT plot. AMPLITDE (db) 6 8 f SAMPLE = 8kHz f IN = kHz SFDR = 98dB THD = 9.dB FREQENCY (khz) 9 Fa Figure a. LTC9 Nonaveraged, 96 Point FFT, Input Frequency = khz AMPLITDE (db) 6 8 f SAMPLE = 8kHz f IN = 7kHz SFDR = 88.dB SINAD = 8. FREQENCY (khz) 9 Fb Figure b. LTC9 Nonaveraged, 96 Point FFT, Input Frequency = 7kHz Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure shows a typical spectral content with a 8kHz sampling rate and a khz input. The dynamic performance is excellent for input frequencies up to and beyond the Nyquist limit of khz. Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D).76]/6. where N is the effective number of bits of resolution and S/(N + D) is expressed in db. At the maximum sampling rate of 8kHz, the LTC9 maintains near ideal ENOBs up to the Nyquist input frequency of khz (refer to Figure ). EFFECTIVE BITS f SAMPLE = 8kHz k k k INPT FREQENCY (Hz) 9 TA Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD Log V + V + = V + Vn V where V is the RMS amplitude of the fundamental frequency and V through Vn are the amplitudes of the second through nth harmonics. THD vs Input Frequency is shown in Figure. The LTC9 has good distortion performance up to the Nyquist frequency and beyond Figure. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency M M SIGNAL/(NOISE + DISTORTION) (db)

9 AMPLITDE (db BELOW THE FNDAMENTAL) W Figure. Distortion vs Input Frequency Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ±nfb, where m and n =,,,, etc. For example, the nd order IMD terms include AMPLITDE (db) THD 9 ND RD k k k M M INPT FREQENCY (Hz) G f SAMPLE = 8kHz f IN = kHz f IN =.6kHz FREQENCY (khz) 9 G Figure. Intermodulation Distortion Plot (fa + fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the nd order IMD products can be expressed by the following formula: IMD( fa + fb) = Log Amplitude at (fa + fb) Amplitude at fa Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by db for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 77dB (. effective bits). The LTC9 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter s Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The differential analog inputs of the LTC9 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the A IN input is grounded). The +A IN and A IN inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC9 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 6). For minimum acquisition time with high source impedance, a buffer amplifier should be used. The only requirement is 9

10 that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be ns for full throughput rate). ACQISITION TIME (µs)... W. SORCE RESISTANCE (kω) 9 F6 Figure 6. t ACQ vs Source Resistance Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of + and has a unity-gain bandwidth of MHz, then the output impedance at MHz should be less than Ω. The second requirement is that the closed-loop bandwidth must be greater than MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC9 will depend on the application. Generally applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC9. More detailed information is available in the Linear Technology databooks, the LinearView TM CD-ROM and on our web site at com. LinearView is a trademark of Linear Technology Corporation. LT : MHz unity-gain bandwidth voltage feedback amplifier. ±V to ±V supplies. Excellent DC specifications. LT: MHz video current feedback amplifier. ±V to ±V supplies, 6mA supply current. Low distortion at frequencies above khz. Low noise. Good for AC applications. LT7: MHz video current feedback amplifier. ±V to ±V supplies, ma supply current. Lowest distortion at frequencies above khz. Low noise. Best for AC applications. LT9/LT: Dual/quad MHz current feedback amplifiers. ±V to ±V supplies, 6mA supply current each amplifier. Low noise. Good AC specs. LT6: MHz voltage feedback amplifier. ±V to ±V supplies,.8ma supply current. Good AC and DC specs. LT6: 7MHz, V/µs op amps, 6.mA supply current. Good AC and DC specs. LT6/LT6: Dual and quad 7MHz, V/µs op amps. 6.mA supply current per amplifier. Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC9 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple -pole RC filter is sufficient for ANALOG INPT Ω pf µf +A IN A IN V REF Figure 7. RC Input Filter LTC9 REFCOMP AGND 9 F7

11 W many applications. For example, Figure 7 shows a pf capacitor from +A IN to ground and a Ω source resistor to limit the input bandwidth to.6mhz. The pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Input Range The ±.V input range of the LTC9 is optimized for low noise and low distortion. Most op amps also perform well over this same range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. Some applications may require other input ranges. The LTC9 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference and input circuitry and how they affect the input range. Internal Reference The LTC9 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to.v. It is connected internally to a reference amplifier and is available at V REF (Pin ) see Figure 8a. A V V IN LT9A-. V OT + ANALOG INPT µf.µf +A IN A IN V REF LTC9 REFCOMP AGND 9 F8b Figure 8b. sing the LT9-. as an External Reference k resistor is in series with the output so that it can be easily overdriven by an external reference or other circuitry, see Figure 8b. The reference amplifier gains the voltage at the V REF pin by.6 to create the required internal reference voltage. This provides buffering between the V REF pin and the high speed capacitive DAC. The reference amplifier compensation pin (REFCOMP, Pin ) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of µf or greater. For the best noise performance, a µf ceramic or µf tantalum in parallel with a.µf ceramic is recommended. The V REF pin can be driven with a DAC or other means shown in Figure 9. This is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. The filtering of the internal LTC9 reference amplifier will limit the bandwidth and settling time of this circuit. A settling time of ms should be allowed for after a reference adjustment..v V REF R k BANDGAP REFERENCE ANALOG INPT.V TO V DIFFERENTIAL +A IN A IN.6V REFCOMP REFERENCE AMP LTC.V TO V V REF LTC9 µf R k REFCOMP AGND R 6k LTC9 µf AGND 9 F9 9 F8a Figure 8a. LTC9 Reference Circuit Figure 9. Driving V REF with a DAC

12 Differential Inputs W The LTC9 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of +A IN ( A IN ) independent of the common mode voltage (see Figure a). The common mode rejection holds up to extremely high frequencies, see Figure a. The only requirement is that both inputs can not exceed the AV DD or AV SS power supply voltages. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar zero error (BZE) will vary. The change in BZE is typically less than.% of the common mode voltage. Dynamic performance is also affected by the common mode voltage. THD will degrade as the inputs approach either power supply rail, from 86dB with a common mode of V to 76dB with a common mode of.v or.v. Differential inputs allow greater flexibility for accepting different input ranges. Figure b shows a circuit that converts a V to V analog input signal with only an additional buffer that is not in the signal path. Full-Scale and Offset Adjustment Figure a shows the ideal input/output characteristics for the LTC9. The code transitions occur midway between successive integer LSB values (i.e., FS +.LSB, FS +.LSB, FS +.LSB,... FS.LSB, FS.LSB). The output is two s complement binary with LSB = FS ( FS)/68 = V/68 =.µv. In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure b shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset 8 COMMON MODE REJECTION (db) 7 6 INPT FREQENCY (Hz) 9 G9 OTPT CODE (FS LSB) FS LSB INPT VOLTAGE [+A IN ( A IN )] 9 Fa Figure a. CMRR vs Input Frequency Figure a. LTC9 Transfer Characteristics ±.V ANALOG INPT V TO V µf + +A IN A IN V REF LTC9 REFCOMP AGND R8 k + V R 7k µf R7 k R k R6 k.µf ANALOG INPT R Ω +A IN A IN LTC9 V REF REFCOMP AGND 9 Fb 9 F Figure b. Selectable V to V or ±.V Input Range Figure b. Offset and Full-Scale Adjust Circuit

13 W applied to the A IN input. For zero offset error, apply µv (i.e.,.lsb) at +A IN and adjust the offset at the A IN input until the output code flickers between and. For full-scale adjustment, an input voltage of.99v (FS/.LSBs) is applied to +A IN and R is adjusted until the output code flickers between and. BOARD LAYOT AND GRONDING Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC9, a printed circuit board with ground plane is required. Layout should ensure that digital and analog signal lines are separated as much as possible. Particular care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.The analog input should be screened by AGND. An analog ground plane separate from the logic system ground should be established under and around the ADC. Pin (AGND), Pin and Pin 9 (ADC s DGND) and all other analog grounds should be connected to this single analog ground point. The REFCOMP bypass capacitor and the DV DD bypass capacitor should also be connected to this analog ground plane. No other digital grounds should be connected to this analog ground plane. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC9 has differential inputs to minimize noise coupling. Common mode noise on the +A IN and A IN leads will be rejected by the input CMRR. The A IN input can be used as a ground sense for the +A IN input; the LTC9 will hold and convert the difference voltage between +A IN and A IN. The leads to +A IN (Pin ) and A IN (Pin ) should be kept as short as possible. In applications where this is not possible, the +A IN and A IN traces should be run side by side to equalize coupling. SPPLY BYPASSING High quality, low series resistance ceramic, µf bypass capacitors should be used at the V DD and REFCOMP pins as shown in the Typical Application on the fist page of this data sheet. Surface mount ceramic capacitors such as Murata GRMYV6Z6 provide excellent bypassing in a small board space. Alternatively, µf tantalum capacitors in parallel with.µf ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Example Layout Figures a, b, c and d show the schematic and layout of a suggested evaluation board. The layout demonstrates the proper use of decoupling capacitors and ground plane with a -layer printed circuit board. ANALOG INPT CIRCITRY + +A IN A IN LTC9 REFCOMP AGND V SS AV DD DV DD µf µf µf DGND DIGITAL SYSTEM ANALOG GROND PLANE 9 F Figure. Power Supply Grounding Practice

14 W +V IN J 7V TO V LT- V IN V OT V CC V CC R Ω GND TABGND D SS + C µf V GND J AGND DGND C6 pf JP V OT A + A J JP R7 k R8 k JP R6 Ω R Ω C pf V+ V J C7 pf C8 µf 6V C µf 6V CLK J7 R9 Ω 7A 7B HC HC V LOGIC JPC CS JPB RD JPA SHDN R M NOTES: NLESS OTHERWISE SPECIFIED. ALL RESISTOR VALES IN OHMS, /W, %. ALL CAPACITOR VALES IN µf, V, % AND IN pf, V, % C.µF C.µF V LOGIC + C µf V J 7V TO V 79L V IN IN OT GND D SS V SS C µf V V CC C.µF + 7 V SS V CC V SS C9 µf 6V LT6 6 8 C.µF C µf 6V A IN A IN V REF REFCOMP BSY CS CONVST RD SHDN AV DD DV DD V SS AGND DGND LTC9 D D D D D9 D8 D7 D6 D D D D D D B B B B B9 B8 B7 B6 B B B B B B B[:] B B B B B B B B B B B9 B8 B7 B E 7HC7 D D D D D D D6 D7 E 6 7HC7 D D D D D D D6 D7 Q Q Q Q Q Q Q6 Q7 Q Q Q Q Q Q Q6 Q DATA READY C.µF V LOGIC V CC 7G HC GND 7 7F HC 7C 6 HC R k C6 pf D D D D D D D D D D D9 D8 D7 D6 D[:] D 7E HC 7D 9 8 HC D D D D D D D6 D7 D8 D9 D D D D D D D D D D D6 D7 D8 D9 D D D D D RDY R.k R R R R R R6 R7 R8 R9 R R R R D D D D D D D6 D7 D8 D9 D D D D D D D D D D D6 D7 D8 D9 D D D D J6- J6- J6- J6- J6-9 J6- J6-7 J6-8 J6- J6-6 J6- J6- J6- J6- J6- J6-6 J6-7 J6-8 LED D JP D D D D D D6 D7 D8 D9 D D D D D RDY DGND DGND HEADER 8-PIN + Figure a. Suggested Evaluation Circuit Schematic DC SCHEM

15 W Figure b. Suggested Evaluation Circuit Board Component Side Silkscreen Figure c. Suggested Evaluation Circuit Board Component Side Layout

16 W Figure d. Suggested Evaluation Circuit Board Solder Side Layout DIGITAL INTERFACE The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion. Internal Clock The A/D converter has an internal clock that eliminates the need of synchronization between the external clock and the CS and RD signals found in other ADCs. The internal clock is factory trimmed to achieve a typical conversion time of.9µs and a maximum conversion time over the full operating temperature range of.µs. No external adjustments are required. The guaranteed maximum acquisition time is ns. In addition, a throughput time of.µs and a minimum sampling rate of 8ksps are guaranteed. Power Shutdown The LTC9 provides two power shutdown modes, nap and sleep, to save power during inactive periods. The nap 6 mode reduces the power by 9% and leaves only the digital logic and reference powered up. The wake-up time from nap to active is ns. In sleep mode, the reference is shut down and only a small current remains, about µa. Wake-up time from sleep mode is much slower since the reference circuit must power up and settle to.% for full -bit accuracy. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin ). The wake-up time is ms with the recommended µf capacitor. Shutdown is controlled by Pin (SHDN); the ADC is in shutdown when it is low. The shutdown mode is selected with Pin (CS); low selects nap. CS SHDN t 9 Fa Figure a. CS to SHDN Timing

17 SHDN CONVST W t 9 Fb Figure b. SHDN to CONVST Wake-p Timing Timing and Control Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A logic applied to the CONVST pin will start a conversion after the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BSY output. BSY is low during a conversion. Figures 6 through show several different modes of operation. In modes a and b (Figures 6 and 7), CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BSY rising edge. Mode a shows operation with a narrow logic low CONVST pulse. Mode b shows a narrow logic high CONVST pulse. In mode (Figure 8), CS is tied low. The falling edge of the CONVST signal again starts the conversion. Data outputs are in three-state until read by the MP with the RD signal. Mode can be used for operation with a shared MP databus. In slow memory and ROM modes (Figures 9 and ), CS is tied low and CONVST and RD are tied together. The MP starts the conversion and reads the output with the RD signal. Conversions are started by the MP or DSP (no external sample clock). In slow memory mode, the processor applies a logic low to RD (= CONVST), starting the conversion. BSY goes low, forcing the processor into a WAIT state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results appear on the data outputs; BSY goes high, releasing the processor and the processor takes RD (= CONVST) back high and reads the new conversion data. In ROM mode, the processor takes RD (= CONVST) low, starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result and initiate another conversion. CS RD t 9 F Figure. CS to CONVST Set-p Timing CS = RD = CONVST t CONV (SAMPLE N) t t 6 t 8 BSY t 7 DATA DATA (N ) DB TO DB DATA N DB TO DB DATA (N + ) DB TO DB 9 F6 Figure 6. Mode a. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) 7

18 W CS = RD = t CONV t 8 t t CONVST t 6 t 6 t 6 BSY t 7 DATA DATA (N ) DB TO DB DATA N DB TO DB DATA (N + ) DB TO DB 9 F7 Figure 7. Mode b. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) CS = (SAMPLE N) t CONV t t t 8 CONVST t 6 BSY t 9 t t RD t DATA DATA N DB TO DB 9 F8 Figure 8. Mode. CONVST Starts a Conversion. Data is Read by RD CS = t CONV t 8 RD = CONVST (SAMPLE N) t 6 t BSY t t 7 DATA DATA (N ) DB TO DB DATA N DB TO DB DATA N DB TO DB DATA (N + ) DB TO DB 9 F9 Figure 9. Slow Memory Mode Timing 8

19 APPLICATI O S I FOR W ATIO CS = t CONV t 8 RD = CONVST (SAMPLE N) t 6 t BSY t DATA DATA (N ) DB TO DB DATA N DB TO DB 9 F Figure. ROM Mode Timing PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. G Package 8-Lead Plastic SSOP (.9) (LTC DWG # -8-6) * (.97.7) (..) ** (..).7.99 (.68.78) 8.. (..9)..9 (..7) NOTE: DIMENSIONS ARE IN MILLIMETERS * DIMENSIONS DO NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.mm (.6") PER SIDE ** DIMENSIONS DO NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED.mm (.") PER SIDE.6 (.6) BSC..8 (..).. (..8) G8 SSOP 98 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 9

20 PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. SW Package 8-Lead Plastic Small Outline (Wide.) (LTC DWG # -8-6).697.7* ( ) NOTE.9.9 (.7.6).9.99** ( ) (..77).9. (.6.6).7. (.9.) 8 TYP.9. (.9.) NOTE.6. (.6.7). (.7) BSC..9 (.6.8) TYP NOTE:. PIN IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANFACTRING OPTIONS. THE PART MAY BE SPPLIED WITH OR WITHOT ANY OF THE OPTIONS * DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.6" (.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.. (..) S8 (WIDE) 98 RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC78/79 Single Supply, ksps/6ksps ADCs Low Power, V or ±V Supply LTC High Speed, Serial -Bit ADC ksps, Complete with Internal Reference, SO-8 Package LTC9 Low Power, -Bit, 8ksps Sampling ADC Best Dynamic Performance, f SAMPLE 8ksps, 8mW Dissipation LTC -Bit,.Msps Sampling ADC with Shutdown Best Dynamic Performance, THD = 8dB and SINAD = 7dB at Nyquist LTC Single V, -Bit.Msps ADC Single Supply, mw Dissipation LTC6 6-Bit ksps ADC ±.V Inputs, Pin Compatible with the LTC68 LTC6 Single V, 6-Bit ksps ADC Low Power, ±V Inputs LTC66 6-Bit ksps ADC ±V Inputs, Pin Compatible with the LTC6 LTC68 6-Bit ksps ADC ±.V Inputs, Pin Compatible with the LTC6 Linear Technology Corporation 6 McCarthy Blvd., Milpitas, CA 9-77 (8) -9 FAX: (8) -7 TELEX: LT 6 REV B PRINTED IN SA LINEAR TECHNOLOGY CORPORATION 997