Design of a QR Adapter with Improved Efficiency and Low Standby Power

Size: px

Start display at page:

Download "Design of a QR Adapter with Improved Efficiency and Low Standby Power"

Jonas Sutton
5 years ago
Views:

1 Design of a QR Adapter with Improved Efficiency and Low Standby Power

2 Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/ Step by Step Design Procedure 5. Performances of a 60 W Adapter Featuring Valley Lockout

3 Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/ Step by Step Design Procedure 5. Performances of a 60 W Adapter Featuring Valley Lockout

4 What is Quasi-Square Wave Resonance? MOSFET turns on when V DS (t) reaches its minimum value. Minimizes switching losses Improves the EMI signature valley MOSFET turns on in first valley MOSFET turns on in second valley

5 Quasi-Resonance Operation In DCM, V DS must drop from (V in + V reflect )to V in Because of L p -C lump network oscillations appear Oscillation half period: t = π L C x p lump Vin Lp Cout Rload 1 : N Vout V DS V in + V reflect Vin V in VDS SW Clump

6 A Need to Limit the Switching Frequency In a self-oscillating QR, F sw increases as the load decreases Higher losses at light load if F sw is not limited 2 methods to limit F sw : Frequency clamp with frequency foldback Changing valley with valley lockout

7 Frequency Clamp in QR Converters QR mode Second valley First valley In light load, frequency increases and hits clamp Multiple valley jumps Jumps occur at audible range Creates signal instability

8 Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/ Step by Step Design Procedure 5. Performances of a 60 W Adapter Featuring Valley Lockout

9 The Valley Lockout As the load decreases, the controller changes valley (1 st to 4 th valley in NCP1380) The controller stays locked in a valley until the output power changes significantly. No valley jumping noise Natural switching frequency limitation VCO mode SWITCHING FREQUENCY (Hz) th 3 rd 2 nd 1 st QR operation VCO mode OUTPUT POWER (W)

10 The Valley Lockout FB comparators select the valley and pass the information to a counter. The hysteresis of FB comparators locks the valley. 2 possible operating set points for a given FB voltage. VCO 4 th 3 rd 2 nd 1 st V FB (V) V FB increases (P OUT increases) V FB decreases (P OUT decreases)

11 Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/ Step by Step Design Procedure 5. Performances of a 60 W Adapter Featuring Valley Lockout

12 Operating modes: NCP1379/1380 Features QR current-mode with valley lockout for noise immunity VCO mode in light load for improved efficiency Protections Over power protection Soft-start Short circuit protection Over voltage protection Over temperature protection Brown-Out Rzcd2 Czcd Rzcd1 ZCD / OPP FB CS GND HV-bulk Ct NCP1380 C/D OVP/BO 7 Vcc 6 Rstart DRV Ct Cvcc Rbou Dovp Rbol Mass production: Q4 2009

13 QR Mode with Valley Lockout Operating principle: Locks the controller into a valley (up to the 4 th ) according to FB voltage. Peak current adjusts according to FB voltage to deliver the necessary output power. VCO mode 1.40E E+05 VCO mode Fsw (Pout) for a 60 W adapter QR operation 1.00E Fsw (Hz) 8.00E E E E E+00 4 th 3 rd 2 nd Pout (W) 1 st Advantages Solves the valley jumping instability in QR converters Achieves higher min F sw and lower max F sw than in traditional QR converters Reduce the transformer size

14 VCO Mode Occurs when V FB < 0.8 V (P out decreasing) or V FB < 1.4 V (P out increasing) Fixed peak current (17.5% of I pk,max ), variable frequency set by the FB loop. I pk max Constant peak current (17.5% of I pk max) F P out1 F P out2 P out1 > P out2

15 Combined ZCD and OPP Zero-Crossing Detection (ZCD) and Over Power Protection (OPP) are achieved by reading the Aux. winding voltage ZCD function used during the off-time of MOSFET (positive voltage). OPP function used during the on-time of MOSFET (negative voltage) Rzcd 1 Aux Ropu Ropl ZCD/OPP 1 ESD protection + CS 0.8 V + Vopp 0.8 V + - IpFlag 0 V 50 mv V ZCD + Possible restarts for ZCD V OPP - Demag Vth DRV leakage blanking Tblank V DRV 2

16 NCP1380 Versions 4 versions of NCP1380: A, B, C and D OTP OVP BO Auto-Recovery Over current protection Latched Over current protection NCP1380 / A X X X NCP1380 / B X X X NCP1380 / C X X X NCP1380 / D X X X OTP: Over Temperature Protection OVP: Over Voltage Protection BO: Bown-Out

17 Short-Circuit Protection Internal 80 ms timer for short-circuit validation. Additional CS comparator with reduced LEB to detect winding short-circuit. V CS(stop) = 1.5 * V ILIMIT S Q Q DRV R CS LEB1 + PWMreset Rsense FB/4 - Down ZCD/OPP OPP IpFlag Up TIMER Reset Stop controller Laux LEB2 V ILIMIT + CsStop grand reset - V CS(stop)

18 Short-Circuit Protection (A and C versions) A and C versions: the fault is latched. V CC is pulled down to 5 V and waits for ac removal. S Q DRV Q Vdd R aux latch VCC management Vcc CS after LEB1 + FB/4 V ILIMIT + V OPP CS after LEB PWMreset IpFlag CSstop Down Up CSstop TIMER Reset S Q Q fault grand reset VCCstop SCR delatches when I CC < ICC LATCH - t LEB2 < t LEB1 V CS(stop) grand reset R

Short Circuit Protection (B and D) Auto-recovery short circuit protection: the controller tries to restart Auto-recovery imposes a low burst in fault mode.

19 Short Circuit Protection (B and D) Auto-recovery short circuit protection: the controller tries to restart Auto-recovery imposes a low burst in fault mode. Low average input power in fault condition S Q Q to DRV stage Vdd aux R VCC management Vcc CS after LEB1 FB/4 V ILIMIT + V OPP PWMreset IpFlag Down Up grand reset TIMER Reset fault grand reset VCCstop V CC CS after LEB2 + CSstop V DS V CS(stop) - t LEB2 < t LEB1

20 Fault Pin Combinations OVP / OTP NCP1380 A & B versions V Fault OVP / BO NCP1380 C & D versions, NCP1379 V Fault Latch! Latch! OK OK Latch! time BO time OVP and OTP or OVP and BO combined on one pin. Less external components needed.

21 Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/ Step by Step Design Procedure 5. Performances of a 60 W Adapter Featuring Valley Lockout

22 Step by Step Design Procedure Calculating the QR transformer Predicting the switching frequency Implementing Over Power Compensation Improving the efficiency at light load with the VCO mode Choosing the startup resistors Implementing synchronous rectification

23 Design Example Power supply specification: V out = 19 V P out = 60 W F sw,min = 45 khz (at V in = 100 Vdc) 600 V MOSFET V in = 85 ~ 265 Vrms Standby power consumption < Vrms Vbulk T1.. Vout Gnd

24 Turns Ratio Calculation Derate maximum MOSFET BV dss : V = BV k ds, max dss D k D : derating factor For a maximum bulk voltage, select the clamping voltage: BV dss V ds,max V os 15% derating V = V V V clamp ds, max in, max os V reflect V clamp V os : diode overshoot V bulk,max Deduce turns ratio: N ps N s = = N p k ( V + V ) c out f V clamp k c : clamping coef. k c = V clamp / V reflect )

25 How to Choose k c k c choice dependant of L leak (leakage inductance of the transformer) k c value can be chosen to equilibrate MOS conduction losses and clamping resistor losses. 3 P Rclamp 600-V MOSFET 2 P V in,min P loss (W) 1 P tot 2.5 W k leak =0.01 k leak =0.008 k leak =0.005 P P Rclamp Pout kc = kleak η kc 1 2 4P out 1 kc = Rdson + 3η V, V, BV k V, V MOS, on k c in min in min dss D in max os Curves plotted for: R dson = 0.77 Ω at T j = 110 C P out = 60 W V in,min = 100 Vdc

26 Primary Peak Current and Inductance 1 2 Pout = LpriIpri, peak Fswη 2 DCM I pri,peak 0 t on t off t v t on t off t v T I L I L N pri, peak pri pri, peak pri ps sw = + +π LpriClump Vin, min Vout + Vf C oss contribution alone. I pri, peak P 1 N 2P C F out = π η Vin,min Vout V + f η ps out lump sw L pri = I 2P out 2 pri, peak F η sw

27 RMS Current Calculate maximum duty-cycle at maximum P out and minimum V in : d max = I pri, peak V L in, min pri F sw, min Deduce primary and secondary RMS current value: I = I pri, rms pri, peak d 3 max I sec, rms = I pri, peak N ps 1 d 3 max I pri,rms and I sec,rms Losses calculation

28 Design Example Based on equations from slides 11 to 14: Turns ratio: N ps kc ( Vout + Vf ) 1.3 ( ) = = Nps 0.25 B k V V Vdss D in, max os Peak current: Inductance: Max. duty-cycle: I pri, peak 2P 1 N 2P C F out = + + π η Vin,min Vout V + f η ps out lump sw p 45k = + + π Ipri, peak = 3.32 A P 2 60 Lpri = = L pri = 285µH I F k 0.85 out 2 2 pri, peak swη I L µ d = F = 45 k d = 0.43 pri, peak pri max sw, min max Vin, min 100 dmax 0.43 Primary rms current: Ipri, rms = Ipri, peak = 3.32 Ipri, rms = 1.26A 3 3 Secondary rms current: I 1 d I = = I = 5.8 A pri, peak max sec, rms sec, rms N ps

29 Predicting the Switching Frequency The controller changes valley as the load decreases. => How can we predict the switching frequency evolution as the load varies? Depending upon the power increase or decrease, the FB levels at which the controller changes valley are different => valley lockout

30 Predicting the Switching Frequency Knowing the FB threshold values, we can calculate F sw evolution and the corresponding P out. F sw 1 = V t 1 N + V L + + ( 1+ 2n) π L C FB prop ps in, dc 4 p p lump Rsense Lp Vin, dc Vout + Vf P 1 L V V t F FB prop out = p + in, dc sw 2 4Rsense L p 2 η Replace V FB by the valley thresholds values in the previous slide

31 Predicting the Switching Frequency Calculate by hand (using the previous equations) or use the Mathcad spreadsheet to deduce the maxima of the switching frequency => EMI khz 93 khz 90 khz 95 khz sw ve sus ou V N F sw (Hz) VCO mode 4 th 3 rd 4 th 2 nd 3 rd 1 st 2 nd 1 st VCO mode P out (W) P out decreases P out increases

32 VCO Mode The switching frequency is set by the end of charge of C t capacitor The end of charge of C t capacitor is controlled by the FB loop Vdd Load FB Rpullup Enable VCO mode Vdd 6.5-(10/3)Vfb VCO Ct ICt V FBth - + V Ct Controlled by FB loop C t Ct discharge DRV Q S Q R CS comparator (Timing capacitor voltage)

33 4 th Valley to VCO Mode Transition Output load slightly decreases: Load V FB 1.4 V 0.8 V V FBth T sw2 T sw1 4 th valley VCO mode

34 How to Calculate C t Capacitor? Switching frequency at the end of the 4 th valley operation (V FB = 0.8 V): T 0.8 t V 2 L 1 N L C in, max ps sw, 4th VCO = + prop p + + 7π p OSS 4Rsense L p Vin, max 2 Vout + V f T sw gap between 4 th valley and VCO mode must not exceed 10 µs (based on lab experiments) for V FB = 1.4 V (hysteresis): T T µs sw, VCO = sw, 4th VCO + 10 The relationship between V FB and V Ct is: V Ct C = t I T Ct sw, VCO 1.83 ( ) = 6.5 (10 / 3) V = / = 1.83V FB

35 C t Design Example Switching frequency at the end of the 4 th valley operation : Tsw, 4th VCO = + 300n 285µ 7π 285µ 250 p µ = 10.7 µs T sw gap between 4 th valley and VCO mode must not exceed 10 µs (based on lab experiments): Tsw, VCO = T sw, 4th VCO + 10 µs = 10.7µ + 10µ = 20.7 µs The timing capacitor value is: C t ICtT sw, VCO 20µ 20.7µ = = = pf Finally, we choose C t = 200 pf

36 OPP: How it Works? L aux with flyback polarity swings to NV IN during the on time. Adjust amount of OPP voltage with (R zcd +R opu ) // R opl. V CS,max = 0.8 V + V OPP The diode bypass R opu during the off-time for optimum zero-crossing detection. Rzcd Aux Ropu Ropl ZCD/OPP 1 ESD protection + CS 0.8 V + Vopp 0.8 V + - IpFlag Peak current set point 100% + 60% - Demag Vth leakage blanking DRV Tblank 370 V IN (V)

37 OPP Amount Needed for the Design Because of the propagation delay, at high line: I The switching frequency is: T I L 1 N L C P 0.8 = + V pk ( high) in, max Rsense ps sw( high) = pk ( high) p + + π p lump Vin, max 2 Vout + V f 1 1 = L I 2 T 2 out( high) p pk ( high) t 2 prop The power capability at high line is: L sw( high) p η I = = 4.32 A pk ( high) T ( ) sw high = + + π = 19.5 µs P 1 1 = = 116W out( high) 6

38 Amount of OPP Voltage Needed Limit the output power to P out(limit) = 70 W at high line. What is the peak current I pk(limit) corresponding to P out(limit)? I pk ( limit) = L 1 + N + L 1 + N 2 L η π L C L η ps 2 ps p p p p lump Vin( max), dc Vout + V f Vin ( max), dc Vout + V f Pout( limit) P p out( limit) 2 I pk ( limit) µ µ + + ( 285µ ) + 2 π 285µ 250p = = 2.67 A 285µ Amount of OPP voltage needed: V OPP I = I pk ( limit) pk ( max) VOPP 2.67 = = 300 mv 4.32

39 Calculating the OPP Resistors The amount of OPP voltage needed to limit P out to 70 W is : V OPP = 300 mv Resistor divider law: R + R N V V = R V opu zcd p, aux IN OPP opl OPP Rzcd Ropu ZCD/OPP 1 R opu + Rzcd = = R 0.3 opl 224 Aux Ropl We choose: R opl = 1 kω and R zcd = 1 kω R = 221R R opu opl zcd Ropu = 223kΩ

40 Why is the OPP Non Dissipative? Input voltage information given by auxiliary winding In light load: VCO mode => T sw expands, thus the average current in the resistor bridge decreases 1 t 1 toff I = N V + V + V ( ) on bridge, avg p, aux IN CC f Rzcd + Ropu + Ropl Tsw Ropu + Ropl Tsw Previous example: R opu = 220 kω, R opl = 1 kω, R zcd = 1 kω At light load (P out = 4 W), t on = 1.2 µs, t off = 3.6 µs, T sw = 40 µs 1 1.2µ 1 3.6µ I bridge, mean = = 15 µa 220k+ 1k+ 1k 40µ 220k+ 1k 40µ

41 Startup Network Bulk I1 I1 D4 D3 Rstartup Rstartup/3.14 Vcc D1 Vcc D2 D6 D5 CVcc Laux CVcc Laux Classical configuration Improved startup dissipation The startup resistor can either be connected: To the bulk capacitor with R startup To the half-wave for a similar charging current, take R startup /π

Startup Capacitor Calculation C Vcc calculated to allow the power supply to close the loop before V CC falls below V CC(off) C Vcc = ( + ) I Q F t CC3A g sw reg V CC( on) V CC(off) ( ) 2.

42 Startup Capacitor Calculation C Vcc calculated to allow the power supply to close the loop before V CC falls below V CC(off) C Vcc = ( + ) I Q F t CC3A g sw reg V CC( on) V CC(off) ( ) 2.4m+ 17n m C Vcc = = 3.9 µf 17 9 We choose C Vcc = 4.7 µf V CC t startup t reg Needed startup current to charge C Vcc : I Cvcc = V CC( on) t C startup Vcc µ I Cvcc = = 28.5µA 2.8 t reg

43 Startup Resistor Calculation Bulk capacitor connection Resistor calculation: Vin, min 2 Rstartup = I + I Rstartup P startup = Cvcc CC( start) Power dissipation: Pstartup 85 2 = = 2.76 MΩ 28.5µ + 15µ ( V ) 2, 2 V in max CC R startup ( ) 2 = = 55mW 2.68M Half wave connection Resistor calculation: R P startup Rstartup startup = I V Cvcc V = in, min π + I in, max 2 π R 2 CC( start) 85 2 π = = 880kΩ 28.5µ + 15µ Power dissipation: Pstartup startup V ( π 16) 2 CC = = 16 mw 880k 2 Half wave connection saves 39 mw!

44 Synchronous Rectification High rms currents in secondary side increased losses in the output diode. Replace the diode with a MOSFET featuring a very low R DS(on). + Increased efficiency - Degraded light load and standby power consumption Vout.. C out Q sync Gnd

45 Losses in the Sync. Rect. Switch PQsync = PON + PQdiode Body diode conduction losses PQdiode = Vf IoutFswtdelay Low if t delay small Body diode conducts before the MOSFET is turned-on. No switching losses MOSFET conduction losses P = R I 2 ON DS ( on) 120 sec, rms.. t delay Vout C out R load Q sync Gnd Losses in the Sync. Rect. switch are mainly conduction losses.

46 Choosing the Sync. Rect. MOSFET Target around 1 W conduction losses in Sync. Rect. switch to avoid using an heatsink. R DSon120 = I 1W 2 sec, RMS V out = 19 V F sw,min = 45 khz Universal mains P loss (W) R DSon110 = 70 mω MBR20H150 R DSon110 = 50 mω R DSon110 = 30 mω I out (A)

47 60 W QR Sync. Rect. Calculations Body diode losses: P = V I F t = n P Qdiode f out sw delay Qdiode = 7 mw MOSFET losses: P = R ( ) I, = 30m 5.8 P 2 2 ON DS on 120 sec rms ON = 1W Total Sync. Rect. switch losses: PQsync = W Losses into the MBR20200 diode: 2.6 W Power loss saving: 1.6 W

48 Agenda 1. Quasi-Resonance (QR) Generalities 2. The valley lockout technique 3. The NCP1379/ Step by step design procedure 5. Performances of a 60 W adapter featuring valley lockout

49 60 W Demo Board Schematic C1 2.2n R4 18k R11 18k X18 KBU4K + R18 1k Rx 10 TO-220 L3 2.2u Vout L1 IN C18 100n 10 mh 2 A - C14 100u R1 240k D4 1N X1 DIP8 8 D6 1N967 R2 1500k R6 1200k D1 1N4937 D5 1N4937 C13 100u... T1 D2 MBR20H150 C5a 680uF 35V C5b 680uF 35V C15 2.2nF Type = Y1 R9 1k C7 100uF 25V Gnd R5 27k Gnd R12 1Meg R19 1Meg R13 1Meg C6 22p D8 1N4148 R14 1k 2 3 R29 1k D7 1N4148 R16 10 D3 1N4148 M1 IPA60R385 R15 1k C10 47n R7 39k X2 C9 330nF C5 1n C8 220p C4 200p C17 10n X4 NTC C11 4.7u Q1 BC857 R3 47k R R X5 TL431_G R8 10k C20 100n Gnd NCP1380B in a 19 V, 60 W adapter

50 Startup Startup resistor connected to the bulk rail (R startup = 2.7 MΩ) T startup = 2.68 s Startup resistor connected to the half-wave (R startup = 910 kω) T startup = 2.1 s V CC V CC

51 Transient Load Step Load step: 3% to 100% of output load with a slew rate of 1 A / µs V in = 230 Vrms The overshoot / undershoot is 1% of the nominal value of V out

52 Short-Circuit V CC(off) V CC V DRV A short-circuit is made at the board output. The circuit pulses with a low burst (5%) The measured averaged input power is: P in = mw for V in = 230 Vrms

53 Efficiency 115 Vrms 230 Vrms P out (W) P out (%) P in (W) Eff. (%) P out (W) P out (%) P in (W) Eff. (%) Average efficiency (25, 50, 75, 100% of P out,max ): 87.9% Average efficiency (25, 50, 75, 100% of P out,max ): 87.7%

54 Improving the No Load Consumption At very low output load, the TL431 bias is removed using a special circuit: L3 2.2u Vout.. D2 MBR20H150 C5a 680uF 35V C5b 680uF 35V C7 100uF 25V Gnd C15 2.2nF Type = Y1 R9 1k TL431 bias suppresion circuit C10 47n Gnd R5 27k R7 39k X5 TL431_G R8 10k Gnd

55 No Load Consumption R startup connected to the bulk rail: Without TL431 bias: P out = 0 W 115 Vrms P in = 60 mw 230 Vrms P in = 98 mw With TL431 bias: P out = 0 W 115 Vrms P in = 98 mw 230 Vrms P in = 128 mw 3 MΩ resistor to discharge X2 capacitor included

56 No Load Consumption R startup connected to the half wave: Without TL431 bias, R startup = 1.1 MΩ (T startup = Vrms) P out = 0 W 115 Vrms P in = 55 mw 230 Vrms P in = 90 mw 3 MΩ resistor to discharge X2 capacitor included

57 Synchronous Rectification Schematic T1. L3 0.5u Vout IRFS4321 M3 C5a 680µF 35V C5b 680µF 35V C7 100uF 16V Gnd C15 2.2nF Gnd R28 10 R10 75 D2 1N X1 DIP4302 Sync DRV R9 TL431 and NCP4302 1k bias suppression R5 TL431 and NCP4302 circuit 27k Vcc 8 3 C10 47n R7 39k bias removed at light load. 2 Trig 4 5 Dlyadj Gnd 6 R30 15k R31 110k R8 10k Gnd

58 Efficiency and No Load Consumption 115 Vrms 230 Vrms P out (W) P out (%) P in (W) Eff. (%) P out (W) P out (%) P in (W) Eff. (%) Average efficiency (25, 50, 75, 100% of P out,max ): 89.5% Average efficiency (25, 50, 75, 100% of P out,max ): 89.1% No load consumption: 115 Vrms 230 Vrms P out = 0 W P in = 62 mw P in = 107 mw

59 Conclusion The valley lockout technique allows to solve the valley jumping problem in QR power supplies. NCP1380, NCP1379 features: QR current-mode with valley lockout for noise immunity for high load. VCO mode in light load for improved efficiency. OPP, OVP, BO, OTP, soft-start for building safe power supplies A complete design method has been presented. It is possible to achieve standby power consumption below 100 mw at 230 Vrms with the NCP1380. Good efficiency at light load with Sync. Rect if the bias of the TL431 and the Sync. Rec. controller is removed. Mathcad spreadsheet and simulations models available.

60 For More Information View the extensive portfolio of power management products from ON Semiconductor at View reference designs, design notes, and other material supporting the design of highly efficient power supplies at

Design of a QR Adapter with Improved Efficiency and Low Standby Power

Design of a QR Adapter with Improved Efficiency and Low Standby Power Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/1380 4. Step by Step Design Procedure 5.