FULL RECONFIGURABLE INTERLEAVER ARCHITECTURE FOR HIGH-PERFORMANCE SDR APPLICATIONS

Transcription

1 SDR'10 Sesson 5G- 6 FULL RECONFIGURABLE INTERLEAVER ARCHITECTURE FOR HIGH-PERFORMANCE SDR APPLICATIONS Renaud Pacalet (Telecom-Parstech, LabSoC, Sopha-Antpols, France; renaud.pacalet@telecom-parstech.fr); Jar Gonzalez-Pna (Telecom-Parstech, LabSoC, Sopha-Antpols, France; jar@telecom-parstech.fr). ABSTRACT Ths paper presents an nterleaver / denterleaver archtecture that meets all the requrements for complex SDR applcatons, bascally, t offers enough flexblty to mplement about any nterleavng method. Ths archtecture allows to run several nterleavng processes concurrently, ether wth the same method or wth dfferent ones, enablng hgh performance mult-rado applcatons wth the same hardware. Ths archtecture ntegrates the nterleavng altogether wth the rate matchng and the frame equalzaton two closely related processng, mprovng the overall system s performance. Whle the reconfgurable nterleaver can be shared among several steps of the communcatons process, t would be very neffcent to use t for the nternal nterleavng of turbo codng or decodng. It would requre a large communcaton bandwdth between the nterleaver and the channel coder / decoder. Ths paper also dscusses the mplementaton of two hghly optmzed nterleaver archtectures for the specfc requrements of turbo codng modules of LTE and UMTS standards. 1. INTRODUCTION It s wdely accepted that future wreless communcatons devces wll be based n Software Defned Rado Platforms (6),(8), Rado Platforms composed of shared hardware and software modules, all of them beng confgurable enough to support dfferent standards. Ths paper presents three nterleaver archtectures: a reconfgurable one that s capable of mplementng any nterleavng method, and two other whch are hghly optmzed for the nternal nterleavng of the channel turbo codng / decodng modules of LTE and UMTS standards. As the nterleavng process has a drect mpact on the performance of the system, many papers have been wrtten that evaluate performance of dfferent nterleavng methods (5), The research leadng to these results has receved fundng from the European Communty s Seventh Framework Programme (FP7/ ) under grant agreement SACRA n (9), (10), (12). In contrast, few papers are focused on nterleaver archtectures for SDR applcatons. (4), (11) and (14) are examples of dual-mode nterleaver archtectures, whch are suffcent for systems targetng standards wth smlar nterleavng methods, but not for real SDR and CR applcatons. Our reconfgurable nterleaver / denterleaver module also mplements rate-matchng and frame-equalzaton wthn the same hardware. To our knowledge, no other prevous archtecture proposed ths, whch n fact ncreases not only the performance of the nterleaver tself, but also the overall system performance. The paper s organzed as follows: Secton II descrbes the functonalty and archtecture of our full reconfgurable nterleaver. Secton III presents the optmzed core of LTE s nner nterleaver. The secton IV presents the optmzed core for UMTS nner nterleaver. The cores are compared to other mplementatons n secton V. Secton VI concludes. 2. FULL RECONFIGURABLE INTERLEAVER As llustrated by fgure 1, our fully reconfgurable nterleavng core uses three nternal mult-port memores: an nput buffer X, an output buffer Y and a permutaton buffer P, whch holds the table that defnes the permutaton functon (). The basc operaton mode s straghtforward: entres of the permutaton table are ponters to nput buffer entres; durng executon the permutaton table stored n P s parsed, one entry at a tme, and the ponted nput sample X[P []] s coped n the output buffer: Y [] = X[P []]. In the presented mplementaton, the nput and output buffers are 8 bts wde wth length of 2 16 = The P buffer s 16 bts wde, allowng to address the whole 64k samples from nput buffer X. Ths memory confguraton exemplfes the requrements of a worst case scenaro, and can be changed accordng to the partcular requrements of a gven applcaton, wthout alterng the functonalty of the core. For systems targetng only one or two communcatons standards, and assumng ther nterleavng functons are structured ones, t s lkely that more effcent archtectures exst, both n terms of slcon area and power consumpton: whle nput and output buffers can usually not be avoded n Proceedngs of the SDR 10 Techncal Conference and Product Exposton, Copyrght 2010 Wreless Innovaton Forum, Inc. All Rghts Reserved 509

2 any mplementaton, the permutaton buffer can sometmes be replaced by a more cost effectve address generator. But as we target complex SDR wth a full range of flexblty and as we want to adapt even to not yet defned nterleavng methods, t was chosen usng a permutaton buffer as the one opton that offers the level of flexblty and performance that s requred. In order to mtgate the overhead, we take beneft of the offered flexblty and mplement extra features as rate matchng, frame equalzaton, handlng of soft bts and hard bts, and mappng n mult-carrer waveforms. An mportant characterstc of our archtecture s ts capablty to handle concurrent nstances of the same or dfferent standards (for mult-rado applcatons). Swtchng from one standard to another s just a matter of loadng a new permutaton table n memory or, when several tables ft n the P buffer, pontng to a dfferent table(see fgure 1 ). In other approaches based on address generators ths can be acheved by duplcatng the hardware and / or addng dfferent generators for dfferent standards (assumng all of them are known at desgn tme)... up to the pont where the number of generators becomes ntractable or where ther cumulated cost exceeds the cost of our table-based soluton. Our fgures account already for ths capablty. Permutaton buffer (P ) 1(0) 1() 1(l1 1)) 2(0) 2() 2(l2 1)) 16 bts l1 64k Standard 1 Standard 2 Input buffer (X) sample 64k Output buffer (Y ) 8 bts 8 bts Fg. 1. Memory based nterleaver archtecture 2.1. Advanced Interleavng modes As already mentoned, our reconfgurable archtecture offers several extra features, confgured through a set of parameters. It s mportant to note that these extra features do not requre extra computaton tme, they are performed whle nterleavng and wth the same hardware. 64k Hard-bts and soft-bts modes The module handles soft bt samples of 1 to 8 bts, stored on a one byte per sample bass, as shown on fgure 2, example (a). The unused bts on a byte are gnored n the nput buffer and forced to zero n the output buffer. (a) (b) j 1() 2() 13 bts P X Y x..x bt offset sample smpl. wdth j smpl. wdth Fg. 2. Softbts (a) and Hardbts (b) operatng mode In the hard-bts mode, each byte of the nput or output buffer holds 8 dfferent one-bt samples. The meanng of the entres n the permutaton table P changes: the 13 MSBs (Most Sgnfcant Bts) are the byte offset n the nput buffer X and the 3 LSBs (Least Sgnfcant Bts) are the bt offset of the nput sample n the selected byte, as depcted n fgure 2, example (b), where the nput and output data are accessed btwse. Hard bts are frequently used on transmsson and soft bts on recepton Rate-matchng mode The rate matchng process s carred out so that the sze of a block of samples matches the sze of rado frames. It wll ether repeat bts to ncrease the rate or puncture bts to decrease the rate. At transmsson the rate-matchng s specfed n the permutaton table, ether by repeatng entres n the P Buffer, or by omttng them, accessng several tmes the same sample from the X buffer, or smply not accessng t at all, accordng to the rate-matchng specfcaton. At recepton, repeated samples wll be handled dfferently from the others. When rate-matchng mode s enabled, the MSB of each P entry s consdered as a repeat flag. The 15 LSBs form the ponter to the nput sample, reducng the range to nstead of The repeat flag defnes a repeat sequences n the P buffer (fgure 3). The ponters n a repeat sequence pont to the dfferent copes of the same repeated nput sample. The dfferent copes can have dfferent values because of transmsson errors. Dependng on the selected rate-matchng mode, the correspondng, sngle, output sample wll be the average of the copes or the last one. If rate-matchng mode s average, a repeat sequence s at most 8 entres long. Unless the last of a repeat sequence, an entry Proceedngs of the SDR 10 Techncal Conference and Product Exposton, Copyrght 2010 Wreless Innovaton Forum, Inc. All Rghts Reserved 510

3 wth the repeat flag unset ponts to a regular, non-repeated, sample. P X Y P () = F orcezero zero one Y repeat sequence (8 entres max n average mode) mean or last Fg. 4. Frame equalzaton mode 15 bts Fg. 3. Rate-matchng operatng mode Frame equalzaton mode Frame equalzaton conssts n addng stuffng bts to the data stream, ether zeros or ones, wth the purpose of ensurng that the output can be segmented nto equal sze segments to be transmtted n a TTI (Transmsson Tme Interval). When the frame equalzaton opton s enabled, two specal values of permutaton entry are defned: ForceZero and ForceOne. When a ForceZero / ForceOne entry s encountered n the P buffer, the nterleaver forces a zero / one n the next ( th ) poston of the Y buffer. The ForceZero and ForceOne specal values can be specfed as an operaton parameter, and should of course be dfferent. Fgure 4 llustrates the frame equalzaton Very large permutaton functons Although the proposed buffer szes are large enough for most today s standards, t s possble that future nterleavng methods requre larger permutaton tables. Stll, these large permutatons can be mplemented n ths archtecture n several passes. When nterleavng n several passes, t may be requred to skp output entres that were updated n prevous passes or wll be updated n subsequent passes. In order to allow ths, a thrd specal value s defned for the permutaton entres: the SkpValue. When the SkpValue entry s encountered and the skp mode s enabled, the ponter to the output buffer s ncremented wthout wrtng any output sample, thus preservng the value of the skpped sample. The SkpValue entry can also be defned as an operatng parameter and should be dfferent from ForceZero and ForceOne f both skp and frame equalzaton modes are enabled Implementaton The nterleaver was mplemented as a ppelne wth statonary control as depcted n fgure 5. The ppelne s dvded n nne stages. Flushng or stallng t s never necessary. It runs at full speed (one permutaton entry per cycle) n all confguratons. Three out of the nne stages are dedcated to memory access, the others are used to generate read and wrte addresses for the three buffers, and to make calculatons for Rate-matchng and Frame-equalzaton procedures. The address generaton logc of ths module was syntheszed for a 130 nm CMOS standard cells lbrary, ts maxmum speed s 350Mhz, although we requre only 200Mhz. At 200Mhz the area consumpton s of just 0.02mm OPTIMIZED INTERLEAVER CORES A generc, table-based, nterleaver such as the one descrbed n the prevous secton s not always the best soluton, even n the SDR context. The nternal nterleaver of turbo coders / decoders s tghtly coupled wth the channel codng / decodng. It would be rather neffcent to delegate ths specfc nterleavng to an external generc nterleaver. Ths s especally true for the decoder because the nterleaver s used several tmes per teraton of the decodng process and the number of teratons s frequently 5 to 10 per code word. A dedcated, compact and energy effcent address generator, embedded drectly nsde the channel coder / decoder seams a much better soluton. The two address generators presented below are dedcated to the 3GPP UMTS and 3GPP LTE turbo nterleavers. They mplement all varants of these two standards at a much lower hardware cost than the generc nterleaver. Ther major drawback, of course, s that they would not handle a possble new standard, wth a totally dfferent turbo nterleavng scheme. Contrary to other mplementatons, lke (3), these nterleavers are already desgned to be embedded n a complete SoC n whch a CPU s n charge of controllng the whole dgtal baseband processng. Thanks to ths CPU, some blocklength specfc parameters are computed n software and drectly used by the hardware address generators. Ths HW / SW parttonng allows for a more effcent hardware utlzaton. Proceedngs of the SDR 10 Techncal Conference and Product Exposton, Copyrght 2010 Wreless Innovaton Forum, Inc. All Rghts Reserved 511

4 VCI_e srstn exec Param eoc err status p_cnt d_ovf eoc_rep r_ovf do_ovf one_rep Interface zero_rep force skp_rep frc1 frc2 skp3 skp4 prevvalue errors skp skp1 skp2 accu_n accu accu1 mask p_ovf Sel1 sel2 repeat rpt1 rpt2 rpt3 rpt4 newvalue enp1 enp2 enx enx1 enx2 enx3 enx4 enp accu endv1 endv2 add mss2p.x a perm addp p nput enx P X Accum d output y stage stage e DIV sam2wr stage eny Y rnwy ry Fg. 5. Full reconfgurable Interleaver controller 3.1. LTE turbo encoder nterleaver Ths module mplements an address generator for the LTE turbo encoder and decoder as defned n (2). The block of samples to nterleave s frst wrtten n a buffer n the natural order. It s then read out accordng to the sequence of addresses produced by the address generator. The nverse permutaton s appled by wrtng the nput block wth the address generator and readng out n natural order. The 3GPP LTE turbo nternal nterleaver s defned n (2) as () = P () = (f 1 + f 2 2 ) mod k, where f 1 and f 2 are two parameters dependng on the block sze k. The module generates a sequence of ndexes P (0), P (1),... P (k 1). P () s the poston n the nput block of the th sample of the output block. The frst output ndex P (0) s thus the ndex n the nput block of the frst output sample. The parameters used by the module (α, β) are calculated n advance from the f 1, f 2 parameters of the 3GPP specfcaton: α = (f 1 + f 2 ) mod k and β = (2 f 2 ) mod k. In the course of an nterleavng / denterleavng operaton, the ndex ncrements from 0 to k 1. The module takes beneft of ths smple scheme to compute the polynomal P () ncrementally: P ( + 1) = f 1 ( + 1) + f 2 ( + 1) 2 = P () + f f 2 + f 2 = P () + Q() Q( + 1) = Q() + 2 f 2 = Q() + β Wth P (0) = 0 and Q(0) = f 1 + f 2 = α. The sequence wraps around k naturally. There s no need to detect the last value of a sequence or to reload Q(0) and P (0) n ther correspondng regsters. Indeed P (k) = 0 = P (0) and Q(k) = α = Q(0). Because P (), Q(), α, β are naturals less than k, the modulus k reducton when computng P (+1) and Q( + 1) s a smple comparson wth k and an optonal subtracton by k. The mplementaton s depcted n fgure6. load β = (f2 2) mod k k k load α = (f1 + f2) mod k β (. +.) mod k q = 0? load 0 (. +.) mod k p last frst Fg. 6. Optmzed archtecture for LTE turbo nterleaver 3.2. UMTS turbo encoder nterleaver Ths module mplements an address generator for the UMTS turbo encoder and decoder as defned n (1). As n the LTE case, the nterleavng / denterleavng s mplemented by wrtng n natural order and readng n permuted order or the opposte. The module generates a sequence of ndexes n 0,... n k 1. The n ndex s the poston n the nput block of the th output sample. The frst output value n 0 s thus the poston n the nput block of the frst output sample. After hardware / software parttonng, t was decded to pre-compute several parameters n software. From the UTMS standard, the parameters that are precomputed are: number of rows rp, number of columns c, prme number p. We also precompute the sere x, whch can be of 5, 10 or 20 elements, where x = (v q 256) mod p, all ths parameters are passed to the module before startng operaton. Once havng the precomputed parameters, the nterleaver mplements the followng steps, accordng to the UMTS standard for turbo code nternal nterleaver: p2 Proceedngs of the SDR 10 Techncal Conference and Product Exposton, Copyrght 2010 Wreless Innovaton Forum, Inc. All Rghts Reserved 512

5 1. Fnd the S(j) j {0,1,...,p 1} for ntra-row permutaton, where S(j) = s(ν s(j 1)) mod p 2. Fnd the q ) {0,1,...,rp 1}, where q 0 s equal to 1; and q s to be a least prmer nteger number such that gdc(q,p q)=1; and q > 6 and > q 1 for each =1,2,3...,R Fnd the r ) {0,1,...,rp 1} sequence, where r T ()=q, = 0, 1, 2..., rp and T (I) I {0,1,...,rp 1} s selected from the standard accordng to the block sze k. 4. Perform ntra-row permutaton as: U (j) = s((j r ) mod (p 1)); where U (j) s the orgnal bt poston of j-th permuted bt of -th row. 5. Perform nter-row permutaton as U T () (j) 6. Read the matrx column by column. In our algorthm, U sequences of 5, 10 or 20 elements are constructed ncrementally. The current value of each U sequence s stored n a shft regster (u () n fgure 7). The j th value of the T () th U sequence s: U T () (j) = S((j r T () ) mod (p 1)) = (v (j r T ()) mod (p 1) ) mod p As by defnton r t() = q, t can be wrtten: U T () (j) = (v (j q) mod (p 1) ) mod p Fermat s lttle theorem allows to rewrte ths expresson as: U T () (j) = (v j q ) mod p = From whch t comes: U T () (j 0) = ( x ) j mod p 256 ( U T () (j 1) x ) mod p 256 Wth U T () (0) = 1. Then, usng (a, b, p) 8 bts modular Montgomery (7) multplcaton: ( ) a b (a, b, p) = mod p 256 We end up wth U T () (j 0) = (U T () (j 1), x, p) 3.3. Archtecture Ths core s based on a Montgomery multplcaton mplementaton, wth two shft regsters as nputs, x () and u () for the two sequences U T () (j 1) and x respectvely. The Montgomery multplcaton s mplemented n 5 stages Table 1. Desgn Results comparson Desgn Process Standards Area Freq (MHz) (mm 2 ) Desgn(13) 180 nm UMTS Desgn(3) 90 nm UMTS, LTE ND ND Ths work 130 nm UMTS, LTE ppelne (correspondng to the mnmum number of rows). The frst 4 stages of the ppelne mplement the 8 teratons of the 8 bts modular Montgomery multpler, 2 bts of x at a tme, LSBs frst. The ffth stage mplements a fnal reducton modulus p. As depcted n fgure 7, for a new nterleavng procedure, the current value of each U sequence s ntalzed to 1. Then, these values enter a fve stages ppelne, one after the other. The output of the ppelne s fed back to the frst poston n the u () ppelne (whch s dfferent for 5, 10 and 20 rows schemes). A 5, 10 or 20 stages ppelne (x () ) contans the x. The x () and u () shft regsters move together so that the rght U and x values are always nput to the four frst stages of the modular Montgomery multpler ppelne. The modular Montgomery multpler also uses a 5 stages w () shft regster to store the ntermedate results of the modular Montgomery multplcaton. Once computed, the current value of each U sequence enters a 3 stages post-processng unt. Ths unt computes the actual n ndexes from the U sequences as specfed n the 3GPP standards. The frst stage computes the nput row and column ndexes. The second stage computes the nput bt poston. The U sequences naturally wrap so there s no need for an ntalzaton between two sequences wth the same parameter set mplementaton Results The two address generators modules were syntheszed for a 130 nm CMOS standard cells lbrary, wth 350 MHz a target clock frequency. Table 1 summarzes the results. Slcon area s used nstead of the more classcal (and more technologyndependent) gate count because some prevous works count nstances of standard cells whle others count gate equvalents, that s, the less buffered, 2-nputs, NAND gate. Takng nto account the technology shft our desgn outperforms (13) n terms of slcon area, maxmum frequency and flexblty. It s probably very close from the one of (3), whch s very smlar. The man dfferences are the utlzaton of a Montgomery modular multpler, the absence of nternal RAM (2 K-bts n (3)) and the pre-computaton of parameters n our case, whle they requre extra hardware to do ths. Proceedngs of the SDR 10 Techncal Conference and Product Exposton, Copyrght 2010 Wreless Innovaton Forum, Inc. All Rghts Reserved 513

6 Post. P 1 P 2 P 3 RED R = 20 R = 10 R = 5 u (18) u (17) u (8) u (3) u (2) u (1) u (0) w (0) w (3) S w (2) w (1) 3 S 2 S 1 S 0 x (19) x (18) x (9) x (4) x (3) x (2) x (1) x (0) R = 20 R = 10 R = 5 Fg. 7. Optmzed archtecture for UMTS turbo nterleaver 4. CONCLUSIONS Ths paper presents three archtectures of nterleavers targetng complex SDR applcatons. The frst s a full reconfgurable desgn that can be used for practcally all known standards of communcatons, and provdng more flexblty than any other archtecture of our knowledge. The two others are optmzed for the LTE and UMTS turbo nterleavers respectvely. They are extremely compact and fast but ther flexblty s lmted to the varants of ther target standard. References [1] 3GPP. Multplexng and channel codng (fdd), rel 920. [2] 3GPP. Evolved unversal terrestral rado access (eutra); multplexng and channel codng, rel 920. [3] ASGHAR, R., AND LIU, D. Dual standard reconfgurable hardware nterleaver for turbo decodng. In Wreless Pervasve Computng, ISWPC rd Internatonal Symposum on ( ), pp [4] CHANG, Y.-N. A low-cost dual-mode denterleaver desgn. Consumer Electroncs, IEEE Transactons on 54, 2 (May 2008), [5] HAO, D., YAO, P., AND HOEHER, P. Analyss and desgn of nterleaver sets for nterleave-dvson multplexng and related technques. In Turbo Codes and Related Topcs, th Internatonal Symposum on (Sept. 2008), pp [6] MITOLA, J. The software rado archtecture. Communcatons Magazne, IEEE 33, 5 (May 1995), [7] MONTGOMERY, P. L. Modular multplcaton wthout tral dvson. Mathematcs of Computaton 44, 170 (1985), [8] MUHAMMAD, N.-U.-I., RASHEED, R., PACALET, R., KNOPP, R., AND KHALFALLAH, K. Flexble baseband archtectures for future wreless systems. pp [9] PARK, S.-J., AND JEON, J.-H. Interleaver optmzaton of convolutonal turbo code for systems. Communcatons Letters, IEEE 13, 5 (May 2009), [10] SADJADPOUR, H., SLOANE, N., SALEHI, M., AND NEBE, G. Interleaver desgn for turbo codes. Selected Areas n Communcatons, IEEE Journal on 19, 5 (May 2001), [11] SANCHEZ-ORTIZ, C., PARRA-MICHEL, R., AND GUZMAN-RENTERIA, M. Desgn and mplementaton of a mult-standard nterleaver for a, n, e & dvb standards. In Reconfgurable Computng and FPGAs, ReConFg 08. Internatonal Conference on (Dec. 2008), pp [12] WANG, M., SHEIKH, A., AND QI, F. Interleaver desgn for short turbo codes. In Global Telecommuncatons Conference, GLOBECOM 99 (1999), vol. 1B, pp vol. 1b. [13] WANG, Z., AND LI, Q. Very low-complexty hardware nterleaver for turbo decodng. Crcuts and Systems II: Express Brefs, IEEE Transactons on 54, 7 (july 2007), [14] WU, Y.-W., TING, P., AND MA, H.-P. A hgh speed nterleaver for emergng wreless communcatons. In Wreless Networks, Communcatons and Moble Computng, 2005 Internatonal Conference on (June 2005), vol. 2, pp Proceedngs of the SDR 10 Techncal Conference and Product Exposton, Copyrght 2010 Wreless Innovaton Forum, Inc. All Rghts Reserved 514