TQP3M9008 High Linearity LNA Gain Block
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- Victor York
- 5 years ago
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1 General Description The is a cascadable, high linearity gain block amplifier in a low-cost surface-mount package. At 1.9 GHz, the amplifier typically provides 2.6 db gain, +36 dbm OIP3, and 1.3 db Noise Figure while only drawing 85 ma current. The device is housed in a leadfree/green/rohs-compliant industry-standard SOT-89 package using a NiPdAu plating to eliminate the possibility of tin whiskering. The has the benefit of having high gain across a broad range of frequencies while also providing very low noise. This allows the device to be used in both receiver and transmitter chains for high performance systems. The amplifier is internally matched using a high performance E-pHEMT process and only requires an external RF choke and blocking/bypass capacitors for operation from a single +5 V supply. The internal active bias circuit also enables stable operation over bias and temperature variations. The covers the.5 4 GHz frequency band and is targeted for wireless infrastructure or other applications requiring high linearity and/or low noise figure. Functional Block Diagram Product Features 3-pin SOT-89 Package 5 4 MHz 2.6 db Gain at 1.9 GHz +36 dbm Output IP3 1.3 db Noise Figure at 1.9 GHz 5 Ohm Cascadable Gain Block Unconditionally stable High input power capability +5 V Single Supply, 85 ma Current SOT-89 Package Applications Repeaters Mobile Infrastructure LTE / WCDMA / EDGE / CDMA General Purpose Wireless Backside Paddle - GND Ordering Information RF IN GND RF OUT / V DD Part No. Description -PCB_IF.5.5 GHz Evaluation Board -PCB_RF.5 4. GHz Evaluation Board Standard T/R size = 1 pieces on a 7 reel Data Sheet, January 1, 218 Subject to change without notice 1 of 1
2 Absolute Maximum Ratings Parameter Rating Storage Temperature 65 to 15 C RF Input Power, CW, 5Ω, T= C Device Voltage (VDD) Reverse Device Voltage +23 dbm +7 V.3 V Operation of this device outside the parameter ranges given above may cause permanent damage. Recommended Operating Conditions Parameter Min Typ Max Units Device Voltage (VDD) V TCASE C Tj for >1 6 hours MTTF +19 C Electrical specifications are measured at specified test conditions. Specifications are not guaranteed over all recommended operating conditions. Electrical Specifications Test conditions unless otherwise noted: VDD = +5 V, Temp. = + C, 5 Ω system Parameter Conditions Min Typ Max Units Operational Frequency Range 5 4 MHz Test Frequency 19 MHz Gain db Input Return Loss 16 db Output Return Loss 17 db Output P1dB +2 dbm Output IP3 Pout = +3 dbm/tone, f = 1 MHz dbm Noise Figure 1.3 db Current, IDD 85 1 ma Thermal Resistance, θjc Junction to case 38.7 C/W Data Sheet, January 1, 218 Subject to change without notice 2 of 1
3 S-Parameters Test Conditions: VDD = +5 V, IDD = 85 ma, Temp. = + C, 5 Ω system, calibrated to device leads Freq (MHz) S11 (db) S11 (ang) S21 (db) S21 (ang) S12 (db) S12 (ang) S22 (db) S22 (ang) Data Sheet, January 1, 218 Subject to change without notice 3 of 1
4 -PCB_IF / RF Evaluation Board J4 J3 J3 V DD R1 J4 GND R1 C3 C1 Q1 L1 C3 C2 L1 J1 RF Input C1 1 Q1 3 2, Backside Paddle C2 J2 RF Output Notes: 1. See Evaluation Board PCB section for material and stack-up. 2. Components shown on the silkscreen but not on the schematic are not used. 3. R1 ( Ω jumper) may be replaced with copper trace in the target application layout. 4. The recommended component values are dependent upon the frequency of operation. 5. All components are of 63 size unless stated on the schematic. Bill of Material -PCB_IF / RF Reference Designation -PCB_IF -PCB_RF 5-5 MHz 5-4 MHz Q1 C1, C2 1 pf 1 pf C3.1 uf.1 uf L1 33 nh 68 nh D1 Do Not Place R1 Ω Performance can be optimized at frequency of interest by using recommended component values shown in the table below. Reference Designation C1, C2 1 pf 22 pf 22 pf 22 pf L1 82 nh 22 nh 18 nh 15 nh Data Sheet, January 1, 218 Subject to change without notice 4 of 1
5 NF (db) OIP3 (dbm) OIP3 (dbm) Gain (db) S11 (db) S22 (db) Typical Performance -PCB_RF Test conditions unless otherwise noted: VDD=+5 V, IDD=85 ma, Temp=+ C, 5 Ω system Parameter Typical Value Units Frequency MHz Gain db Input Return Loss db Output Return Loss db Output P1dB dbm OIP dbm Noise figure db Notes: 1. OIP3 measured with two tones at an output power of +3 dbm / tone separated by 1 MHz. 2. Noise figure values in the table above includes board losses. Approx. =.1dB at 2 GHz. Performance Plots -PCB_RF Test conditions unless otherwise noted: VDD = +5 V, IDD = 85 ma, Temp. = + C, 5 Ω system Gain vs. Frequency over Temp -4 C -2 C + C +85⁰C S11 vs. Frequency over Temp -2⁰C -5-1 S22 vs. Frequency over Temp -2 C +85⁰C Noise Figure vs. Frequency over Temp 45 OIP3 vs. Pout/tone over Temp F=19 MHz, 1 MHz tone spacing 45 OIP3 vs. Frequency over Temp 1 MHz tone spacing, 3 dbm/tone Pout/tone (dbm) Data Sheet, January 1, 218 Subject to change without notice 5 of 1
6 Idd (ma) Idd (ma) OIP3 (dbm) P1dB (dbm) NF (db) P1dB (dbm) OIP2 (dbm) Pout (dbm) Performance Plots -PCB_RF Test conditions unless otherwise noted: VDD = +5 V, IDD = 85 ma, Temp. = + C, 5 Ω system 22 2 P1dB vs. Frequency over Temp 55 5 OIP2 vs. Frequency Pout = 3 dbm / tone, 1 MHz spacing, +5V, +C _PCB-RF Freq.=5 MHz Temp.=+ C Compression Curve P1dB P1dB Pin (dbm) MHz 9MHz OIP3 vs. Vdd Pout/tone = 3dBm Tone spacing = 1MHz 3 2 P1dB vs. Vdd 19 MHz 9 MHz MHz 9MHz Noise Figure vs. Vdd Vdd (Volts) Vdd (Volts) Vdd (Volts) 9 Idd vs Vdd 9 Idd vs. Temperature CW Signal Vdd (Volts) Temperature ( C) Data Sheet, January 1, 218 Subject to change without notice 6 of 1
7 Pout (dbm) NF (db) OIP3 (dbm) P1dB (dbm) Gain (db) S11 (db) S22 (db) Typical Performance -PCB_IF Test conditions unless otherwise noted: VDD = +5 V, IDD = 85 ma, Temp. = + C, 5 Ω system Parameter Typical Value Units Frequency MHz Gain db Input Return Loss db Output Return Loss db Output P1dB dbm OIP dbm Noise figure db Notes: 1. OIP3 measured with two tones at an output power of +3 dbm / tone separated by 1 MHz. 2. Noise figure values in the table above includes board losses. Approx. =.1dB at 2 GHz. Performance Plots -PCB_IF Test conditions unless otherwise noted: VDD =+5 V, IDD =85 ma, Temp= + C, 5 Ω system. Gain vs. Frequency over Temp S11 vs. Frequency over Temp S22 vs. Frequency over Temp C -2 C + C +85⁰C ⁰C -2 C C +85⁰C Noise Figure vs. Frequency over Temp 45 OIP3 vs. Frequency over Temp 1 MHz tone spacing, 3 dbm/tone 22 P1dB vs. Frequency over Temp _PCB-IF Freq.=5 MHz Temp.=+ C Compression Curve P1dB P1dB Pin (dbm) Data Sheet, January 1, 218 Subject to change without notice 7 of 1
8 Pin Configuration and Description Backside Paddle - GND Pin No. Label Description 1 RF IN RF input; matched to 5 ohms. External DC Block is required. 2, Backside Paddle GND RF/DC ground. Use recommended via pattern to minimize inductance and thermal resistance. See PCB Mounting Pattern for suggested footprint. 3 RF OUT / VDD RF output, matched to 5 ohms. External DC Block and bias voltage required. Evaluation Board PCB RF IN GND RF OUT / V DD Qorvo PCB 1758 Material and Stack-up.62" ±.6" Finished Board Thickness Nelco N-4-13 Core Nelco N oz. Cu top layer 1 oz. Cu inner layer 1 oz. Cu inner layer 1 oz. Cu bottom layer 5 ohm line dimensions: width =.28, spacing =.28 Data Sheet, January 1, 218 Subject to change without notice 8 of 1
9 Package Marking and Dimensions Package Marking Product Identifier: 3M98 Lot Code: XXXX Notes: 1. All dimensions are in millimeters. Angles are in degrees. 2. Dimension and tolerance formats conform to ASME Y14.4M The terminal #1 identifier and terminal numbering conform to JESD 95-1 SPP Contact plating: NiPdAu or Matte Tin PCB Mounting Pattern 29X [.152] 1.26 [.5].63 [.].76 [.3] 4.5 [.177] Ø.4 (.1) PLATED THRU VIA HOLES PACKAGE OUTLINE 2X.58 [.23] 2X 1.27 [.5] 2.65 [.14].64 [.] 2X.86 [.34].86 [.34] 3.86 [.152] NOTES: 1. All dimensions are in millimeters[inches]. Angles are in degrees. 2. Use 1 oz. copper minimum for top and bottom layer metal. 3. Vias are required under the backside paddle of this device for proper RF/DC grounding and thermal dissipation. We recommend a.35mm (#8/.135") diameter bit for drilling via holes and a final plated thru diameter of.mm (.1 ). 4. Ensure good package backside paddle solder attach for reliable operation and best electrical performance. 5. Place mounting screws near the part to fasten a back side heat sink. 6. Do not apply solder mask to the back side of the PC board in the heat sink contact region. 7. Ensure that the backside via region makes good physical contact with the heat sink. Data Sheet, January 1, 218 Subject to change without notice 9 of 1
10 Product Compliance Information ESD Sensitivity Ratings Caution! ESD-Sensitive Device ESD Rating: Class 1A Value: V to < 5 V Test: Human Body Model (HBM) Standard: ESDA/JEDEC Standard JS ESD Rating: Class C3 Value: 1 V Test: Charged Device Model (CDM) Standard: JEDEC Standard JESD22-C11F MSL Rating MSL Rating: Level 3 or better Test: 26 C convection reflow Standard: JEDEC Standard IPC/JEDEC J-STD-2 Solderability Compatible with both lead-free (26 C maximum reflow temperature) and tin/lead (245 C maximum reflow temperature) soldering processes. Contact plating: NiPdAu or Matte Tin RoHs Compliance This part is compliant with EU 22/95/EC RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and Electronic Equipment). This product also has the following attributes: Lead Free Halogen Free (Chlorine, Bromine) Antimony Free TBBP-A (C15H12Br42) Free PFOS Free SVHC Free Contact Information For the latest specifications, additional product information, worldwide sales and distribution locations: Tel: Web: customer.support@qorvo.com For technical questions and application information: appsupport@qorvo.com Important Notice The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR OTHERWISE, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Copyright 218 Qorvo, Inc. Qorvo is a registered trademark of Qorvo, Inc. Data Sheet, January 1, 218 Subject to change without notice 1 of 1
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Applications 3G / 4G Wireless Infrastructure CDMA, WCDMA, LTE Repeaters ISM Infrastructure Product Features 28-pin 6x6 mm leadless SMT package Functional Block Diagram 0.6-1.0 GHz Frequency Range 31.5
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2.4GHz Wi-Fi LNA+BAW Receive Module Product Overview The provides a complete integrated receive solution in a single placement front end module (FEM) for Wi-Fi 802.11a/n/ac systems. The full integration
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Applications Return Path Amplifier System Amplifier Line Amplifier DOCSIS Return Path VGA Bonded Channel Cable Modem Return Path Product Features 6x6 mm Pin leadless SMT Package Functional Block Diagram
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Applications Repeaters BTS Transceivers BTS High Power Amplifiers CDMA / WCDMA / LTE General Purpose Wireless 24-pin QFN 4x4mm SMT Package Product Features Functional Block Diagram 700-4000 MHz +32.8 dbm
More informationQPD W / 220 W, 48 V, Asymmetric Doherty. Product Description. Applications. Ordering Information
Product Description The is an asymmetric Doherty power device composed of pre-matched, discrete GaN on SiC HEMTs. The device operates from 2.575 to 2.635 GHz. can deliver PAVG of 36 W at +48 V operation.
More informationTQM EVB B7 BAW Duplexer
Applications LTE handsets, data cards & mobile routers Band 7 2500-2570 MHz Uplink 2620-2690 MHz Downlink 8 Pin 1.6 x 2.0 mm Package Product Features Highly Selective LowDrift BAW Duplexer Low Insertion
More informationTAT7457-EB. CATV 75 Ω phemt Adjustable Gain RF Amplifier. Applications. Ordering Information
Applications Single-ended and Push-pull Optical Receivers Low-noise Drop Amplifiers Distribution Amplifiers Multi-Dwelling Units Single-ended Gain Block SOT-89 package Product Features Functional Block
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General Description The is a high linearity driver amplifier in industry standard, RoHS compliant, QFN surface mount package. This InGaP / GaAs HBT delivers high performance across 6 27 MHz range of frequencies
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Applications W-CDMA / LTE Macrocell Base Station, Band 1 and Band 3 Active Antenna General Purpose Applications 2 Lead NI400 Package Product Features Functional Block Diagram Operating Frequency Range:
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Product Description The Qorvo is a packaged 6-bit digital phase shifter fabricated on Qorvo s high performance.15 um GaAs phemt process. It operates over 2.5-4 GHz while providing 36 of phase coverage
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Applications Point-to-Point Radio -Lead 8.0 x.0 x 2 mm Package Product Features Functional Block Diagram Frequency Range: 9.5 12 GHz Power: +42 dbm Psat Gain: 33 db Integrated Power Detector Bias: V D1
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5 MHz to 6000 MHz Digial Step Attenuator Product Overview The RFMD s is a 4-bit digital step attenuator (DSA) that features high linearity over the entire 15dB gain control range with 1.0dB steps. The
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Applications Repeaters Base Station Transceivers High Power Amplifiers Mobile Infrastructure LTE / WCDMA / CDMA / WiMAX SOIC- Package Product Features Functional Block Diagram -7 MHz.7 db Gain at MHz +
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TGA94-HM Product Description Qorvo s TGA94-HM is a packaged power amplifier fabricated on Qorvo s. um GaN on SiC process (QGaN). Operating from 27 to 31 GHz, the TGA94- HM achieves 36.5 dbm saturated output
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Product Description Qorvo s TGA2214-CP is a packaged wideband power amplifier fabricated on Qorvo s QGaN15 0.15 µm GaN on SiC process. Operating from 2 to 18 GHz, the TGA2214- CP generates > 4 W saturated
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Product Overview The is a digital variable gain amplifier (DVGA) featuring high linearity over the entire gain control range. This amplifier module integrates two gain blocks, a digitalstep attenuator
More informationTGA2583-SM 2.7 to 3.7 GHz, 10 W GaN Power Amplifier
Applications Commercial and Military Radar QFN 5x5 mm 32L Product Features Functional Block Diagram Frequency Range: 2.7 3.7 GHz PSAT:.5 dbm PAE: > 50 % Small Signal Gain: 33 db Return Loss: > 12 db Bias:
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More informationTGA2813-CP 3.1 to 3.6 GHz, 100W GaN Power Amplifier
Applications Radar Product Features Frequency Range: 3.1 3.6 GHz Pout: 5 dbm (at PIN = 27 dbm) Power Gain: 23 db (at PIN = 27 dbm) PAE: 51 % CW Bias: VD = pulsed (PW = 15 ms, DC = 3 %), IDQ = 3 ma, VG
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More informationTQP4M9083 High Linearity 7-Bit, 31.75dB Digital Step Attenuator
Applications Mobile Infrastructure LTE / WCDMA / CDMA / EDGE Test Equipment and Sensors IF and RF Applications General Purpose Wireless Product Features 24-pin 4x4mm leadless QFN package Functional Block
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