MAX100 Evaluation Kit. Evaluates: MAX100

Transcription

1 ; Rev 0; 11/94 MAX100 Evaluation Kit General Description The MAX100 evaluation kit (EV kit) allows high-speed digitizing of analog signals at 250Msps, using the MAX100 ADC. All circuitry required to support the ADC is supplied. Data output is available in three formats: divide-by-1, divide-by-2, or divide-by-5 mode. Clocking is provided by an external clock source input through an SMA connector. The MAX100 EV kit main board comes complete with a MAX100 high-speed, 8-bit flash ADC with strobed comparators, latched outputs, and an internal track/hold. Analog input to the board is through two SMA coaxial connectors, for use with either differential or singleended inputs. Signals from the main board include dual-output data paths that allow easy interfacing to external circuitry. These two outputs can be configured either to provide two identical fast outputs (A and B), or an 8-to-1 demultiplexer mode that reduces the output data rates to one-half the sample clock rate. This demux is internal to the MAX100 ADC and is one of the key features of this device. A termination board with 50Ω ECL pull-down resistors is also supplied, and is connected to the main board with a 3x32 pin EURO-card connector. It provides access to the converter output data and provides proper ECL data termination. In addition to the pull-down resistors, this board has two ranks of square pins, each providing eight differential data outputs plus clock outputs. Either AData or BData may be observed with a high-speed logic analyzer. Standard power supplies of +5V and -5.2V are needed to operate the MAX100 EV kit board. Power can be supplied through the 3x32 EURO-card connector or through the pads on the edge of the board. Nominal power dissipation for both boards is 12W. The board set comes fully assembled and tested, with the MAX100 installed. Features.8 Effective Bits at 125MHz On-Board Reference Generator/Buffer 50Ω Input Through SMA Coaxial Connectors Dual Differential-Output Data Paths ±270mV Input Signal Range Latched 100k ECL Outputs 3x32 Pin EURO-Card Connector Ordering Information PART TEMP. RANGE BOARD TYPE MAX100EVKIT 0 C to +70 C Multi-Layer EV Kit Maxim Integrated Products 1 Call toll free for free literature.

2 Component List DESIGNATION QTY DESCRIPTION U5 1 Motorola MC100E11 (quintuple line receiver) U2, U3, U4 3 Motorola MC100E151 (Hex D flip-flop) U9 1 Motorola MC100E157 (quadruple 2:1 multiplexer) U 1 LM337T negative voltage regulator Install on back of board behind U 1 Insulating washer U7 1 Maxim MAX412CPA U8 1 Maxim MX580KH D1, D2 2 Central Semiconductor CMPSH-3 D3 1 Central Semiconductor CMPD4448 C25, C µF ceramic SMD capacitors C2, C, C µF ceramic SMD capacitors C1, C3, C5, C8, C11, C12, C14, C1, C18, C20, C22 C24, C2, C28, C29 C13, C15, C17, C19, C21, C30 1 ceramic SMD capacitors 100pF ceramic SMD capacitors C4, C7, C µF surface-mount tantalum capacitors SW1 1 8-pin dip switch L1, L2 2 Surface-mount ferrite bead R14, R Ω, 5% surface-mount resistors R18, R Ω, surface-mount resistors R7, R8, R13, R20 R45 29, 5% surface-mount resistors R1, R3, R Ω, surface-mount resistors R5, R Ω, surface-mount resistors R Ω, surface-mount resistor R2, R Ω, surface-mount resistors R1, R kΩ, surface-mount resistors R11, R Ω trim pots J1, J2, J3 3 Female SMA connectors J4 1 9-pin EURO-style plug None 1 MAX100 clamp kit Quick Start 1) Plug the termination board into the 9-pin connector of the MAX100 EV kit board. 2) Use a fan to provide at least 200 lineal feet per minute airflow to the MAX100 s heatsink. 3) Connect the power supplies. The power-supply input pads are in the lower right corner of the MAX100 EV kit board. The board requires a 12W power supply that provides +5V and -5.2V with a common ground. 4) Turn on the -5.2V power supply, followed by the +5V power supply. The -5.2V power supply should be the first supply turned on and the last supply turned off. 5) Connect a low-phase-jitter RF source with an input range of -4dBm to +10dBm to the clock input. ) Connect a test signal to the analog inputs. Use IN+ and IN- if the signal is differential, or use IN+ if the signal is single-ended. 7) Use a logic analyzer (such as the HP8000 or an equivalent data-acquisition system) to observe the digitized results on the termination board pins. The outputs are 100k ECL compatible. Detailed Description Board Set The MAX100 EV kit is a two-board set. The first contains ECL-interface circuitry and the MAX100 ADC. The second (termination board) provides for high-speed signal termination and access to the data. For further signal processing, the board containing the MAX100 can be plugged into a larger customer system via the provided EURO-card connector. Clock Input The ADC clock is provided through an external clock input. The external clock supplied to the board must be very stable, with low phase jitter (-150dBc/Hz at 0.2kHz from fundamental) for best effective bits performance. Figure 2 in the MAX100 data sheet shows the input to output clock and data timing relationships. The MAX100 will accurately operate with low-repetitionrate clocks (DC to 250MHz) as long as the proper t pwl is observed (nominally 2ns to 5ns). Refer to Figures 1 4 in the MAX100 data sheet for further information. Analog Input Analog input to the ADC is made through one or both of the SMA coaxial connectors (IN+, IN-) provided. Each input is a direct connection to the ADC. 50Ω terminations are provided (at AIN+ and AIN- inputs) internal to the MAX100 ADC. Optimum performance is achieved 2

3 by using the converter in differential input mode. Single-ended drive is handled by choosing either input, and leaving open or terminating the other in the system characteristic impedance. In this mode, the unused input can provide a DC offset to the incoming signal. (See the Electrical Characteristics in the MAX100 data sheet for this DC voltage range.) To obtain a digital output of all ones (11...1) with differential input drive, apply 270mV between AIN+ and AIN-. That is, AIN+ = +135mV and AIN- = -135mV (when no DC offset is applied). Mid-scale digital output code occurs when there is no voltage difference across the analog inputs. Zero-scale digital output code, with differential drive, occurs when AIN+ = -135mV and AIN- = +135mV. The converter s output stays at all ones (full scale) or all zeros (zero scale) when over-ranged or under-ranged, respectively. Table 1 shows these relationships. Digital Outputs The MAX100 EV kit provides complementary ECL digital outputs. Data output from the ADC is available in several selectable options (Table 2). Two 8-bit-wide data paths from the ADC are latched in D flip-flops (MC100E151), and are provided as unterminated differential outputs at the 3x32 pin EURO-card connector on the main board. Output timing clocks DCLK and DCLK are also available unterminated at the connector. Clock Phasing The MAX100 contains an internal track/hold (T/H) amplifier. The differential inputs, AIN+ and AIN-, are tracked continuously between data samples. When a negative CLK is applied, the T/H enters the hold mode. When CLK reaches the low state, the just-acquired sample is presented to the ADC s input comparators. After additional clock cycles required for internal processing, the sampled data is available at the AData or BData outputs. All output data is timed from the output clocks, DCLK and DCLK. (See Figure 2 in the MAX100 data sheet.) ADC Reference Resistors An on-board reference supply and op-amp circuit drive the ADC reference-resistor string. Adjustments can be made through the two potentiometers provided. After the MAX100 ADC is installed, follow the Calibration Procedure. Buffer amplifiers are used to drive the top and bottom inputs of the reference-resistor string. (The resistor string center-tap is not made available for adjustment on this board.) A 2.5V reference (MX580KH) is divided down and buffered through a MAX412 op amp. The relatively low 14Ω input impedance of this string will draw approximately 14mA. A reference voltage of nominally ±1.02V is set by trim pots R11 and R12 at the factory, and can be measured at the VARTS and VARBS sense input pins. This reference controls the comparator input windows, and can be adjusted between ±1.4V to accommodate other reference voltages (MAX100 accuracy specifications are based on a reference voltage of ±1.02V). DIV, MOD, A=B Three dip switches (SW1), DIV, MOD, and A=B, program converter operation and the characteristics of the two output data paths. Six options are available, but the normal operating configuration is set to on the A=B, MOD, and DIV switches, respectively (Table 2). This gives the most current sample at AData, with the older data on BData. Both outputs are synchronous and are output at half the input clock rate. Figure 4 shows the location of these switches on the ADC board. Refer to Table 1 for mode-selection instructions. Power Supplies Two supplies are needed for normal operation of both boards with a device installed: +5V at 0.A and -5.2V at 1.7A. The pads APOS1 and ANEG1 are located in the lower right corner of the ADC board, and are labeled accordingly. The ADC runs off both supplies. Power may also be applied at the EURO-card connector pins, which are labeled as follows: (+5V), (-5.2V for digital DNEG1), (-5.2V for analog ANEG1), and (1 ground). The ferrite beaded jumper (L1) in the lower right corner of the board connects and for a single -5.2V supply. Board Layout The MAX100 requires proper PC board layout for device operation. This section explains the layout requirements and demonstrates how the EV kit achieves these goals. Use power and ground planes to deliver power to the devices, keeping the digital planes separate from the analog planes. The EV kit uses layers 3, 4, and 5 for power and ground planes. Tie digital ground and analog ground together at a single point, as close to the power supply as possible. On the EV kit, digital ground ties to analog ground at ferrite bead L1. Likewise, tie digital power () and analog power () together at a single point, as close to the power supply as possible. On the EV kit, digital power ties to analog -5.2V power at ferrite bead L2. Use transmission lines for the analog input and for the high-speed digital outputs. The MAX100 EV kit uses 50Ω microstrip lines that occupy layers 1 and 2, and 3

4 FR4 epoxy dielectric material with a relative dielectric constant between 4.1 and 4.9. The nominal design has a foil thickness of inch ( mm) for layer 1 (the signal layer) and inch ( mm) for layer 2 (the ground return). Dieletric thickness between layers is nominally inch (0.28 mm), with a signal trace width of inch (0.50 mm). Refer to Motorola s MECL or ECLinPS data book for an introduction to microstrip design. Due to the high-speed nature of this part, the propagation delay of the PC board traces becomes a significant design consideration. For the EV kit design, the propagation delay is approximately 145ps per inch (5.7ps/mm). For best results, try to match the lengths of the data traces to within 0.5 inch (12 mm). The EV kit board matches the data-bus lengths by using curved traces on layer. A computer-aided design system can be helpful in measuring the trace lengths accurately. The clock signal must be routed on one layer only, without using any throughhole vias. The MAX100 EV kit is a controlled-impedance board (50Ω) and has a total board thickness of 0.02 inches (1.57 mm) using six copper layers (Figure 3). Testing We recommend that a digital acquisition instrument like the HP8000 logic analyzer be used to acquire and process the output data. At Maxim, the data acquired from the converter is evaluated in an effective-bits software program developed in-house. The effective-bits measurement is a good tool to determine and compare ADC accuracy. Calibration Procedure The MAX100 EV kit comes ready to operate from the factory. If other devices are to be used in the same fixture, the EV kit should be recalibrated according to the following procedure: 1) With the ADC removed, adjust the +5V and -5.2V supplies. 2) Set the mode-select options (A=B, DIV, MOD) for the desired operation using the on-board DIP switches. See Table 1. 3) With the power off, insert the MAX100. The MAX100 s heatsink fits down through the board with the device leads resting on top. Be sure to place the part in the board with pin 1 in the correct location. Provide at least 200 lineal feet per minute airflow whenever power is applied. Turn on the power supplies with -5.2V first, then the +5V. The -5.2V power supply should be the first supply turned on and the last supply turned off. MECL and ECLinPS are trademarks of Motorola Corp. Table 1. Input Voltage Range INPUT Differential Single- Ended AIN+** (mv) AIN-** (mv) OUTPUT CODE (MSB TO LSB) Full scale Mid scale Zero scale Full scale Mid scale Zero scale ** An offset, V IO, as specified in the DC Electrical Characteristics, is present at the input. Compensate for this offset either by adjusting the reference voltage VA RT, VA RB, or by introducing an offset voltage in one of the input terminals, AIN+ or AIN-. Table 2. Output-Mode Control DIV MOD A = B DCLK* DESCRIPTION Divide-by-1 Mode 0 X 0 250MHz Data appears on AData only. BData port inactive (see Figure 3 of MAX100 data sheet). 0 X 1 250MHz Divide-by-2 Mode MHz MHz Divide-by-5 Mode MHz MHz AData identical to BData (see Figure 3 of MAX100 data sheet). 8:1 demux mode. AData and BData ports are active. BData carries older sample and AData carries most recent sample (see Figure 4 of MAX100 data sheet). AData and BData ports are active. Both carry identical sampled data. Alternate samples are taken but discarded. AData port updates data on 5th input CLK. BData port inactive. The other four sampled data points are discarded. AData and BData ports are both active with identical data. Data is updated on output ports every fifth input clock (CLK). The other four samples are discarded. * Input clocks (CLK, CLK) = 250MHz for all above combinations. In divide-by-2 or divide-by-5 mode, the output clock DCLK is always a 50% duty-cycle signal. In divide-by-1 mode, DCLK has the same duty cycle as CLK. 4

5 4) After the part has warmed up for several minutes, adjust the reference voltages to ±1.02V nominally. The test points for these voltages are at the bottom of the sense resistors, R13 and R1, located just above the sense pins VARTS and VARBS (Figure 4). 5) Adjust mid-code level. With no analog input (AIN+ - (AIN-) = 0V) the output code should match that specified in Table 1. If there is an offset, adjust either the positive or negative reference until the expected code C23 U8 1 MX580KH +VS TO VREF VOUT C24 ADJREF+1 3 R11 100Ω ADJREF+1 R9 150, R12 100Ω R10 121Ω, ADJREF-1 R k REFERENCE VOLTAGE GENERATOR 1 U7A MAX412CPA DIP8 7 U7B MAX412CPA DIP8 C2 C28 of (MSB to LSB) is achieved. After adjusting to the proper level, the references need to be balanced to ±1.02V around any offset that was introduced. (If the negative reference was moved by +32mV, the positive reference must be moved by that same amount to ensure the correct LSB size.) It may be necessary to repeat the reference offset adjustment again after the correct 2.04V differential reference voltage is re-established around the common-mode offset. R14 20Ω, 5% C µF R15 20Ω, 5% C µF R13, 5% R1 12.1k R Ω, D1 SOT-23 CMPSH-3 R Ω, D2 SOT-23 CMPSH-3 VARTS VART TO MAX100 VARBS VARB POWER-SUPPLY BYPASSING ANALOG +5.0V ANALOG GROUND ANALOG -5.2V DIGITAL +5.2V APOS1 1 ANEG1 DNEG1 FERRITE L1 C3 C5 C8 C2 0.1µF C 0.1µF C9 0.1µF C4 10µF, 10V C7 10µF, 10V C10 CAP 10µF, 10V FERRITE L2 MODE SELECT SWITCHES D3 CMPD SW A = B MOD DIV DIP8 BYPASS CAPACITORS NEAR U1 C12 PIN 8 C13 100pF C20 PIN 32 C21 100pF PIN 43 C18 C19 100pF PIN 80 PIN 9 C1 C17 100pF C14 C15 100pF GENERATOR ADJ U LM337T TO-220 OUT IN 2-5.2V 1 3 C11 R5 121Ω R 82.5Ω -2.0V TO TERMINATING RESISTORS Figure 1. MAX100 EV Kit Schematic 5

6 NOTES: 1. WHERE INDICATED, MATCH BUS LENGTH TO WITHIN ±0.5". 2. UNLESS OTHERWISE SPECIFIED, ALL RESISTORS AND CAPACITORS ARE 120 SIZE. 3. NOTE SPECIAL MECHANICAL REQUIREMENTS OF MAX100, INCLUDING CUT-OUT FOR THE HEATSINK. J2 J3 ANALOG PLANES DIGITAL PLANES C22 R7 R8 4 5 TP3 TP2 7 8 TP INPUT+ 72 AIN+ 73 AIN+ 74 INPUT- 75 AIN- 7 AIN PAD 2 CLK 3 CLK 4 VART VARB 3 2 CLK 1 CLK TO/FROM REFERENCE BUFFER VARB 54 VARBS 53 VACT 52 VACTS 51 U1 MAX100 B0 VARTS 50 VART B0 4 NOTE MECHANICAL REQUIREMENTS A0 D 45 VARTS VARBS B1 A0 44 B DIV 12 MOD 13 DCLK 14 DCLK 15 1 A = B 17 A7 18 D 19 B7 20 A 21 ANALOG PLANES DIGITAL PLANES 42 A1 41 B2 40 D 39 A2 38 B3 37 D 3 A D D 29 SUB 28 B4 27 D 2 A4 25 B5 24 D 23 A5 22 A1 B2 A2 B3 A3 B4 A4 B5 A5 DCLK DCLK A7 B7 A J1 SMA EXT CLK C1 R4 221Ω R3 82.5Ω R2 221Ω R1 82.5Ω U5D MC100E11 R42 R43 R44 ANALOG PLANES DIGITAL PLANES ROUTING INSTRUCTIONS: CLOCK LINE MUST ROUTE ON THE TOP LAYER, WITH NO VIAS. ATTEMPT TO MINIMIZE THE DISTANCE BETWEEN U4 CLOCK AND U2 CLOCK PINS. MATCH LENGTHS OF MAX100 TO '151 DATA BUS TO WITHIN ±0.500". TERMINATIONS FOR MAX100-TO-151 DATA BUS SHOULD BE PAST THE 151 PINS. DISTANCE FROM 151 PIN TO TERMINATION IS NOT CRITICAL. MATCH LENGTHS OF ;151-TO-EURO CONNECTOR BUS TO WITHIN ±0.500". DIV DIV MOD 5 R41 R40 50Ω A = B U5B MC100E11 DCLK 3 DCLK 4 PCK NCK 2 D2B 27 D2A 28 1 SEL2 2 SEL1 25 SEL3 NC 23 D3A 22 D3B D1A D1B U9 MC100E157 SEL0 D0A D0B NC 5 7 Q3 19 Q3 NC NC Q2 17 Q Q1 14 Q1 13 Q0 12 Q0 R45 50Ω FFCLK Figure 1. MAX100 EV Kit Schematic (continued)

7 FFCLK R24 R29 R30 R35 R3 R39 R20 25 B0 2 D5 A0 27 D4 B D3 A1 2 D2 B2 3 D1 A2 4 D0 R21 B3 2 D5 A3 27 D4 B D3 A4 2 D2 B5 3 D1 A5 4 D0 R22 R23 FFCLK MR 24 CPB 23 CPA O 0 20 NB0 Q5 19 PB0 Q5 21 PA2 7 Q0 NA2 8 Q0 PB2 9 Q1 NB Q MR 24 CPB 23 CPA O 25 2 D5 27 D4 A 28 1 D3 B7 2 D2 A7 3 4 D1 D0 U2 MC100E NB3 Q5 19 PB3 Q5 U3 MC100E151 PA5 7 Q0 NA5 8 Q0 PB5 9 Q1 NB5 10 Q1 MR 24 CPB 23 CPA O 7 Q Q5 19 Q5 U4 MC100E151 8 Q0 PA7 9 Q1 NA7 10 Q1 0 SIGNAL DISTRIBUTION LAYER DIGITAL AREA SIGNALS (-2V) (-5.2V) SIGNALS ANALOG AREA SIGNALS (+5V) (-5.2V) SIGNALS Figure 1. MAX100 EV Kit Schematic (continued) NA0 Q4 17 PA0 Q NB1 Q3 14 PB1 Q3 13 NA1 Q2 12 PA1 Q2 18 NA3 Q4 17 PA3 Q NB4 Q3 14 PB4 Q3 13 NA4 Q2 12 PA4 Q2 18 N Q4 17 P Q NA Q3 14 PA Q3 13 NB7 Q2 12 PB7 Q2 PB0 PA0 PB1 PA1 PB2 PA2 PB3 PA3 PB4 PA4 PB5 PA5 P PA PB7 9-PIN EURO CONNECTOR DATA DATA LABEL J4-A1 J4-A2 J4-A3 J4-A4 J4-A5 J4-A J4-A7 J4-A8 J4-A9 J4-A10 J4-A11 J4-A12 J4-A13 J4-A14 J4-A15 J4-A1 J4-A17 J4-B1 J4-B2 J4-B3 J4-B4 J4-B5 J4- J4-B7 J4-B8 J4-B9 J4-B10 J4-B11 J4-B12 J4-B13 J4-B14 J4-B15 J4-B1 J4-B17 NB0 NA0 NB1 NA1 NB2 NA2 NB3 NA3 NB4 NA4 NB5 NA5 N NA NB7 NA7 PA7 J4-A18 J4-B18 PCK J4-A19 J4-B19 NCK A = B J4-A20 DIV J4-B20 MOD J4-A21 J4-B21 J4-A22 J4-B22 J4-A23 J4-B23 J4-A24 J4-B24 J4-A25 J4-B25 J4-A2 J4-B2 J4-A27 J4-B27 J4-A28 J4-B28 J4-A29 J4-B29 J4-A30 J4-B30 J4-A31 J4-B31 J4-A32 J4-B32 J4-C1 J4-C2 J4-C3 J4-C4 J4-C5 J4-C J4-C7 J4-C8 J4-C9 J4-C10 J4-C11 J4-C12 J4-C13 J4-C14 J4-C15 J4-C1 J4-C17 J4-C18 B0 A0 B1 A1 B2 A2 B3 A3 D B4 A4 B5 A5 A B7 A7 J4-C19 CLOCK J4-C20 MODE J4-C21 RESERVED J4-C22 J4-C23 J4-C24 J4-C25 J4-C2 J4-C27 J4-C28 J4-C29 J4-C30 J4-C31 J4-C32 7

8 DCLK from MAX100 DATA at MAX100 DATA at D FLIP-FLOP INPUTS FIRST D FLIP-FLOP CLOCK OLD DATA 0.8ns (0.145ns/inch) (1.33" to 1.844") 1.0ns 2.4ns DIV = 0 2.0ns 3.0ns 4.0ns VALID DATA VALID DATA (2.7") + (220ps to 550ps) DATA HOLD TIME DIV = 1 DCLK from MAX100 DATA at MAX100 VALID DATA 1.4ns 0.1ns VALID DATA DATA at D FLIP-FLOP INPUTS VALID DATA FIRST D FLIP-FLOP CLOCK DATA HOLD TIME Figure 2. Evaluation Kit Timing 8

9 Copper Layer 1 Copper thickness = (1 oz copper) Epoxy FR4 Dielectric layer thickness = Copper Layer 2 Copper thickness = (1 oz copper) Epoxy FR4 Dielectric layer thickness = Copper Layer 3 Copper thickness = (1 oz copper) Epoxy FR4 Dielectric layer thickness = Copper Layer 4 Copper thickness = (1 oz copper) Epoxy FR4 Dielectric layer thickness = Copper Layer 5 Copper thickness = (1 oz copper) Epoxy FR4 Dielectric layer thickness = Copper Layer Copper thickness = (1 oz copper) Microstrip traces are 20 mils wide for 50Ω impedance. Figure 3. Layer Profile Figure 4. Main Board Component Placement Guide Component Side Figure 5. Main Board Component Placement Guide Solder Side Figure. Main Board Layout Copper Layer 1 (Top) 9

10 Figure 7. Main Board Layout Copper Layer 2 (negative image) Figure 8. Main Board Layout Copper Layer 3 (negative image) Figure 9. Main Board Layout Copper Layer 4 (negative image) Figure 10. Main Board Layout Copper Layer 5 (negative image) 10

11 .000" (152mm) NOTE: THE MAX100 CUT-OUT IS 1.18" SQUARE SIZE QTY SYM X Y 0 3 Z 5.000" (127mm) Figure 11. Main Board Layout Copper Layer (Bottom) Figure 12. Main Board Mechanical Outline TERM BOARD SIGNAL T1 F1 T2 F2 T3 F3 T4 F4 T5 F5 T F T7 F7 T8 F8 T9 F9 T10 F10 T11 F11 T12 F12 T13 F13 T14 F14 T15 F15 T1 F1 T17 F17 MAX100EVKIT SIGNAL B0 B0 A0 A0 B1 B1 A1 A1 B2 B2 A2 A2 B3 B3 A3 A3 B4 B4 A4 A4 B5 B5 A5 A5 A A B7 B7 A7 A7 DCLK DCLK MAX101EVKIT SIGNAL A0 A0 A1 A1 A2 A2 A3 A3 A4 A4 A5 A5 A A DCLK DCLK A7 A7 B7 B7 B5 B5 B4 B4 B3 B3 B2 B2 B1 B1 B0 B0 Figure 13. Termination Board Component Placement Guide and Signal Connections Component Side Figure 14. Termination Board Component Placement Guide Solder Side 11

12 2, 3 Figure 15. Termination Board Layout Layer 1 Figure 1. Termination Board Layout Layers 2, " (25.8mm) 4.500" (114.3mm) 50Ω MICROSTRIP LAYER PROFILE 0.020" 1OZ COPPER " FR4 E = " 1OZ COPPER " FR4 E = " 1OZ COPPER " FR4 E = " 1OZ COPPER 0.020" " Figure 17. Termination Board Layout Layer 4 (Bottom) Figure 18. Termination Board Mechanical Guide Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 9408 (408) Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.