Three-dimensional multi-terminal superconductive integrated circuit inductance extraction

Transcription

1 Three-dimensional multi-terminal superconductive integrated circuit inductance extraction Coenrad J Fourie 1, Olaf Wetzstein 2, Thomas Ortlepp 3 and Jürgen Kunert 2 1 Department of Electrical and Electronic Engineering, Stellenbosch University, Private Bag X1, 7602, South Africa 2 Institute of Photonic Technology (IPHT), Department of Quantum Detection, P.O. Box , Jena, Germany 3 Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, 231 Cory Hall, Berkeley CA coenrad@sun.ac.za Abstract. Accurate inductance calculations are critical for the design of both digital and analogue superconductive integrated circuits, and three-dimensional calculations are gaining importance with the advent of inductive biasing, inductive coupling and sky plane shielding for RSFQ cells. InductEx, an extraction programme based on the three-dimensional calculation software FastHenry, was proposed earlier. InductEx uses segmentation techniques designed to accurately model the geometries of superconductive integrated circuit structures. Inductance extraction for complex multi-terminal three-dimensional structures from current distributions calculated by FastHenry is discussed. Results for both a reflection plane modelling an infinite ground plane, and a finite segmented ground plane that allows inductive elements to extend over holes in the ground plane, are shown. Several SQUIDs were designed for and fabricated with IPHT s 1 ka/cm 2 RSFQ1D niobium process. These SQUIDs implement a number of loop structures that span different layers, include vias, inductively coupled control lines and ground plane holes. We measured the loop inductance of these SQUIDs and show how the results are used to calibrate the layer parameters in InductEx and verify the extraction accuracy. We also show that with proper modelling, FastHenry can be fast enough to be used for the extraction of typical RSFQ cell inductances. 1. Introduction The calculation of inductance remains important for digital and analogue superconductive electronic circuit design. Many numerical inductance calculation tools have been developed for integrated circuit elements [1]. Most techniques or tools are two-dimensional, sometimes with a combination of analytical models and curve-fitting [2], and fail for structures where the width-to-thickness ratio becomes small. Some methods support full three-dimensional analysis [3], [4] but are not integrated into software tools, or are limited to basic geometries [5]. Others do not readily incorporate ground planes and are better suited to high temperature SQUID geometries [6]. Lmeter [7], which is still the most widely used tool for the extraction of RSFQ circuit inductances, is integrated into computeraided design (CAD) software. It gives fast and reliable results for RSFQ circuits, but does not handle

2 Figure 1. (a) A single segment as used by FastHenry, with electrical node and filaments shown, (b) corner structure created when two segments as wide as conductors are connected at right angles and (c) corner structure when segments much smaller than conductor widths are connected. ground plane holes. 3D-MLSI [8] handles three-dimensional structures and ground plane holes, and can be integrated into CAD software, but is restricted to planar geometries. Published application of 3D-MLSI to RSFQ circuits is rare, and mostly for specific problems such as finding bias line coupling to circuit inductors [9]. With the advent of inductive biasing for energy efficient RSFQ circuits [10] and inductively coupled RSFQ cells for current recycling [11], [12], it is becoming increasingly important to calculate inductance of non-planar structures in the presence of ground plane holes. Moreover, it has been demonstrated that coupling between superconductive lines in integrated circuits permeate even thin shield layers [13], so that three-dimensional extraction is important for circuits fabricated in new multi-layer processes. InductEx, an extraction programme that allows inductance calculation for three-dimensional circuit structures, was proposed earlier [14]. InductEx is a pre-processor and post-processor for FastHenry [15] with superconductivity support [16]. InductEx discretizes the geometries for multi-terminal inductance networks in integrated circuits directly from GDSII input files, uses FastHenry to calculate current distribution, and calculates branch currents and lumped inductance values corresponding to specified circuit netlists during post-processing. InductEx is slower than the quasi-2d solver Lmeter [7], [1] for large structures such as circuits with multiple inductors. Although solution speed for all field solvers, including FastHenry and Lmeter, is strongly related to discretization size, the typical RSFQ digital cell discretized for FastHenry with the methods discussed in this paper contains about 20,000 50,000 filaments and solves 5 20 times slower than with Lmeter. (Lmeter s gain on FastHenry increases with model complexity.) However, through FastHenry, InductEx allows the modelling of vertical structures such as vias, non-planar effects, sky planes and holes in the ground plane. We show how InductEx is used to model IPHT s RSFQ1D superconductive integrated circuit process [17], how discretization and simulation parameters are selected for stability and short simulation times, and how calibration is performed to match extracted inductance values to results measured in SQUID modulation tests. The accuracy of the extraction routine is then verified by comparing extracted and measured results for typical RSFQ structures. Although results for FastHenry calculations on superconductive structures have been published before, none have ever examined the performance and accuracy over a range of structures or used FastHenry for multi-port networks. 2. Overview of FastHenry and InductEx (a) (b) (c) 2.1. FastHenry FastHenry is an established 3D inductance extraction tool developed originally for analysing general packaging structures [15]. For analysis, a structure is subdivided into discrete connected segments which can be divided further into filaments (see figure 1(a)). FastHenry then uses analytic solutions for the filaments and performs a mesh analysis on the structure to calculate the complex impedance between defined ports. The typical inductance extraction problem requires more than a few thousand filaments, which renders Gaussian elimination for the solution of the complex linear system impractical. Therefore an iterative generalized minimal residual (GMRES) algorithm [18] is implemented in FastHenry. A multipole algorithm, which groups together filaments in close proximity when calculating their interaction with elements that are at greater distances, further reduces

3 computation time and memory requirements. GMRES iteration convergence for the sparse matrix inversion is accelerated by the use of a preconditioner. FastHenry supports several preconditioners, but uses a sparsified-l cube-block preconditioner by default [15]. However, the performance of these preconditioners is modest compared to that of more recent methods [19], leaving room for future speed improvements FastHenry for superconductors. Early applications of field solvers to the analysis of superconducting structures involved solving with normal conductors at a frequency where the conductor skin depth matched the penetration depth of the superconducting material under consideration [20]. This method only accounts for magnetic inductance and correction factors are used to also incorporate kinetic inductance. Although MAXWELL [21] was used, Du concludes that the method extends to all normal metal field solvers [20], which includes FastHenry. Another implementation with FastHenry adds a kinetic inductance term to the inductance of every filament [22]. Inherent support for superconductivity was later added to FastHenry through the inclusion of the two-fluid London equations thereby accounting for both magnetic and kinetic inductance [16]. It is this version of FastHenry, with superconductivity support, that is used by InductEx. Confusion as to the difference between the normal metal version of Kamon [15] and the superconductor version of Whiteley [16] still exists, as evidenced by Kemppinen et al. [23] using the superconductor version of FastHenry to solve geometric inductance while solving kinetic inductance separately (thus solving it twice and presumably ambiguously), as well as Zen et al. [24] claiming to calculate only the magnetic inductance of Nb striplines with FastHenry from Whiteley Research [16] while citing Kamon [15] Accuracy and segmentation. Whiteley s FastHenry was found to agree very accurately [1] with an analytical formulation for inductance of a microstrip line [25]. However, its use of uniform current flow along one axis of a segment, and the interconnection of segments at nodes on this axis mean that three-axis interleaved segments are necessary to model current flow in bends, tees and vias (see figure 1(b) and 1(c)) when length-to-width ratios are small. Some recent work used FastHenry, backed by SQUID measurements, for the calculation of mutual inductors in integrated circuits [12], [13], but no indication of discretization or wider application to other circuit inductances is given. FastHenry cannot perform segmentation on structures other than a ground plane, therefore this is done in pre-processing with InductEx InductEx InductEx divides complex circuit structures into x, y and z-directed segments, while taking into account actual vertical offsets. Layout and process technology files are processed to generate input files for FastHenry, and InductEx allows modelling of both a finite ground plane with holes and a reflection plane at the effective penetration depth of the ground plane. Due to the computer resources required to extract inductances with FastHenry, earlier CAD implementations for superconductive integrated circuits used lookup tabulated results, calculated once with FastHenry, for the inductances of typical structures such as lines, corners, tees and vias [22]; much the same as the technique for semiconductor integrated circuits [26]. However, with a good segmentation algorithm, multiple port extraction and a proper preconditioner selection, typical RSFQ cells can be fully modelled and all the inductances extracted within minutes Port-to-port inductance calculation. FastHenry calculates the l l complex impedance matrix of an l-conductor network such as that shown in figure 2(a) if an external or input port is defined for every conductor either from end to end for partial inductance [27], or from one end of the conductor to the closest point on a ground plane for total loop inductance if a closed current return path exists. The self and mutual inductances of the l conductors are found by dividing frequency from the imaginary components of the inductance matrix.

4 When the inductances of integrated circuit cells are extracted, models often contain a multiterminal (also called a multi-port) network of lumped inductances such as that shown in figure 2(b). As long as there are no closed inductive loops, the simplest way to solve such a network is to calculate the inductance between all ports in sequence by specifying one external (or input) port to FastHenry while shorting a return port. This is done in pre-processing. For an m-port network containing k m m 1 inductors and no coupling, this requires FastHenry to be executed n times. The individual 2 inductances are found by solving the overdetermined system of linear equations Mb y (1) where M is a mostly zero (n k) matrix of which the column entries are 1 if the corresponding inductor forms part of the inductance calculated for a specific port-to-port row. The vector y contains the n calculated port-to-port inductances, while the vector b holds the k unknown lumped inductance values of the network. When more than one electrically isolated subnet is present, each subnet is solved through (1) by using only the ports and inductors belonging to it. Mutual inductance between two inductors in different isolated subnets can be found directly from the inductance matrix calculated by simultaneously specifying an input and return port in each subnet such that the current paths between the ports include the coupled inductors of interest, but no other inductors that have coupling. Although this method works, it requires multiple executions of FastHenry. This would not be a problem if FastHenry spends almost all the execution time on the iterative solver. However, for practical RSFQ cells, calculating the preconditioner requires more time than the iterative solver, which makes the method unnecessarily slow Inductance from port current calculation. A modification to the way in which FastHenry is executed provides a much faster alternative. If all m ports in a network are specified simultaneously, FastHenry attempts to solve an m m impedance matrix by driving one port at a time with a unity amplitude voltage while connecting zero volt sources over all the other ports. With multiple ports connected to the same network, this yields a meaningless impedance matrix. However, during postprocessing the network port currents can be calculated. If an inductive circuit netlist is available, the branch currents through every lumped inductor in the network can be calculated from the port currents. This method requires FastHenry to be executed only once for an m-port network. Consequently the preconditioner is also only calculated once. This method is substantially faster than m m 1 port-to-port calculation, although not exactly times, as the iterative solver is still called m 2 times and the preconditioner s performance is slower than with port-to-port models. Continuing with the arbitrary network of k inductors and m ports, we can apply Kirchhoff s voltage law around every loop in the network when port 1 is excited with a unity voltage, and repeat this for all m ports. This yields v 2 f Iz (2) where f is the excitation frequency used by FastHenry. All the components of voltage vector v equal 1 for loops containing the excited port and 0 otherwise. I is the (m(m 1) k) branch current matrix. In (2), z is the vector holding the k unknown inductance values which can be solved through singular value decomposition. In the general case where a circuit model contains any number of electrically isolated subnets with a total of k inductors, m ports (with a minimum of 2 ports per subnet) and any number of mutual inductances, such as the example shown in figure 2(c), vector z is expanded to include all the self and mutual inductances of the total network, while v is enlarged with zero components corresponding to zero-voltage loops in isolated subnets. The branch current matrix I is enlarged correspondingly, and the solution of (2) through singular value decomposition still holds. This method is now supported by InductEx, and is used for all results presented here.

5 (a) (b) (c) Figure 2. (a) Three-inductor network with self and mutual inductances solved readily with FastHenry, (b) multi-terminal inductance network solved with InductEx through 10 port-to-port FastHenry inductance calculations or a single FastHenry port current calculation and (c) multi-terminal inductance network with multiple electrically isolated subnets and mutual inductance solved through a single FastHenry port current calculation. 3. Discretization In order to build a numerical model for FastHenry, InductEx slices every figure in a layout into a grid of evenly-sized blocks in the xy plane so that no block dimension exceeds a specified maximum segment size. Connectivity is simplified by applying slices made to any figure to all other figures (also on other layers) bisected by the slice lines. We refer to the technique as layered cake slicing, and it is described graphically and in more detail in [14]. Where current density gradient is steep, such as at line edges or on the inside of corners, narrower slices can be enforced by the user through the layout input file. We use this to define the lambda edge segments described in Section 3.1. Nodes are declared in the centre of each block, and these are connected through segments in the x and y directions. Segments in the z direction are only used at vias to connect different metal layers. Segments in the xy plane can be subdivided into height filaments (see figure 1(a)) to model nonuniform current density in layers thicker than the penetration depth. When a structure is discretized for processing with FastHenry, a careful selection of segment size is necessary. The uniform current distribution applied by FastHenry over filaments causes large inaccuracies for structures with bends and short arms, as well as for superconducting structures where most current flows close to the surface or edges. Making segments too large causes results that are artificially high. Although calculated results can be adjusted closer to measured values through calibration, such solutions are not stable, and changes to segment size enforced by geometry can cause large variations. It has earlier been reported that a stable solution could be obtained by using more than 15 segments across the width of any arm of a structure [22]. This is excessive, and a more methodical investigation is needed. A series of simulations on several structures show that the inductance solution calculated by FastHenry decreases asymptotically for finer discretization until the segment size reaches the London penetration depth ( ) of the superconductor. For typical niobium-based superconductor circuits, the penetration depth is in the order of 10-1 m, while line widths are in the order of 10 1 m and cells in the order of 10 2 m. The practical limit for FastHenry 3.0wr, which was compiled for a 32-bit address space, is just below 10 5 filaments, for which the mesh matrices and preconditioner require 2 GB of memory. This makes discretization at 0.1 m impossible for any structure larger than a short inductor over ground. A more efficient discretization strategy is thus necessary Lambda edge segments One way to mitigate the cost of discretization is to use non-uniform segments [5], where segments at the edge of a structure are approximately wide, while the rest of the structure is segmented coarsely. Figure 3 shows the current distribution over the cross section of a superconducting microstrip line above a superconducting ground plane as calculated by FastHenry when the structures are segmented at 0.1 m, 1 m and 1 m with lambda edge segments. In the simulation, = 90 nm. It can be seen from figure 3 that the use of lambda edge segments allows FastHenry to approximate the current

6 distribution much better than with coarse segments, especially at the edges, with a minimal increase in segments Filaments IPHT Jena s RSFQ1D [17] foundry process for RSFQ circuits, used for experiments described in this paper, comprises three superconducting niobium layers. The first layer (M0, 200 nm thick) serves as a ground plane, while both upper niobium layers are used for wiring. Both the lower wiring layer (M1, 250 nm thick), and the upper wiring layer (M2, 350 nm thick) are thicker than the penetration depth. However, since there is no current flow in the vertical direction except near vias, it would be unnecessarily expensive to create multiple segments over the height of the lines and connect these with vertically directed segments. A much more efficient solution for allowing current density variation over the thickness of a line is to use FastHenry s built-in ability to create multiple height filaments (which obviates the need to connect vertically). Figure 3. Current distribution in the lowest filaments of a superconducting conductor and the highest filaments in a ground plane as calculated by FastHenry. The line is 4 m wide, is 90 nm and thickness is irrelevant. The graphs show the current distribution, from top to bottom, when 70 homogenous 0.1 m segments, 8 homogenous 1 m segments, and 1 m segments with 0.1 m lambda edges (10 segments in total) are used Effects of discretization on calculation results and time An experiment into the stability of solutions at different discretization levels has been done for structures with typical dimensions for niobium integrated circuits. The structures are shown in figure 4. The first is a short line structure, 4 m wide by 10 m long (figure 4(a)). The second is a 4 m wide line with a corner and arms extending 5 m on each end (figure 4(b)). Both structures have a 0.1 m thick ground plane. Calculations for both structures show a decrease in inductance as segment size is decreased. Figure 5 shows the results (normalised to the smallest solution) as segment size and height filament number are varied for both structures. Segment size refers to the largest permissible dimensions of any segment in the structure after discretization, and actual segment size is mostly slightly smaller to allow equal segment sizes across the width or length of a structure. InductEx still employs segmentation techniques described earlier [14]. For the simulation results shown in figure 5, where the conductor thickness is almost three times the penetration depth, it can clearly be seen that the results for both structures improve substantially with 2 and 3 height filaments, but stabilise thereafter. At three filaments, the conductor is divided into upper and lower sections each 75 nm thick, and a centre section that is 150 nm thick. The use of lambda segments also almost halves the initial inaccuracy of a solution, and makes solutions only half as sensitive to segment size variations as those with homogenous segments.

7 (a) (b) (c) Figure 4. Inductance structures, drawn to exact dimensions, used for calculating normalised inductance of superconductive conductors above a ground plane as a function of segmentation. (a) Straight line, (b) Corner and (c) U-shaped upper conductor coupled to straight lower conductor. The structures in (a) and (b) are not process specific, while (c) is for the IPHT RSFQ1D process. (a) Figure 5. Inductance of superconducting structures calculated with FastHenry, and normalised to the smallest solution for (a) a microstrip line 4 m wide and 10 m long and (b) a microstrip line 4 m wide with a corner and arms extending 5 m on each side of the bend. Both lines are 0.3 m thick and separated by 0.35 m from a 0.1 m thick ground plane extending 2 m beyond the line dimensions, and = 90 nm throughout. The stability of FastHenry solutions when models include mutual inductance was investigated for the structures in figure 4(c). The parameters for IPHT s 1 ka/cm 2 RSFQ1D niobium process were used, and the lower line (in layer M1) is 6 m wide and 25 long, with ports at both ends. The U- shaped upper line is in layer M2 and is 4 m wide. The ground plane is 200 nm thick, so that it was subdivided into height filaments along with the upper layers. The simulation results are shown in figure 6 as segment size and height filaments are changed in unison over all the superconducting layers. (b)

8 (a) (b) (c) Figure 6. Self and mutual inductance of two superconducting lines above a ground plane, as shown in figure 4(c), modelled for IPHT s 1 ka/cm 2 RSFQ1D niobium process, and calculated with FastHenry. Results are normalised to the smallest solution. (a) Self-inductance of a line in layer M1. (b) Selfinductance of a U-shaped line in M2. (c) Mutual inductance between the structures in M1 and M2. The ground plane extends 2 m beyond the M1 and M2 structures, and = 90 nm throughout. Height filamentation is applied simultaneously over layers M0, M1 and M2. The key applies to all the graphs. It can be seen from figure 6 that coarse segmentation and single height filaments cause results that differ by almost 15 % from the asymptotic values. Although this can be adjusted with calibration, the problem is that complex geometries cause uneven segmentation as segments are aligned to geometry edges. This results in accuracy fluctuations internal to a structure that cannot be corrected through calibration. It is clear that, for the IPHT RSFQ1D process, the use of 3 height filaments and lambda edge segments gives a much more stable result (mostly within 2.5 % of the asymptotic value) than simply decreasing the homogenous segment size by a factor of three. The solution times versus segment size and filament count for the above simulations are shown in figure 7. For the cases discussed here, using 3 height filaments and lambda edges with coarse (2 m) segments is on average 4 times faster than using finer homogenous, single-filament segmentation to obtain the same accuracy. The reason is visible in the graphs: solution time scales much more strongly for decreasing segment size than for increased filament count, mostly because halving the segment size quadruples the number of interleaved segments in the x and y directions, but also because FastHenry preconditions problems with multiple filament segments faster than those with the equivalent amount of elements consisting only of single filament segments.

9 (a) (b) (c) Figure 7. Solution time in seconds versus segment size for (a) the straight line structure of figure 4 and (b) the corner line of figure 4, both solved with FastHenry s sparsified-l cube-block preconditioner, and (c) the coupled inductors of figure 4 solved with the sparsified-l diagonal-of-l preconditioner. Figure 8 shows solution time for the models discussed above against the total number of discrete elements (segments and filaments). For models with fewer than 1000 elements, solution time is mostly faster than 10 seconds and quicker when segments have fewer filaments. Solutions with the sparsified- L cube-block preconditioner are also quicker than with the sparsified-l diagonal-of-l preconditioner, because the GMRES algorithm does not converge as quickly for the latter (in this element range the GMRES algorithm takes more time than the preconditioner), and the model used for this experiment has double the number of ports than those used for the cube-block problems. Figure 8 also shows that when models contain more than 10 4 elements, which is typical for RSFQ cells segmented as described here, using segments with multiple filaments is more economical than simply using more segments to improve accuracy. Furthermore, use of the diagonal-of-l preconditioner gives faster solutions than some calculations with the cube-block preconditioner. Above 10 4 elements the preconditioner dominates the calculation time, and a trade-off between preconditioner time (diagonal-of-l is faster than cube-block for models of typical RSFQ geometries) and convergence time (GMRES takes 2-3 times longer to converge after preconditioning with diagonal-of-l rather than cube-block) can be made.

10 Figure 8. Solution time in seconds versus total number of elements (segments and filaments) for the straight line, corner and coupled inductor structures. The straight line and corner structures were solved with FastHenry s sparsified-l cube-block preconditioner, and the coupled structure with the sparsified-l diagonal-of-l preconditioner. 4. SQUID structures and test setup 4.1. Calibration structures We use the IPHT RSFQ1D process, with two superconductive metal layers (M1 and M2) above a ground plane. An inductive structure above the ground plane is typically realised in M1 or M2. The inductance between the two Josephson junctions of a dc SQUID is easy to measure accurately [28], and three standard test SQUIDs (with shunted junctions) are used: one with the loop inductor in M1, another with the inductor in M2 (see figure 9(a) and 9(b)), and a third with an inductor that spans M1 and M2 and includes vias (see figure 9(c) and 9(d)). Loop inductance is measured at 4.2 Kelvin in liquid helium by biasing the SQUID in the voltage state. In a constant external magnetic field, the SQUID voltage is modulated by the application of a swept modulation current flowing through the SQUID inductance. The voltage is periodic, and the change in modulation current that sweeps out one period is equal to 0 divided by the loop inductance Test structures An array of test SQUIDs was fabricated with which to verify the accuracy of InductEx and FastHenry. This includes a SQUID with a longer M2 conductor (of about 20 ph), two SQUIDs for mutual inductance measurement (one with the loop inductor in M2 and the control line in M1 as shown in figure 9(g) and 9(h), and the other with the layer order inverted), and two SQUIDs with inductors that loop over cut-outs in the ground plane (one in M1, as shown in figure 9(e) and 9(f), and one in M2).

11 (a) (b) (c) (d) (e) (f) (g) Figure 9. Segmented models and microphotographs of some of the SQUID inductances extracted for this experiment. (a) Model of M2 calibration SQUID, with 10 m wide loop inductor in metal layer M2, and image (using a reflection plane) and (b) M2 calibration SQUID microphotograph. (c) Model of calibration SQUID with vias and a 10 m wide loop inductor transitioning between layers M2 and M1, with ground plane included, and (d) VIA calibration SQUID microphotograph. (e) Model of SQUID with inductor in M1 (12.5 m wide) looping over a hole in the ground plane to form an enclosed hole of 12.5 m 10 m, and (f) microphotograph SQUID with ground plane hole. (g) Model of SQUID with 15 m wide loop inductor in M2 and 10 m wide control line passing between loop inductor and ground plane in M1, and (h) microphotograph of SQUID with coupled control line. All models are segmented to smaller than 2.5 m (x-y interleaving causes a perceived grid of 1.25 m) with 0.1 m segments at edges. Shunt resistors are not modelled, and vias to ground are approximated by line ports to reduce segment count. For image clarity, subdivision into height filaments is omitted and vertical dimensions are enlarged 5 times. (h)

12 (a) (b) Figure 10. Inductance extraction circuit schematic diagrams for (a) the four-port model describing the SQUIDs in figure 9(a), 9(c) and 9(e), and (b) the six-port model, with isolated control line, describing the SQUID in figure 9(g). 5. Numerical modelling and extraction Except for the mutual inductance models which have 6 ports each (figure 10(b)), the FastHenry models for the test SQUIDs include the Josephson junction geometries and 4 ports two at the modulation current inputs and two at the ground contacts near the junctions (see figure 10(a)). The IPHT RSFQ1D process is modelled as shown in table 1. The model is simplified, and loss of thickness in M0 and M1 due to anodisation is not accounted for since the exact thicknesses of the metal layers vary after fabrication. Calibration is used to remove most of this inaccuracy. Table 1. IPHT RSFQ1D layer definitions. Description Name Thickness (nm) (nm) Ground M Isolation I0A, I0B First wiring layer M Isolation I1B, I Second wiring layer M A segment size of 2.5 m is selected as the standard setup (except near junctions, where layouts do not adhere to this grid). When the ground plane is included in the analysis, all inductive structures are modelled with a ground plane extending 2 m beyond the furthest edges of the structures, as shown in figure 9(c), 9(e) and 9(g). 6. Using image theory to model infinite ground plane We found that when the ground plane surrounding an inductor extends beyond its edges more than a few times the height of the conductor, it is equally accurate to model the ground plane as infinite. Using image theory, this is done with a reflection plane and a mirror image of the inductor. The reflection plane is not placed at the top of the ground plane, but at the effective penetration depth of the ground plane [4]. With this method the kinetic inductance of the ground plane is disregarded, but the effect is not substantial for typical RSFQ inductances. Calculated inductance is divided by 2 to remove the loop area between the reflection plane and the image, as well as the kinetic inductance of the image conductor. For the oblong test structures presented in this paper the computation time is very similar to when a ground plane is used, but for typical RSFQ cells with almost square layouts and higher ratios of ground plane to conductor segments, the computation time is 2 5 times shorter with a reflection plane.

13 A failure of image theory in partial inductance calculation has recently been reported [29], and correction factors proposed. However, this is only problematic when a single inductance is decomposed into smaller parts of which the return paths are not known a priori, and the partial inductances of the parts then solved individually. We will show that, after calibration, the method of images yields calculation results that are as good as those obtained with ground planes. 7. Calibration Although fabricated circuits differ from designs with respect to layer thickness of all the metal and isolation layers, adjusting all of these to match numerical calculations to measurements is cumbersome. We rather calibrate the numerical calculations against measurements by only adjusting the penetration depths of layers M1 and M2 ( M1 and M2 ), which mostly affects the kinetic inductance. For calibration we use SQUIDs with loop inductors in M2 (figure 9(a)), M1, and both layers connected with vias (figure 9(c)). We start by adjusting M1 and M2 separately until the numerical and measured results for the M2 and M1 SQUIDs agree to within 0.5 %. Then the result for the via SQUID (with the inductor spanning M1 and M2) is calculated and compared to its measured value. The root mean squared error (RMSE) between the three calculations and measurements is then minimised through two or three cycles of incremental changes in M1, M2. Recalibration is necessary whenever structures on a new wafer are analysed. The resulting penetration depths used for inductance calculation account for all process tolerances, offsets and calculation inaccuracies, and are therefore artificial (they do not reflect the actual penetration depths). 8. Results We tested chips from two identical fabrication runs with nominal parameters from IPHT Jena. The fabrication runs are labelled run 1 and run Calibration structures from fabrication run 1 The accuracy of the calculation and calibration process was tested with structures fabricated with run 1 from IPHT. Segment size is 2.5 m, with lambda edge segments of 0.1 m. Ground plane segments have 2 height filaments, and conductor segments have 3. Uncalibrated calculations are done with the parameters in table 1, and have an RMSE of 10.8 % compared to the measured results. After calibration, calculated inductances for the three structures are found to agree to the measured results with an RMSE of 1.05 %, while M1 = 104 nm and M2 = 195 nm. The results and errors after calibration are listed in table 2. The input inductance of a DC-SFQ converter is then calculated as 3.76 ph, which differs only 0.3 % from the measured value of 3.75 ph. The results are consistent with the three-digit inductance measurement accuracy and fall within the guaranteed on-chip inductance homogeneity of 2 % for the process [17]. Table 2. Measured and extracted inductance results for calibration structures from fabrication run 1 with ground plane in simulation model and lambda edge segments. Height filaments for layers are: M0 = 2, M1 = 3 and M2 = 3. The first three structures were used for calibration. Inductor Measured (ph) Uncalibrated (ph) Calibrated (ph) Error (%) M % M % M1-M % DCSFQ-in %

14 8.2. Full array of test structures from fabrication run 2 A more detailed experiment was done with fabrication run 2. The full array of test structures described in section 4.2 was distributed over 4 chips. For calibration, the M2, M1 and via SQUIDs on chip 1 were used, as well as a duplicate M2 SQUID on chip Ground plane in simulation model. A ground plane extending 2 m beyond the extremities of the inductors, and with 2 height filaments per segment, is used. Segment size is 2.5 m, with lambda edge segments of 0.1 m. Conductor segments in layers M1 and M2 have 3 height filaments. Uncalibrated calculations are done with the parameters in table 1, and have an RMSE of 5.2 % compared to measurements. After calibration, M1 = 83 nm and M2 = 140 nm, with an RMSE of only 0.45 % for the four calibration structures. The results are listed in table 3. For comparison, the calculations were repeated for models without lambda segments but with the same number of height filaments as above, and then for models without any lambda segments or filament subdivision. These results are listed in table 4. Table 3. Measured and extracted inductance results for fabrication run 2 inductors with ground plane in simulation model and lambda edge segments. Height filaments for layers are: M0 = 2, M1 = 3 and M2 = 3. The inductors on Chip 1 and the first inductor on Chip 2 were used for calibration. Chip Inductor Measured (ph) Uncalibrated (ph) Calibrated (ph) Error calibrated to measured (%) 1 M2 a M M1-M M2 a L 11 in M2 b M M2-M1 b L 11 in M1 c M M1-M2 c M M2 hole d M1 hole e M M1-M M2 a a Duplicate structure on different chips. b Structure shown in figure 9(g), with SQUID loop in M2 and control line in M1. c Structure with SQUID loop in M1 and inductively coupled control line in M2. d SQUID with loop inductor in M2 spanning hole in ground plane. e SQUID with loop inductor in M1 spanning hole in ground plane as show in figure 9(e) Reflection plane in simulation model. The accuracy of the method of images was evaluated by repeating the inductance calculations for all the structures except the two with ground plane holes. Calculation models use lambda edge segments and 3 height filaments to every conductor segment. After calibration, M1 = 88 nm and M2 = 146 nm, with an RMSE of only 0.43 % for the four calibration structures. This very good agreement with the calibration parameters and RMSE of the

15 ground plane calculations not only validates the correctness of the method of images, but also that of the reflection plane position proposed by Teh et al. [4]. The results are listed in table 5. Table 4. Extracted inductance results for fabrication run 2 inductors with ground plane in simulation model and uniform segments. Error percentage is the difference between calibrated calculation results and the measurements listed in table 3. Inductors correspond to those listed in table 3. The inductors on Chip 1 and the first inductor on Chip 2 were used for calibration. Chip Inductor Uncalibrated (ph) Height filaments in M0 = 2, M1 = 3, M2 = 3 Calibrated (ph) Error (%) Uncalibrated (ph) Height filaments in M0 = 1, M1 = 1, M2 = 1 Calibrated (ph) Error (%) 1 M M M1-M M L 11 in M M M2-M L 11 in M M M1-M M M2 hole M1 hole M M1-M M Discussion of results. A comparison of the values for M1 and M2 used to calibrate the four calculation methods is shown in table 6, along with the RMSE of the calculations compared to the measurements for every method. RMSE is calculated for only the calibration structures, then for all the self and mutual inductances of the test structures excluding the two with ground plane holes, and finally for all inductances calculated with ground plane methods. The calculation results for the filamented methods both with and without lambda segments agree very well with measured values and with each other. All inductance errors for the calibration chip are within the 2 % on-chip homogeneity and all errors across the 4 chips within the 5 % to 6 % range for on-wafer homogeneity guaranteed by the foundry, with the exception of the inductor in M2 across a ground plane hole. Although the use of lambda edge segments gives more stable calculation results as shown in figures 6 and 7, as well as better RMSE values as shown in table 6, the experiments described here do not show a conclusive advantage over uniform segmentation after calibration. Fortunately, lambda segments do not add a significant amount of elements to a model, and computation times for methods with and without these segments are similar. The results in tables 4 and 6 do show that models with single height filaments, although faster than models with more filaments, produce substantially worse calculation results. Even for the calibration structures, the kinetic inductance of layer M1 needs to be disregarded almost completely to produce a

16 good fit between simulations and measurements, while the inaccuracy is very evident for the mutual inductance. Table 5. Measured and extracted inductance results for fabrication run 2 inductors with lambda edges and reflection plane in simulation model. Height filaments for layers are: M0 = 2, M1 = 3 and M2 = 3. Error percentage is the difference between calibrated calculation results and the measurements listed in table 3. Inductors correspond to those listed in table 3. The inductors on Chip 1 were used for calibration. Chip Inductor Measured (ph) Uncalibrated (ph) Calibrated (ph) Error (%) 1 M M M1-M M L 11 in M M M2-M L 11 in M M M1-M M M M1-M M Table 6. Calibrated penetration depth values and root-mean-square errors. Parameter Lamda segments, multiple height filaments, ground plane Lambda segments, multiple height filaments, reflection plane Uniform segments, multiple height filaments, ground plane Uniform segments, single height filaments, ground plane M2 140 nm 146 nm 134 nm 90 nm M1 83 nm 88 nm 79 nm 25 nm RMSE (calibration structures only) RMSE (all except ground plane holes) 0.45 % 0.43 % 0.47 % 1.24 % 2.02 % 1.56 % 2.75 % 7.64 % RMSE (all) 5.06 % % 8.10 % The calculated value of the loop inductor in layer M2 over a ground plane hole differs about 15 % from the measured result. The inductance is primarily a function of the loop area, which is defined by the square hole between the M2 inductor and the edge of the ground plane, and is thus not very sensitive to calibration as we implement it through variation of the penetration depth. Calculations with the lambda edge segment method were done for a range of misalignments between the ground plane and M2, which effectively varies the loop area. The results are listed in table 7, and show that the inductance of this structure is a function of mask alignment, but not enough to explain the 15 %

17 difference between calculation and measurement. Experiments are planned to obtain more data points for such structures and to draw better conclusions on the accuracy of FastHenry calculations for inductors over ground plane holes. Table 7. Variation of calculated inductance of an M2 inductor over ground plane hole as a function of M2-M0 misalignment. Misalignment ( m) Inductance variation (%) Conclusion We showed that a proper modelling of a multi-terminal inductive structure with the methods incorporated into InductEx allows FastHenry to obtain very accurate calculation results that can be post-processed to find lumped inductance values. Using port currents and good segmentation, FastHenry calculations can be as versatile as those done with Lmeter for RSFQ circuits, with the added advantage that holes in the ground plane are also supported. We furthermore showed that the calculation results can be calibrated to give results with RMSE values smaller than 1 % for inductance on a single chip and around 2 % for self and mutual inductance over a wafer (excluding inductors over ground plane holes) both of which are comparable to the measurement accuracy and smaller than the guaranteed process homogeneity. Inductance calculations for inductors over ground plane holes differ by 5 % to 15 % from measured values, but only two test structures were available. These results are better than the 20 % to 30 % error reported for FastHenry calculations of coupled structures over a ground plane hole [12], but suggest that our modelling of such structures could be further improved. The use of lambda edge segments when segment size exceeds the penetration depth by an order of magnitude or more clearly yields more accurate results (at the cost of increased computing time) in theory. However, during practical measurements and calibration the accuracy advantage is overwhelmed by process variations. More practical measurements are required to verify if this is always the case, but we can already suggest that such segments are not necessary for layout extraction. We can thus conclude that the use of large segments (as opposed to the recommendation of very fine segmentation [22]) with multiple height filaments, port current calculations and proper preconditioners in FastHenry yields very accurate solutions for the lumped inductance of multiterminal structures typical of RFSQ cells. For IPHT layouts, we suggest 2.5 m segment size, 2 height filaments for M0, and 3 height filaments for layers M1 and M2. The computation time for the extraction of all the inductance in such cells typically falls in the range of 10 2 to 10 3 seconds with a single processor, which makes full cell inductance extraction possible with computer-aided design software. Acknowledgment The authors wish to thank Retief Gerber and Jan Pool at NioCAD for their help in modifying FastHenry. References [1] Gaj K, Herr Q P, Adler V, Krasniewski A, Friedman E G and Feldman M J 1999 Tools for the computer-aided design of multigigahertz superconducting digital circuits IEEE Trans. Appl. Supercond [2] Xiao P H, Charbon E, Sangiovanni-Vincentelli A, Van Duzer T and Whiteley S R 1993 INDEX: An inductance extractor for superconducting circuits IEEE Trans. Appl. Supercond [3] Nakazato T and Okabe Y 1997 Inductance computation of microscopic superconducting loop

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