MONOLITHIC GATED DELAY LINE OSCILLATOR (SERIES 3D7702)
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1 MONOLITHIC GATED DELAY LINE OSCILLATOR (SERIES 3D7702) FEATURES All-silicon, low-power CMOS technology TTL/CMOS compatible inputs and outputs Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Frequency range: 0.3MHz through 100MHz Frequency tolerance: 0.5% typical Temperature stability: ±1.5% typical (-40C to 85C) Vdd stability: ±0.5% typical (4.75V to 5.25V) 14-pin DIP available as drop-in replacements for hybrid delay line oscillator (DLO32F) PACKAGES 3D7702Z-xx SOIC-8 3D7702-xx 3D7702K-xx D7702 DIP-14 pins removed For mechanical dimensions, click here. For package marking details, click here. FUTIONAL DESCRIPTION PIN DESCRIPTIONS The 3D7702 Delay Line Oscillator product family consists of fixedfrequency CMOS integrated circuit oscillators. Each package contains a single oscillator, which is gated and can therefore be synchronized to an external signal. The device frequency can range from 0.3MHz through Oscillator Enable Oscillator Output 1 Oscillator Output 2 +5 Volts 100MHz. The 3D7702 has two outputs that are 180 out-of-phase when Ground the oscillator is running, and can be used as a drop-in replacement for the DLO32F hybrid oscillator. The 3D7702 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads. It is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC package. Doc #06024 DATA DELAY DEVICES, I. 1
2 TABLE 1: PART NUMBER SPECIFICATIONS DASH OUTPUT FREQUEY (MHz) NUMBER 25C Vdd=5.00V -40C to 85C 4.75<Vdd< ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± 7.00 NOTE: Any dash number between 0.3 and 100 not shown is also available as standard Data Delay Devices Doc #06024 DATA DELAY DEVICES, I. 2 12/5/2006 Tel: Fax:
3 APPLICATION NOTES OPERATIONAL DESCRIPTION The 3D7702 delay line oscillator architecture is shown in Figure 1. The internal delay line is composed of a number of delay cells connected in series and is compensated for thermal and supply voltage variations. A low-going edge on the input starts the oscillator, with the output responding immediately. The output is delayed by ½ cycle. The response of the output when the oscillator is disabled depends on the status of when the signal goes high, as shown in Figure 2. If is low, it will remain low, and the final pulse on will be ½ of the period. If is high, it will go low as soon as goes high, and the final pulse on both outputs will have a width smaller than ½ the period. Temp & Vdd Compensation Delay Line Figure 1: 3D7702 Functional Diagram Figure 2: 3D7702 Timing Diagrams Doc #06024 DATA DELAY DEVICES, I. 3
4 APPLICATION NOTES (CONT D) POWER SUPPLY AND TEMPERATURE CONSIDERATIONS The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The monolithic 3D7702 oscillator utilizes novel and innovative compensation circuitry to minimize the frequency variations induced by fluctuations in power supply and/or temperature. The thermal coefficient is reduced to 250 PPM/C, which is equivalent to a variation, over the -40C to 85C operating range, of ±1.5% from the roomtemperature frequency setting. The power supply coefficient is reduced, over the 4.75V to 5.25V operating range, to ±0.5% of the frequency setting at the nominal 5.0VDC power supply. These specifications hold for the lower frequencies only. For higher dash numbers, the variations will be slightly greater, as noted in Table 1. It is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. DEVICE SPECIFICATIONS TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNITS NOTES DC Supply Voltage V DD V Input Pin Voltage V IN -0.3 V DD +0.3 V Input Pin Current I IN ma 25C Storage Temperature T STRG C Lead Temperature T LEAD 300 C 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (-40C to 85C, 4.75V to 5.25V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Static Supply Current* I DD ma High Level Input Voltage V IH 2.0 V Low Level Input Voltage V IL 0.8 V High Level Input Current I IH 1.0 µa V IH = V DD Low Level Input Current I IL 1.0 µa V IL = 0V High Level Output Current I OH ma V DD = 4.75V V OH = 2.4V Low Level Output Current I OL ma V DD = 4.75V V OL = 0.4V Output Rise & Fall Time T R & T F ns C LD = 5 pf *I DD (Dynamic) = 2 * C LD * V DD * F Input Capacitance = 10 pf typical where: C LD = Average capacitance load/output (pf) Output Load Capacitance (C LD ) = 25 pf max F = Device frequency (GHz) Doc #06024 DATA DELAY DEVICES, I. 4 12/5/2006 Tel: Fax:
5 SILICON DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: OUTPUT: Ambient Temperature: 25 o C ± 3 o C R load : 10KΩ ± 10% Supply Voltage (Vcc): 5.0V ± 0.1V C load : 5pf ± 10% Input Pulse: High = 3.0V ± 0.1V Threshold: 1.5V (Rising & Falling) Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V Device 10KΩ Digital ) Under Scope Test 470Ω 5pf NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. COMPUTER SYSTEM PRINTER PULSE GERATOR OUT TRIG DEVICE UNDER TEST (DUT) REF IN TRIG FREQUEY/ TIME INTERVAL COUNTER Figure 3: Test Setup 2.4V 1.5V 0.6V t FALL V IL t RISE 2.4VV IH 1.5V 0.6V t B 1/f OSC t DIS 1.5V 1.5V 1.5V Figure 4: Timing Diagram Doc #06024 DATA DELAY DEVICES, I. 5
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C4 oltage Controlled Crystal Oscillator Features ectron s Smallest CXO, 5.0 X 3.2 X 1.2 mm High Frequencies to 77.70 MHz 5.0 or 3.3 operation Linearity 10% Tri-State Output for testing Low jitter < 1ps
CLK_EN CLK_SEL. Q3 THIN QFN-EP** (4mm x 4mm) Maxim Integrated Products 1
19-2575; Rev 0; 10/02 One-to-Four LVCMOS-to-LVPECL General Description The low-skew, low-jitter, clock and data driver distributes one of two single-ended LVCMOS inputs to four differential LVPECL outputs.
78A207 MFR1 Receiver DATA SHEET DESCRIPTION FEATURES OCTOBER 2005
DESCRIPTION The 78A207 is a single-chip, Multi-Frequency (MF) receiver that can detect all 15 tone-pairs, including ST and KP framing tones. This receiver is intended for use in equal access applications
HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J
Data Sheet HCPL-9000/-0900, -9030/-0930, HCPL-901J/-091J, -902J/-092J Description The HCPL-90xx and HCPL-09xx CMOS digital isolators feature high speed performance and excellent transient immunity specifications.
High Speed, +5 V, 0.1 µf CMOS RS-232 Drivers/Receivers ADM222/ADM232A/ADM242*
a FEATURES 00 kb/s Transmission Rate Small (0. µf) Charge Pump Capacitors Single V Power Supply Meets All EIA--E and V. Specifications Two Drivers and Two Receivers On-Board DC-DC Converters ± V Output
NTE4016B & NTE4016BT Integrated Circuit CMOS, Quad Analog Switch/Quad Multiplexer
NTE4016B & NTE4016BT Integrated Circuit CMOS, Quad Analog Switch/Quad Multiplexer Description: The NTE4016B (14 Lead DIP) and NTE4016BT (SOIC 14) quad bilateral switches are constructed with MOS P channel
General Purpose Clock Synthesizer
1CY 290 7 fax id: 3521 CY2907 General Purpose Clock Synthesizer Features Highly configurable single PLL clock synthesizer provides all clocking requirements for numerous applications Compatible with all
LOW SKEW 1 TO 4 CLOCK BUFFER. Features
DATASHEET ICS651 Description The ICS651 is a low skew, single input to four output, clock buffer. Part of IDT s ClockBlocks TM family, this is a low skew, small clock buffer. IDT makes many non-pll and
Pin Connection (Top View)
TOSHIBA TC551001BPL/BFL/BFTL/BTRL-70L/85L SILICON GATE CMOS 131,072 WORD x 8 BIT STATIC RAM Description The TC551001BPL is a 1,048,576 bits static random access memory organized as 131,072 words by 8 bits
DS1642 Nonvolatile Timekeeping RAM
www.dalsemi.com Nonvolatile Timekeeping RAM FEATURES Integrated NV SRAM, real time clock, crystal, power fail control circuit and lithium energy source Standard JEDEC bytewide 2K x 8 static RAM pinout
M74HCT04. Hex inverter. Features. Description
Hex inverter Features High speed: t PD = 11 ns (typ.) at =4.5V Low power dissipation: I CC = 1 μa (max.) at T A =25 C Compatible with TTL outputs: V IH = 2 V (min.) V IL = 0.8 V (max) Balanced propagation
Supertex inc. TP2510. P-Channel Enhancement-Mode Vertical DMOS FET TP5AW. Features. General Description. Applications. Ordering Information
TP251 P-Channel Enhancement-Mode Vertical DMOS FET Features Low threshold (-2.4V max.) High input impedance Low input capacitance (125pF max.) Fast switching speeds Low on-resistance Free from secondary
DS1720 ECON-Digital Thermometer and Thermostat
www.maxim-ic.com FEATURES Requires no external components Supply voltage range covers from 2.7V to 5.5V Measures temperatures from 55 C to +125 C in 0.5 C increments. Fahrenheit equivalent is 67 F to +257
ICS553 LOW SKEW 1 TO 4 CLOCK BUFFER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS553 Description The ICS553 is a low skew, single input to four output, clock buffer. Part of IDT s ClockBlocks TM family, this is our lowest skew, small clock buffer. See the ICS552-02 for
Programmable Clock Generator
Features Clock outputs ranging from 391 khz to 100 MHz (TTL levels) or 90 MHz (CMOS levels) 2-wire serial interface facilitates programmable output frequency Phase-Locked Loop oscillator input derived
VVC1 VVC2 Voltage Controlled Crystal Oscillator
VVC1 VVC2 Voltage Controlled Crystal Oscillator Features The VVC1 Voltage Controlled Crystal Oscillator VCXO with a CMOS output Small 5.0 X 7.0 X 1.9 mm package Output frequencies to 66 MHz 5.0 or 3.3
P54FCT373T/74fct373T OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS FEATURES DESCRIPTION. Function, Pinout and Drive Compatible with the FCT and F Logic
P54FCT373T/74fct373T OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS FEATURES Function, Pinout and Drive Compatible with the FCT and F Logic FCT-A speed at 5.6ns max (MIL) Reduced VOH (typically = 3.3 V)
IS62/65WV102416EALL IS62/65WV102416EBLL. 1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating (typical): - 10.8mW (1.8V), 18mW (3.0V) CMOS Standby (typical): - 48
DS14C238 Single Supply TIA/EIA x 4 Driver/Receiver
Single Supply TIA/EIA-232 4x4Driver/Receiver General Description The DS14C238 is a four driver, four receiver device which conforms to the TIA/EIA-232-E standard and CCITT V.28 recommendations. This device
MM5452/MM5453 Liquid Crystal Display Drivers
MM5452/MM5453 Liquid Crystal Display Drivers General Description The MM5452 is a monolithic integrated circuit utilizing CMOS metal gate, low threshold enhancement mode devices. It is available in a 40-pin