Operational Amplifiers: Theory and Design

Transcription

1 Operational Amplifiers: Theory and Design TU Delft, the Netherlands, November 6-10, 2017 All Rights Reserved 2017 MEAD Education SA 2017 TU Delft These lecture notes are solely for the use of the registered course Participants and Instructors teaching in the course. No part of these notes may be reproduced, stored in a retrieval system, or transmitted in any form or by any means (electronic, photocopying, microfilming, recording or otherwise) without written permission of MEAD Education SA, TU Delft or any of the Authors.

2 Lesson 1 A quick start Burak Gönen November

3 Hands-on Sessions There are totally 7 hands-on simulation sessions Ø Ø Ø Ø Ø Ø Ø Lesson 1: Introduction, Macromodels and Noise Lesson 2: Input stage Lesson 3: Output stage Lesson 4: Overall design Lesson 5: Two-stage configurations Lesson 6: Three-stage configurations Lesson 7: Fully differential amplifiers 2

4 Hands-on Sessions In each lesson, you will complete several assignments, which are divided into three levels: A, B and C Ø Ø Ø Assignments on Level A is for everyone Assignments on Level B is for higher level participants Assignments on Level C is for advanced participants A manual with simulation instructions and these presentation slides are included in the folders. Relax and keep yourself busy! When you are stuck, please ask for help! 3

5 The Simulation Tool: Cadence Virtuoso

6 Libraries The relevant Library for all the Hands-On Sessions is: OPAMP Cells Views Most assignments have a top cell schematic, or a test bench, to test the circuit under test. Library The relevant top cell and the circuits to be tested are shown for each assignment. 5

7 Simulation Models The models used in hands-on simulations are provided by NCSU Cadence Development Kit. In case you need to manually place them, the transistor cells are: NMOS = Library: NCSU_Analog_Parts, Cell: nmos4, View: symbol PMOS = Library: NCSU_Analog_Parts, Cell: pmos4, View: symbol Feature size is 0.3um For more information: 6

8 Adding Transistors 1 -Press I to insert a new instance Click Browse to see the Component Browser 3- Select the library, click flatten and select nmos4 or pmos Return back to Add Instance window to edit properties of the transistor Edit properties of the transistor 5- Make sure that the view is symbol 6- Your new transistor is ready! 7

9 Cadence Virtuoso: Beginners We are assuming for all participants to have a basic knowledge of designing and simulating in Cadence environment. For participants not familiar with the Cadence Virtuoso: There is a short Cadence tutorial included in handout. It explains how to open and edit a schematic, how to simulate and how to choose important parameters for simulation. You can also find detailed manuals on Cadence tools on your desktop. The first lesson is an excellent way to get acquainted with the tools. 8

10 Boyle Macromodels 9

11 Boyle Macromodels Input stage 10

12 Boyle Macromodels 1 st gain-stage 11

13 Boyle Macromodels 2 nd gain-stage 12

14 Boyle Macromodels Miller Compensation 13

15 Boyle Macromodels Output current limit 14

16 Boyle Macromodels Output saturation 15

17 Boyle Macromodels Common-mode feedback 16

18 Assignments - I Top Cell: 01_BoyleMacroModels Assignment 1 Level A Check DC biasing [ADE-L > Analyses > Choose > DC > Save DC Op.] Run AC simulation to see the open-loop gain of the amplifier Assignment 2 Level A Add a capacitive load, and run the AC again Check: DC gain, unity gain-bandwidth (UGBW), and phase-margin Set the load capacitance as a variable and run parameter analysis together with AC simulations to see the open-loop gain and phase margin [ADE-L > Tools > Parametric Analysis > Add Variable (Cap Name) > From/To: 1p/1u > Total Steps: 10] 17

19 Bode-Plots DC gain UGBW Phase-margin 18

20 Assignments - II Top Cell: 02_Applications_DynamicRange Assignment 4 Level A Here we have an inverting and an non-inverting amplifier. Please calculate the gain of the each amplifier Check the input common-mode voltages of the each amplifier What do you expect as output voltage? 19

21 Assignment III Top Cell: 02_Applications_DynamicRange Assignment 5 Level A Check DC biasing [ADE-L > Analyses > Choose > DC > Save DC Op.] Do the output voltages of the each amplifier correct? Can you comment on the virtual-ground voltages? Run AC simulation to see the closed gain of the amplifiers Do the results match with your expectations? 20

22 Assignment - IV Top Cell: 02_Applications_DynamicRange Assignment 6 Level A Run transient simulation [1s] to see the step response of the amplifier in closed loop configuration Observe the output voltages Observe the virtual-ground voltages Increase the input signal amplitude [V1=0 and V2=2.5V], and do the previous simulation again What difference you see compared to the previous case Please define the output range What is the maximum input range? Can you comment about the dynamic-range? 21