DESIGN OF ERROR AMPLIFIER FOR LDO

Transcription

1 ECEN 607 DESIGN OF ERROR AMPLIFIER FOR LDO PROJECT REPORT Rakesh Selvaraj [UIN XXX-XX-7544] Shriram Kalusalingam [UIN XXX-XX-2738] DEPARTMENT OF ELECTRICAL ENGINEERING

2 CONTENTS S.No TITLE Page No 1 OBJECTIVE 1 2 ABSTRACT 1 3 INTRODUCTION 1 4 BACKGROUND STUDY 2 5 PREVIOUS WORKS 9 6 PROPOSED SOLUTION 12 7 DESIGN PROCEDURE 15 8 ALTERNATIVE APPROACH 20 9 SIMULATION RESULTS FOR ERROR AMPLIFIER SIMULATION RESULTS OF LDO PERFORMANCE SUMMARY FOR ERROR AMPLIFIER PERFORMANCE SUMMARY FOR LDO COMPARISON OF RESULTS WITH OTHER WORK SUGGESTED IMPROVEMENTS & FUTURE WORKS LAYOUT REFERENCES 36

3 LIST OF FIGURES S.No TITLE PAGE NUMBER 1 Conventional LDO Architecture 2 2 Error Amplifier with NMOS Mirror Load 3 3 Small signal PSR model of NMOS mirror load Error Amplifier 3 4 PSR of Error Amplifier (With PMOS Mirror Load) 5 5 Error Amplifier with PMOS Mirror Load 6 6 Small signal PSR model of PMOS mirror load Error Amplifier 6 7 Typical plot of PSR of LDO 7 8 PSR of LDO with PMOS Pass Transistor and Error Amplifier with PMOS 8 Mirror load 9 Structure of UGCC 9 10 Structure of LDO with UGCC LDO with Cascoded Pass Transistor & charge pump Conventional LDO Architecture Compensation block at LDO output Compensation Block in feedback path compensation block at Error Amplifier output Subtractor circuit Overall circuit I Compensation block to improve PSR BW overall Circuit II AC Response of Error Amplifier with AC Response of Error Amplifier with PSRR of Error Amplifier with PSRR of Error Amplifier with Settling time for Settling time for AC response for loop with AC response for loop with Settling time for LDO with 0 to 50mA Settling time for LDO with 50mA to 0mA PSR of LDO with PSR of LDO with Load Regulation for LDO 28

4 LIST OF TABLES S.No TITLE PAGE NUMBER 1 Given Specification 1 2 Comparison of Error Amplifier Architectures 7 3 Comparison of Previous results 11 4 Summary of transistor sizes 19 5 Achieved Spec for Error Amplifier 28 6 Achieved Spec for LDO 29 7 Comparison with results of other work 29

5 OBJECTIVE To design an error amplifier for the LDO application with the following specifications using 0.5 technology. ABSTRACT PARAMETERS DESIRED VALUE > 60dB GBW > 2MHz Phase Margin > 60 PSRR > 1MHz Power Supply 3.5V Load Capacitance varies from 20pF to 80pF Current Consumption < 20μA Input Common Mode Voltage 1.2V Settling Time < 100ns TableI: Given Specification An error amplifier for LDO application has been designed with PSRR of 65 db 1MHz, settling time less than 100 ns for a varying capacitive load from 20 pf 80 pf in 0.5 technology. It consumes a current less than < 20 with 3.5 supply. This has been plugged into LDO capable of producing a regulated voltage of 3.33, with a dropout of 170. A novel block has been added between error amplifier and the pass transistor to improve the PSR of DC. There was remarkable improvement of PSR from 45 to 65. INTRODUCTION LDO has become a critical part in the analog circuit design due to the increased mobility and portability. It occupies an important part in the RF communication systems and the battery operated gadgets. The main challenge in the LDO is maintaining a constant voltage for the varying load. It has to effectively to reject the ripples coming from the supply voltage, thus ensuring a noise free voltage source to the other blocks. Both the DC and the bandwidth of the PSR have a tradeoff between them. Using PMOS mirror load error amplifier achieves a good DC, but a low bandwidth. On the contrary, using NMOS mirror load error amplifier achieves a bad DC, but a high bandwidth. In this work, a NMOS mirror load error amplifier has been used which has an inbuilt property of high bandwidth for PSR. To improve the DC, an extra circuit has been added between the error amplifier and the pass transistor. The introduction of this block has improved the DC from 45 t

6 BACKGROUND STUDY Most of the existing error amplifiers that are used in LDO have a single ended output. These architectures employ a current mirror load to perform the conversion from double ended to single ended output which adds the ac signals obtained at the output, which are obtained from the input differential pair. This can be implemented using a PMOS mirror that is connected to or an NMOS mirror connected to gnd. It will be found that the implementation of current mirror will have great impact on the PSR of the Error Amplifier and LDO as well. Conventional architecture of LDO is as shown below. Figure 1: Conventional LDO Architecture 2

7 TOPOLOGY I Consider the conventional error amplifier which has a NMOS input differential pair with PMOS load. Figure 2: Error Amplifier with NMOS Mirror Load The small signal PSR model of this error amplifier is shown below. Figure 3: Small signal PSR model of NMOS mirror load Error Amplifier 3

8 This model is obtained by grounding the input terminals and applying a small signal voltage supply at. and represent the channel resistance for PMOS and MNOS respectively. 2 represents the parasitic sitting at the gate of the PMOS mirror. Assuming that of the PMOS is large, can be assumed to be short due to 1/. We have, 1 Since 1/ is small, can be approximated to be, Applying superposition in the output node, we have, Thus with the assumption that 1/ is small, we observe that the entire ripples in the power supply is transferred to the output node of a single stage amplifier. Similar results were obtained when two stage amplifiers were considered. Thus, we see at low frequency, the PSR of the amplifier is almost 0dB. If we had the load and the parasitic capacitors, the output will be where 4

9 Figure 4: PSR of Error Amplifier (With PMOS Mirror Load) Thus, both the signal path and the supply noise path encounter the same pole and starts rolling off. Since, the DC gain of them differs by & they have same dominant pole, the specification of PSRR of 65 1 MHz could be easily met. 5

10 TOPOLOGY II Now consider the other variant of the conventional error amplifier, with PMOS input differential stage and NMOS mirror. The small signal PSR model is shown below. Figure 5: Error Amplifier with PMOS Mirror Load Figure 6: Small signal PSR model of PMOS mirror load Error Amplifier 6

11 With the same argument discussed above, we can find that, Now applying superposition in the output node, we get, 0 From this result we observe that no ac ripples appears at the output in this architecture, thereby completely isolating the output node from ac ripples. Similar results were obtained when two stage amplifiers were considered. The following table would summarise the DC PSR and PSR BW for LDO with different possible architectures. PASS TRANSISTOR ERROR AMPLIFIER LOAD DC PSR PSR BW PMOS NMOS MIRROR LOW HIGH PMOS MIRROR HIGH LOW NMOS NMOS MIRROR HIGH LOW PMOS MIRROR LOW HIGH Table II: Comparison of Error Amplifier Architectures Figure7: Typical plot of PSR of LDO From the analysis of the conventional architecture for LDO, we can derive the PSR of the circuit as follows, 7

12 This when plotted in MATLAB gave the following response. Figure 8: PSR of LDO with PMOS Pass Transistor and Error Amplifier with PMOS Mirror load For low drop out, we use PMOS transistors as Pass Device. In this case gain from source to drain and gain from gate to drain has same polarities. So we must ensure that polarities of the supply ripple at gate and source of PMOS pass transistors are out of phase. But doing so degrades the PSR performance of the error amplifier. In reality error amplifier cannot be used as such. It must be plugged into LDO. So we are much more concerned about the PSR of the LDO. But it was found that when we try to achieve high DC PSR, high PSR BW couldn t be achieved and vice versa. So the ultimate goal is to achieve high DC PSR for LDO with high PSR BW. So once the architecture for error amplifier has been chosen, the problem bottles down to either improving the DC PSR of LDO or PSR BW. Some of the possible architectures that were designed to achieve this are discussed below. 8

13 PREVIOUS WORKS UGCC for High PSR Bandwidth In this method, a novel block called unity gain cell compensation has been introduced in the loop. It introduces an internal zero which effectively cancels the dominant pole.thus, the cancellation would improve the bandwidth of the PSR of the LDO. The UGCC block is realized with help of an op amp, as shown in the figure. Apart from the dominant zero, it introduces two poles which would affect the stability of the loop. Hence, to improve the stability an external capacitor in the order of micro Farad is added at the output of the LDO. This would significantly increase the chip area which is one of the drawback of this approach. Further, in this method the internal zero Figure 9: Structure of UGCC generated has to the cancel the dominant pole. Here is a varying capacitance due to of the pass transistor. Hence, the generated zero should also be varying, which makes the design complicated. The possible solution to this problem is to move the dominant pole from. Here = is a static pole. 9

14 Cascoded Pass Transistor using Charge Pump Figure 10: Structure of LDO with UGCC In another approach, the PMOS pass transistor is cascoded with a NMOS transistor, which would effectively increase the output impedance thus improving the PSR of the LDO. This modified structure as against the conventional NMOS pass transistor cascoded with another NMOS transistor would reduce the voltage dropout of the LDO. Figure 11: LDO with Cascoded Pass Transistor & charge pump 10

15 Here, the gate voltage of the NMOS cascode transistor should be at higher voltage to bias it. Hence, a charge pump is used to boost the voltage from the. The addition of charge pump provides an extra complexity to the circuit. This does not require any additional off chip capacitance for the stability of the loop. Though, in this approach there silicon area has been considerably reduced and the challenges due to the varying dominant pole have been cleverly eliminated, the complexity lies in the design of the charge pump. PREVIOUS RESULTS PARAMETER [2] [12] Technology >1.8V 1.2V 1.2V 1V DROPOUT VOLTAGE >600mV 200mV DC 70dB 40dB PSR BW 20KHz 1GHz ON CHIP CAPCITANCE 60pF 1pF OFF CHIP CAPACITANCE* 10 LOAD CAPACITANCE 10p 5mA 100mA 0mA 0mA Settling Time * Capacitance that is explicitly added in the circuit Parasitic Capaticance modeled at the output Table III: Comparison of Previous results 11

16 PROPOSED SOLUTION The conventional architecture for LDO is as shown below. Figure 12: Conventional LDO Architecture is DC gain of Error Amplifier + Where To improve DC PSR or PSR BW, we can use some blocks which when inserted in the above shown block diagram would enhance the DC PSR or PSR BW. To do so, we have 3 different locations where this can be inserted. They are At the LDO output In the feed back path At the Error Amplifier output Figure 13 : Compensation block at LDO output 12

17 Figure 14: Compensation Block in feedback path Figure15: compensation block at Error Amplifier output Inserting this block in the LDO output will not be a wise option because when is at its maximum, the channel resistance of Pass transistor will be very low, so it will shunt what ever we are going to plug in there. In the next case, in the feed back path, the block will be unaware of the variation of the capacitance at the gate of the pass transistor. And this will also make the feed back path complex which may disturb the closed loop parameters. In addition the stability of the LDO may be affected, so we may have to end up with using a big off chip capacitance. Finally, at the error amplifier output, we find some convincing arguments that let us to insert the block at this point. This node is also sensitive to the variation of the gate capacitance of the 13

18 pass transistor. In addition to this, the PSR conflicts of Error amplifier and LDO will be solved if this location is chosen as an appropriate spot to insert the compensation block. Since high PSR BW of LDO will also be a requirement, using NMOS mirror in the error amplifier would be a wise option, which by default provides better BW compared to its PMOS mirror counterpart. But the PMOS pass transistor would require noise at its gate terminal, to cancel out the ripples at the LDO output. To get this done we add a subtractor circuit at the output of Error amplifier which would reflect noise directly at the gate of the Pass transistor. This can be implemented as follows. Figure 16: Subtractor circuit Since the resistance across M8 is only 1/, most of the ripples appear at the drain of M7. This is like purposely bring ripples into gate of the pass transistor so that it cancels out these ripples and gives clean for LDO. Since there is an inversion now from error amplifier output to the pass transistor gate, while closing the loop we must ensure that the feed back is negative. So the feed back signal is properly selected. When plugged into the conventional architecture, this is how it looks. 14

19 Figure 17: Overall circuit I With the compensation block inserted at the output of the amplifier, we have another issue of finding appropriate spot for which is used to compensate the LDO. It cannot be connected between the drain and gate of Pass transistor (usual method) because of very low resistance offered by M8. If it is connected to the gate of M7, then the pole as gate of M6 and the pole at gate of M7 will be near to each other, thereby leading to instability. To solve this issue, we make one of the capacitance at either of the gates to be bigger. To do this, we may have to use bigger as its miller capacitance will be reflected only as gain of two stages (from M7 and Pass transistor). But if connected to the gate of M6, the miller capacitance will be reflected as gain of three stages which now includes the M6 stage. Hence it is convincing to connect it to the gate of M6, where the dominant pole is now located. DESIGN PROCEDURE Settling Time The total settling time of the op amp depends on two factors. The small signal settling time and the slewing time of the amplifier. The small signal settling time of the amplifier is given by N ζ β GBW N C L g Where 15

20 The slewing time constant is given by, Number of time constants required for settling time. Where is voltage swing. This is taken into consideration for the design of Error Amplifier. GBW > 2MHz We need, Using 2, we get, Using ACM equations we have, By setting 5, we get FIRST STAGE To compute, we have = ,,

21 , SECOND STAGE To achieve 60 phase margin, we need Thus we have, Therefore, By letting in the output arm to be 15 A, we have, And we then have, 10 RC Compensation is used to attain stability for this two stage amplifier, after proper tweaking R is found to be 30 Ω. For the design of the subtractor block, we must ensure that most the ripples in appears at gate of the PMOS pass transistor. To ensure this we must satisfy the following condition. Thus the sizes of M7 and M8 are designed and tweaked proportionally such that it satisfies the above condition. 17

22 PASS TRANSISTOR Assuming the drop out voltage to be 200mV, the size of the pass transistor is designed using the following square law expression. 2 We have = 50m To ensure quiescent current is 100, and are designed such that, since we use as 1.2V (which is assumed to be obtained from band gap voltage) we ensure the ratio of and such that it provides feedback of 1.2V to the error amplifier. Thus we get, 21 Ω and 12 Ω For this Design we have assumed 50 and 0 and 100 and the compensation capacitance used in the design is 11pF. 18

23 After tweaking the below. we get the following sizes for the transistors which are summarised TRANSISTOR SIZE M1 30 M M M M M M M MPT MB1 45 MB Table IV: Summary of transistor sizes We have 50 Ω, 0.1 and 11 19

24 ALTERNATIVE APPROACH In the first case, we have assumed an NMOS mirror in error amplifier which by default has high PSR BW for LDO but low DC PSR. Instead we can also try a PMOS mirror in error amplifier that would result in High DC PSR but with a low PSR BW. To enhance the PSR BW, we use the following block as compensation block and it is inserted at the output of the error amplifier. Figure 18: Compensation block to improve PSR BW In conventional LDO, as the dominant pole in the system reflects as zero in PSR we should try to push this zero to enhance the PSR BW. For ripples in the circuit can be visualized as follows. It sees a capacitance in series with 1/. In this case we are giving in voltage and taking out current. This would represent an admittance block which has a capacitor and resistor in series. This configuration will introduce a pole at very early frequencies that would push the zero in the PSR (due to the dominant pole). By employing this block in the circuit, we found a remarkable increase in PSR BW from 1.5KHz to 11.5KHz. But the draw back in this approach is that when varies the dominant pole sitting in the gate of the pass transistor is going to vary that will vary the zero in the PSR. So the compensation done using this concept must be able to track that zero and cancel it accordingly. To do so, we can develop a circuit that senses this variation and varies the capacitance accordingly to cancel the varying zero. This makes the circuit complex. But when this is achieved, this concept can be used in the approach 1 (NMOS Mirror) which would result in High DC PSR as well as High PSR BW. With this compensation mechanism for PSR BW the circuit would like as shown below. 20

25 Figure 19: overall Circuit II Simulation plots for Error Amplifier (approach 1, NMOS Mirror) as well as the LDO are shown below. 21

26 SIMULATION RESULTS FOR ERROR AMPLIFIER AC RESPONSE Figure 20: AC Response of Error Amplifier with 20 DC Gain= 60dB, GBW = 10.9MHz and Phase Margin =43 AC RESPONSE Figure 21: AC Response of Error Amplifier with 80 DC Gain= 60dB, GBW = 4.7MHz and Phase Margin =48 22

27 PSRR Figure22: PSRR of Error Amplifier with 20 PSRR = 1MHz. PSRR Figure23: PSRR of Error Amplifier with 80 PSRR = 1 MHz 23

28 SETTLING TIME Settling time = 37.37ns SETTLING TIME Figure 24: Settling time for 20 Settling Time = 90ns Figure 25: Settling time for 80 24

29 SIMULATION RESULTS OF LDO AC RESPONSE Figure 26: AC response for loop with 0 DC Gain =77.98dB, GBW = 475KHz, Phase Margin = 83 AC RESPONSE Figure 27: AC response for loop with 50 DC Gain =56dB, GBW = 451KHz, Phase Margin = 89 25

30 TRANSIENT RESPONSE Settling Time =1.5µs Figure 28: Settling time for LDO with 0 to 50mA TRANSIENT RESPONSE Settling Time =19.3µs Figure 29: Settling time for LDO with 50mA to 0mA 26

31 LDO PSR Figure 30 : PSR of LDO with 0 PSR = DC LDO PSR PSR = DC Figure 31 : PSR of LDO with 50 27

32 LOAD REGULATION Figure 32: Load Regulation for LDO PERFORMANCE SUMMARY FOR ERROR AMPLIFIER PARAMETER GIVEN SPECIFICATION ACHIEVED SPECIFICATION DC Gain >60dB 60dB GBW >2MHz MHz Phase Margin >60 43 PSRR 1MHz 71dB Settling Time <100ns 37.37ns DC Gain >60dB 60dB GBW >2MHz 4.74MHz Phase Margin >60 48 PSRR 1MHz 71dB Settling Time <100ns 90ns Current Consumption < Table V: Achieved Spec for Error Amplifier 28

33 PERFORMANCE SUMMARY FOR LDO PARAMETER ACHIEVED VALUES DC GAIN 77.98dB LOOP BAND WIDTH 475KHz PHASE MARGIN 83.7 DC PSR 65.21dB PSR BW 11.2KHz 140mV DC GAIN 56dB LOOP BAND WIDTH 451KHz PHASE MARGIN 89.7 DC PSR 60.66dB PSR BW 13.3KHz 160mV Settling Time ( 0 to 50mA) 1.5 Settling Time (50 to 0mA) Table VI: Achieved Spec for LDO COMPARISON OF RESULTS WITH OTHER WORK PARAMETER [2] [12] This Work Technology >1.8V 1.2V 3.5V 1.2V 1V 3.3V DROPOUT VOLTAGE >600mV 200mV 200mV DC 70dB 40dB 62dB PSR BW 20KHz 1GHz 13KHz ON CHIP CAPCITANCE 60pF 1pF 11pF OFF CHIP CAPACITANCE* 10 LOAD CAPACITANCE 10p 100pF 5mA 100mA 50mA 0mA 0mA 0mA * Capacitance that is explicitly added in the circuit Parasitic Capaticance modeled at the output Table VII: comparison with results of other work 29

34 Suggested Improvements & Future Works Error amplifier with PMOS current mirror load has good DC LDO output and NMOS current mirror load has a high PSR LDO output. These two error amplifiers can be connected in parallel to achieve both the good DC PSR as well as high PSR bandwidth. But, it comes at the expense of power and the silicon area. Instead, we can add a PSR bandwidth improving circuit to a PMOS mirror load error amplifier or DC PSR improving circuit to the NMOS mirror load error amplifier, which achieves the same performance at a reduced area and the power. The PSR bandwidth of the NMOS mirror load error amplifier along with DC PSR improving circuit can further be improved by using PSR bandwidth improving circuit discussed above. But, the capacitor of the PSR bandwidth improving circuit should be dynamically varied for the varying load. The voltage at the gate of the error amplifier or the current through the pass transistor can be used to vary the capacitor dynamically. The PSR of the LDO at the unity gain frequency is high. This can be further improved by inserting a high pass filter from the. The introduction of this block would improve the PSR at the required high frequency without disturbing the PSR characteristics at the low frequency. The settling time of the LDO is in the range of few. This is due to the low GBW of the loop. This can be improved by increasing the GBW of the LDO. But, this affects the stability or can be achieved with more power. The alternative approach is to provide an internal feedback from the output of the LDO to the gate of the pass transistor. This path would help to bring the loop to stable state in short duration. But, this needs a slight modification in the architecture used above. The improvement of the LDO PSR with the pole cancellation technique should be achieved by introducing an internal zero that does not affect the signal path. This would be the ideal structure to improve the PSR of the LDO. 30

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37 NETLIST LVS.exe version /11/ :36 (cds125839) $ Command line: /baby/cadence/ic5141/tools.sun4v/dfii/bin/32bit/lvs.exe dir /home11/kshiram/cadence/lvs l s t /home11/kshiram/cadence/lvs/layout /home11/kshiram/cadence/lvs/schematic Like matching is enabled. Net swapping is enabled. Using terminal names as correspondence points. Compiling Diva LVS rules... Net list summary for /home11/kshiram/cadence/lvs/layout/netlist count 13 nets 8 terminals 1 cap 30 pmos 10 nmos Net list summary for /home11/kshiram/cadence/lvs/schematic/netlist count 13 nets 8 terminals 1 cap 11 pmos 8 nmos 33

38 Terminal correspondence points N2 N1 gnd! N10 N13 ibias1 N8 N11 ibias2 N0 N0 vdd! N9 N12 vin+ N3 N7 vin N12 N14 vout N6 N8 vres Devices in the rules but not in the netlist: nfet pfet nmos4 pmos4 The net lists match. layout schematic instances un matched 0 0 rewired 0 0 size errors 0 0 pruned 0 0 active

39 total nets un matched 0 0 merged 0 0 pruned 0 0 active total terminals un matched 0 0 matched but different type 0 0 total 8 8 Probe files from /home11/kshiram/cadence/lvs/schematic devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out: 35

40 Probe files from /home11/kshiram/cadence/lvs/layout devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out: REFERENCES 1. V. Gupta, G. A. Rincon Mora, and P. Raha, "Analysis and Design of Monolithic, High PSR, Linear Regulators for SoC Applications," Proc. IEEE International System on Chip (SOC) Conference, pp , Santa Clara, California, V. Gupta and G.A. Rincon Mora, "A 5mA 0.6um CMOS Miller Compensated LDO Regulator with 27dB Worst Case Power Supply Rejection Using 60pF of On Chip Capacitance," IEEE International Solid State Circuits Conference, San Francisco, CA, Feb Robert J. Milliken, José Silva Martinez and Edgar Sánchez Sinencio, Full On Chip CMOS Low Dropout Voltage Regulator, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 54, NO. 9, SEPTEMBER Michael S.Steyaert & Willy M.C. Sansen, Power Supply Rejection Ratio in Operational Transconductance Amplifiers, IEEE transactions on Circuits and Systems, VOL 37, NO 9, Semptember S.K.Hoon, S.Chen, F.Malberti, J.Chen, B.Aravind, A low Noise, High Power Supplyrejection Low Dropout Regulator for wireless System on Chip Applications IEEE 2005 custom integrated circuits conference. 6. Chaitanya K. Chava and José Silva Martinez, A Robust Frequency Compensation for LDO Regulators, Circuits and Systems, ISCAS IEEE International Symposium. 36

41 7. Mikko Loikkanen and Juha Kostamovaara, PSRR Improvement Technique for Amplifiers with Miller capacitor, IEEE International Symposium on Circuits and Systems, Roger A. Whatley, Circuit for improving Power supply rejection in an operational amplifier with frequency compensation, Motorola, United States Patent , C.K. Chava and J, Silva Martinez, A frequency Compensation Scheme for LDO Voltage Regulator, IEEE Tran on Circuits Syst I, Vol 51. pp , June Improved Power Supply Rejection For IC Linear Regulators, Maxim, Application Note, 883, Xiaohua Fan, Chinmaya Mishra and Edgar Sánchez Sinencio, Single Miller Capacitor Frequency Compensation Technique for Low Power Multistage Amplifiers, IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. 40, NO. 3, MARCH Liang Guo Shen, Zu Shu Yan, Xing Zhang,Yuan Fu Zhao,Tie Jun Lu, Design of Low Voltage Low Dropout Regulator with Wide Band High PSR Characteristic, Solid State and Integrated Circuit Technology, ICSICT 06, 8th International Conference,