ECE 658 Project - Delay Locked Loop Design. Y. Sinan Hanay

Transcription

1 ECE 658 Project - Delay Locked Loop Design Y. Sinan Hanay December 20, 2007

2 Chapter 1 Introduction Generation and distribution of clock signals inside the VLSI systems is one of the most important problems in the design of VLSI systems. Because of the process variations and interconnect parasitics, clock signals delays vary for dierent paths. The clock signals should have zero clock skew, that is to say all the clock signals should arrive at the inputs of registers at the same time. Otherwise latches and ip-ops get clock signal at dierent time instances. In order to circuit to operate correctly these dierences should be eliminated, ideally to zero. However it is not possible practically and 10% of the clock cycle is expended in order to compensate for clock skew[1]. To handle this problem, several solutions are proposed. One of which is usage of H-tree clock networks, in which conguration the distance to all circuit blocks is same thus the clock delay would be same. But this technique is hard to implement since the dierent fanout requirements for dierent blocks and routing constraints. Also some CAD techniques and heuristics are used in the routing of the clock trees [6]. The reduction of clock skew is one of the important problems in the VLSI design. Passive techniques such as clock network optimization techniques cannot completely reduce the clock skew [2]. Phase-locked loops and delay-locked loops (DLL) are extensively used in VLSI circuits in order to decrease clock screw in the clock networks. DLL is a rst order loop that compares it`s input with a reference signal, than delay it `s output so that it can synchronize with the reference signal in a feedback fashion. DLL consists of 4 units: 1. Phase Detector 2. Charge Pump 3. Filter 4. Voltage Controlled Delay Line (VCDL) 1

3 It`s working principle is as follows: First, phase detect block compares the reference clock signal with the output signal, depending on the dierence, if reference signal is leading the output Up (U) signal, else if the reference signal lagging the output signal Down (D) signal is asserted, and thus controls the delay line appropriately. VCDL adjusts the phase of the output signal proportional to the dierence between reference signal until the output signal is high %50 of the time. In the gure below this principle is illustrated 2

4 DLL Design DLLs are notoriously dicult to build correctly. They require expertise in both feedback control systems and analog design. (N. Weste, D. Harris, A. Banerjee, 2005: 490 [14]) In this project some part of the design required Analog design and control systems background. DLLs can be classied in two groups: Analog and Digital DLLs. Digital DLLs have the advantage of higher exibility on supply voltage and low design complexity, while Analog DLLs oer better jitter [9], smaller area, low noise sensitivity and power consumption[8]. The DLL consists of four main components, and they will be discussed in the following sections. 1.1 Phase Detector In order to deskew the clock, rst of all the skew must be known. This skew can be detected by the phase detectors. Its function is to detect the phase dierence between reference clock signal with the input clock signal. It takes these clock signals as input and produces an output that is proportional to the phase dierence. Phase detectors can be analog or digital. The rst phase detectors used in locked-loops was the linear multiplier phase detector, but as the PLLs became to implemented by digital components, digital phase detectors become popular [7]. Simplest digital detector is an XOR gate, of which output is zero if the two inputs have same phase, and one as long as they are not equal. Phase detectors can be implemented digitally by J-K ip-ops. In this work, linear phase detector proposed in [4]is implemented is shown in Figure 1.1. Schematic and layout of the phase detector are shown in Figure 1.2 and 1.3. Figure 1.1: Phase Detector [4] 3

5 Figure 1.2: Phase Detector 1.2 Charge Pump Figure 1.3: Layout of the Phase Detector Charge pump design was one of the most complicated part of the DLL.The zero-oset charge pump that was mentioned in [5]was used. Figures 1.4 and 1.5 shows the schematic and layout of the charge pump. 1.3 Filter In the history of the PLLs the rst phase detector was the linear multiplier phase detector [7]. This multiply lters simply multiply the two inputs, and the desired result is reached by 4

6 Figure 1.4: Schematic of the Charge Pump eleminating the higher frequency terms( odd-harmonics) in the product. This elemination, or ltering, is done by a low pass lter. In DLLs there is no need to include a low pass lter, instead a capacitor is used in order to integrate the phase error mainly, and thus increasing control voltage appropriately. So lter block is simply a capacitor, and a 100fF capacitor was used. Increasing capacitor increases the lock time while decreases the bandwidth and the ripples on the control voltage, and decreasing it decreases lock time and increases the ripples. 1.4 Voltage Controlled Delay Line The function of Voltage Controlled Delay Line (VCDL) is to delay the reference signal so that there is no skew between the output clock and reference signal. Its transfer function is simply, t d = κ DL V filter where V filter is the ltered control input to the VCDL fromcharge pump, t d is the delay (the output) andκis the gain of VCDL. The minimum and maximum delay should be Tc 2 and 1.5 T c For the voltage controlled line, there are several dierent techniques can be employed by analog or digital circuitry. The most common techniques use cascaded inverters. Inverters are used specically for the highest delay resolution. Two main usage of cascaded inverters are called: 1) Current-Starved Inverter Delay Line (in Figure 1.6) and 2) Shunt Capacitor Delay Stage (or Capacitor-Loaded Inverter Delay Line in Figure 1.7 [10]. The delay range of Current-starved inverter circuit is higher than Shunt-capacitor circuit, however Shunt-capacitor transfer function is more linear and has lower gain than the that of Current-starved one [11, 10]. Lower gain is important because higher gain also amplies the noise on the control voltage and may violate the stability [10], and linearity is important since 5

7 Figure 1.5: Layout of the Charge Pump the VCDL is modeled as linear with gain κ dl. In this project I used a two-stage shunt-capacitor delay circuit for the reasons mentioned above. The reason for using two stage is because its noise immunity is higher. Increasing delay stages increases κ d, and which in turn will increase the jitter [13]. I also implemented 8 stage VCDL but did not get satisfactory results. Figure 1.8 shows the implemented VCDL`s transfer characteristics. Maximum achievable delay is around 1.4 ns. Figure 1.6: Current-Starved Inverter Delay Line [10] 6

8 Figure 1.7: Shunt Capacitor Delay Stage [12] 1.5 Simulations Figure 1.8: Implemented VCDL`s Transfer Characteristics Figure 1.11 shows the simulation results for 250 MHz. As it can be seen from the gure, the locking is achieved aroung 14th cycle with a static phase error of 194 ps when the clock is leading the reference signal. By decreasing charge pump`s output resistance it is possible to delay in a shorter time and suppressing the phase error. The results of decreasing charge pump`s output resistance is show in Figure It reveals that locking is achieved at 6th clock cycle, but drawback here is the pulse-width of the clock is decreased too. Figures also show that in the lock state, both UP and DOWN signals are asserted for same duration, and the charge pump current rst increases then decreases by the same amount, eectively putting no net charge to lter. Figure 1.13 shows the static error of 192 ps for DLL running at 1 GHz, when the clock is lagging the reference signal. 7

9 Figure 1.9: Layout of the VCDL Figure 1.10: Layout of the DLL 8

10 Figure 1.11: DLL at 250 MHz 9

11 Figure 1.12: DLL at 250 MHz 10

12 Figure 1.13: DLL at 1 GHz 11

13 Results and Conclusions In this section implemented DLL`s performance is compared with some previous works. This Work JSSC99 [9] Thesis [8] Process 0.25 µm CMOS 0.40 µm CMOS 0.18 µm CMOS Max Operating Frequency 800 MHz 667 MHz 700 MHz Min Operating Frequency 200 MHz 250 MHz 160 MHz Lock Time 14 cycles 2.9µs 11 cycles Static Phase Error 192 ps 80 ps The DLL`s noise immunity can be improved by employing Self Biased techniques mentioned in which the process dependent variables in the system dynamics are eliminated [5]. In another work, noise immunity is increased by using regulated Supply CMOS Buers [4]. However since these techniques require dierential elements it increases the circuit complexity 12

14 Appendix LVS Reports 1) LVS Report of the Phase LVS version /02/ :50 (cds11620) $ Like matching is enabled. Net swapping is enabled. Using terminal names as correspondence points. Compiling Diva LVS rules... Net-list summary for /grads/h/hanay/dokuman/proje/lvs/layout/netlist count 18 nets 6 terminals 14 pmos 16 nmos Net-list summary for /grads/h/hanay/dokuman/proje/lvs/schematic/netlist count 18 nets 6 terminals 14 pmos 16 nmos Terminal correspondence points 1 DN 2 UP 3 ckin 4 ckref 5 gnd! 6 vdd! The net-lists match. instances layout schematic un-matched 0 0 rewired 0 0 size errors 0 0 pruned 0 0 active total nets un-matched 0 0 merged 0 0 pruned 0 0 active total terminals un-matched 0 0 matched but dierent type 0 0 total 6 6 Probe les from /grads/h/hanay/dokuman/proje/lvs/schematic devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out: Probe les from /grads/h/hanay/dokuman/proje/lvs/layout devbad.out: 13

15 netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out: 2)LVS Report of the Charge LVS version /02/ :50 (cds11620) $ Like matching is enabled. Net swapping is enabled. Using terminal names as correspondence points. Compiling Diva LVS rules... Net-list summary for /grads/h/hanay/lvs/layout/netlist count 13 nets 6 terminals 10 pmos 8 nmos Net-list summary for /grads/h/hanay/lvs/schematic/netlist count 13 nets 6 terminals 10 pmos 8 nmos Terminal correspondence points 1 DN 2 OUT 3 UP 4 VBN 5 gnd! 6 vdd! The net-lists match. instances layout schematic un-matched 0 0 rewired 0 0 size errors 0 0 pruned 0 0 active total nets un-matched 0 0 merged 0 0 pruned 0 0 active total terminals un-matched 0 0 matched but dierent type 0 0 total 6 6 Probe les from /grads/h/hanay/lvs/schematic devbad.out: netbad.out: mergenet.out: termbad.out: 14

16 prunenet.out: prunedev.out: audit.out: Probe les from /grads/h/hanay/lvs/layout devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out: 2)LVS Report of the Voltage Controlled Delay LVS version /02/ :50 (cds11620) $ Like matching is enabled. Net swapping is enabled. Using terminal names as correspondence points. Compiling Diva LVS rules... Net-list summary for /grads/h/hanay/lvs/layout/netlist count 8 nets 5 terminals 2 pmos 14 nmos Net-list summary for /grads/h/hanay/lvs/schematic/netlist count 8 nets 5 terminals 2 pmos 6 nmos Terminal correspondence points 1 gnd! 2 out 3 vctrl 4 vdd! 5 vin The net-lists match. instances layout schematic un-matched 0 0 rewired 0 0 size errors 0 0 pruned 0 0 active 16 8 total 16 8 nets un-matched 0 0 merged 0 0 pruned 0 0 active 8 8 total 8 8 terminals un-matched 0 0 matched but dierent type 0 0 total 5 5 Probe les from /grads/h/hanay/lvs/schematic devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out: 15

17 Probe les from /grads/h/hanay/lvs/layout devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out: 16

18 Bibliography [1] S.M. Kang, Y. Leblebici, CMOS Digital Integrated Circuits, McGraw Hill, [2] Z. Zilic, Phase- and Delay-Locked Loop Clock Control in Digital Systems, [3] J.M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, 2nd ed., Prentice Hall, [4] S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. Horowitz. Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buers. In Proc. IEEE Symposium on VLSI Circuits, pages , June [5] Maneatis, et al., "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, November [6] N. Menezes, S. Pullela, A. Balivada and L.T. Pillage, Skew Reduction in Clock Trees Using Wire Width Optimization, Proceedings Custom Integrated Circuits Conference, May [7] R. E. Best, Phase-Locked Loops, 6th Edition, McGraw Hill, [8] C. Jia, A Delay-Locked Loop for Multiple Clock Phases/Delays Generation, Doctoral Thesis, Georgia Institute of Technology, [9] B.W. Garlepp, K. S. Donnelly, J. Kim, P. S. Chau, J. L. Zerbe, C. Huang, C. V. Tran, C. L. Portmann, D. Stark, Y.-F. Chan, T. H. Leen, and M. A. Horowitz, A Portable Digital DLL for High-Speed CMOS Interface Circuits, IEEE J. Solid-State Circuits, vol. 34, pp , May [10] M. G. Johnson and M. E. Hudson, A variable delay line PLL for CPUcoprocessor synchronization, IEEE J. Solid-State Circuits, vol. 23, pp , Oct [11] W. J. Dally and J. W. Poulton, Digital Systems Engineering, Cambridge University Press, [12] S. Liu, J. Lee and H. Tsao, "Low-power clock-deskew buer for high-speed digital circuits", IEEE Journal of Solid-State Circuits, SC-34, pp , April [13] J. Baker, H. W. Li and D. E. Boyce, "CMOS - Circuit Design, Layout and Simulation, IEEE Press,

19 [14] N. H. E. Weste, D. Harris and A. Banerjee, CMOS VLSI Design A Circuits and Systems Perspective, Pearson Addison-Wesley, [15] B. Razavi, Design of CMOS Analog Integrated Circuits, McGraw Hill, [16] P. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley Sons, Inc,