DESIGN OF LOW POWER VOLTAGE REGULATOR FOR RFID APPLICATIONS

Transcription

1 UNIVERSITY OF ZAGREB FACULTY OF ELECTRICAL ENGINEERING AND COMPUTING DESIGN OF LOW POWER VOLTAGE REGULATOR FOR RFID APPLICATIONS Josip Mikulic Niko Bako Adrijan Baric MIDEM 2015, Bled Overview Introduction Post-Layout Simulation Results Experimental Results Performance Comparison Conclusion MIDEM 2015, Bled 2 of 19 1

2 Introduction Industry oriented to full on-chip solutions Profit and production complexity Design of the voltage regulators affected Cost production limits chip area Low-power Scalability to low voltages Conventional solutions no longer usable Fully compensated solutions take advantage Topic of this work is the design of voltage regulator which will fulfill the mentioned requirements and will be useable in modern applications, such as RFID MIDEM 2015, Bled 3 of 19 Topology Overview Conventional linear regulator topology Pass device controled by the error amp Stability ensured with large output capacitor Area consuming (C L ) Fully compensated linear regulator topology Miller compensation network included C L no longer important for stability Area efficient = Convinient for fully integrated solutions MIDEM 2015, Bled 4 of 19 2

3 Proposed Topology for the LDO Voltage Regulator RNMC (Reverse Nested Miller Compensation) error amplifier 1st stage differential amplifier 2nd stage common source 3rd stage pass device = VF direct implementation of positive gain RNMC topology = Suitable for driving large capacitive loads with low power = VF in a feedback branch Feedback network Decoupling capacitor MIDEM 2015, Bled 5 of 19 Open-Loop Transfer Function Analysis DC gain Dominant pole GBW ULGF Negative Zero AV 0 = -g m1r1 g m2r2 1 w p 1 = ( CC 1 gm 2 r 2 ) r 1 w GBW g = A V 0 w p1 = C w ULG = FB w GBW rfb2 FB = rfb1 + rfb2 w gmvf z = CC1 m1 C1 Nondominant poles (assuming real) w w Nondominant complex poles w p2,3 gm3 CC1 p2 = CL CC 2 gmvf gm2 p3 = CC1g mvf + CC1g m2 Ø ø 2 gm2 Œ 4gm3CC 1 1+ œ g Œ Ł g m2 mvf ł œ = Œ 1 j -1 g C œ Œ LCC2g m m2 C œ C1 Ł gmvf ł Œ º œ ß MIDEM 2015, Bled 6 of 19 3

4 LDO Voltage Regulator Implementation (I) LDO voltage regulator designed in 0.18 um CMOS technology Biasing network and power enabling circuitry not shown 1st stage differential amplifier 2nd stage common source 3rd stage voltage follower = Low threshold nmos = LDO feature = 500 µa RNMC topology = VF in the feedback branch Voltage reference Feedback network = Diode connected transistors = Factor 1/3 Decoupling capacitor = 100 pf MIDEM 2015, Bled 7 of 19 LDO Voltage Regulator Implementation (II) Nominal output voltage V OUT : V Nominal quiescent current consumption I Q : 3.7 µa Transistor Size (W/L) I Q M 1a, M 1b 1.2µm/1.8µm 0.25 µa M µm/0.54µm 1 µa M a 3 200µm/0.4µm 1.8 µa M VF 0.4µm/1.8µm µa M 2a, M 2b 0.96µm/3.6µm 0.25 µa M d1, M d2, M d3 5.4µm/0.9µm 0.4 µa M gp1 1.2µm/1.2µm 0.5 µa M gp2 2.4µm/1.2µm 1 µa M gn1 0.96µm/3.6µm µa M gn2 0.96µm/5.4µm 1.4 µa Capacitor C C1 C C2 C L Value 1.8 pf 0.18 pf 100 pf MIDEM 2015, Bled 8 of 19 4

5 LDO Voltage Regulator Implementation (III) Layout of the designed voltage regulator Area : mm 2 = mm 2 Output capacitor C L not shown = mm 2 C C1 C C2 M 3 MIDEM 2015, Bled 9 of 19 Post-Layout Simulation Results Loop Gain AC Response Simulated loop gain with parameter I L I L : 0 to 500 µa (log steps) V DD =1.6V GBW = 100 khz PM > 75 deg Poles and zeros Dominant pole: 0.05 khz Nondominant complex poles = Abs. value: 320 khz to 1.5 MHz Negative zero: 500 khz MIDEM 2015, Bled 10 of 19 5

6 Post-Layout Simulation Results Power Supply Rejection Ratio Simulated PSRR with the load current I L as a parameter I L : 0 to 500 µa (log steps) V DD =1.8V Low frequencies -80 db Intermediate frequencies Worse for larger load currents Influenced by the output resistance of the pass device High frequencies Converges to the ratio of C L and C DS of the pass device MIDEM 2015, Bled 11 of 19 Post-Layout Simulation Results Line Regulation Simulated DC response of the output voltage V OUT to the supply voltage V DD V DD changing from 1.4 V to 1.8 V I L = 500 µa Line regulation DV LiR = DV OUT DD I L, MAX LiR = 1.25 mv/v MIDEM 2015, Bled 12 of 19 6

7 Post-Layout Simulation Results Load Regulation Simulated DC response of the output voltage V OUT to the load current I L I L changing from 0 to 500 µa Room temperature Three voltages Load regulation DV LoR = OUT DIL LoR = 1.08 mv/ma for V DD = 1.6 V at 500 µa MIDEM 2015, Bled 13 of 19 Post-Layout Simulation Results Transient Simulations Simulated transient response of the output voltage V OUT to the step load current I L I L changing from 0 to 500 µa = Rise/fall time of t r/f = 1 µs V DD = 1.6V Settling time: 6 µs MIDEM 2015, Bled 14 of 19 7

8 Experimental Results Chip fabricated in UMC 0.18 um Microphotograph and measurement PCB visible in the figures VDD Results: V OUT = 1.49 V = 35 mv higher than nominal ΔV = 60 mv I Q = 4.2 µa = Including the voltage reference and biasing circuitry LiR = 3.5 mv/v LoR = 2.4 mv/ma at 500 µa PSRR: -49 db at DC and -16 db at 1MHz VOUT GND IBIAS MIDEM 2015, Bled 15 of 19 Experimental Results Transient Measurement Measured transient response of the output voltage V OUT to the step load current I L I L changing from 0 to 500 µa = rise/fall time of t r/f = 100 ns V DD =1.6V Simulation results for the comparison Comparison Very good correspondence between the simulations and measurements MIDEM 2015, Bled 16 of 19 8

9 Performance Comparison [5] [6] [7] This work Comparison with other low-power voltage regulators Good static and dynamic behaviour for the invested power LDO feature Fully compensated Suitable for full on-chip solutions Technology 0.13µm 0.18µm 65nm 0.18µm Chip area (mm 2 ) NA NA Input voltage (V) > to to to 1.8 Nominal output voltage (V) Referent voltage (V) Supply capability (µa) Quiescent current (µa) (4.2) Load regulation (mv/ma) Line regulation (mv/v) (3.5) -51dB -12dB NA NA -45dB -62dB -80dB (-49dB) -20dB (-16dB) References: Settling time (µs) NA 6 Load capacitance (pf) NA 100 Compensated YES NO NO YES [5] L. Lijun, K.D. Gannes, K. Fricke, S. Senjuti, and R. Sobot, Low power CMOS voltage regulator architecture for implantable RF circuits, in RFID Technology (EURASIP RFID), 2012 Fourth International EURASIP Workshop on, pp , Sep [6] J. Guo and K.N. Leung, A CMOS voltage regulator for passive RFID tags ICs, International Journal of Circuit Theory and Application, vol. 40, no. 4, pp , April [7] C.C. Liu. Chia-Chin, C. Chen An ultra-low power voltage regulator for RFID application, in Circuits and Systems (MWSCAS), IEEE 56th International Midwest Symposium on, p.p , 4-7 Aug MIDEM 2015, Bled 17 of 19 Conclusion Topology based on RNMC, suitable for low-power full on-chip voltage is proposed The topology was proposed based on analytic calculations LDO voltage regulator is designed by using the proposed topology Circuit is implemented in 0.18 um technology Layout was drawn Post-layout static and dynamic simulations are performed The designed regulator is fabricated in UMC 0.18 CMOS process Performed silicon measurements show high correspondence with the simulations MIDEM 2015, Bled 18 of 19 9

10 Acknowledgement This work has been partly supported by the European Union from the European Regional Development Fund under the project Wirelessly powered microelectronic circuits for distributed sensor networks, project code RC , contracted through the Ministry of Science, Education and Sports of Croatia. MIDEM 2015, Bled 19 of 19 THE END Thank you for you attention! MIDEM 2015, Bled 20 of 19 10