Steven Mark s Toroidal Power Unit (TPU) TP900 - TPU PULSER. - A useful tool for TPU and other research

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1 Steven Mark s Toroidal Power Unit (TPU) TP00 TPU PULSER A useful tool for TPU and other research Prepared by: Document Date: Revision: Darren Kozey (z_p_e) 00/AUG/0 TP00.

2 TP00 TPU PULSER PREFACE After folks finish reading through the SM material and feel they are ready to begin experimenting, one must have tool they need is a unit that can be used to pulse their coils. It is the aim of this document to provide the design for such a tool. The core TP00 circuit provides separate and independently controlled square wave generators capable of frequeies from 0. Hz up to about MHz. The unit comes integrated with a unique frequey divider by changing the mode switch over to SYNCHRONIZED, the outputs are harmonically related and syhronized in time. As an added bonus, the TP00 is equipped with a sophisticated and novel pulse generation circuit capable of pulse widths variable from ms to as short as ns. To put things in perspective, the propagation delay of a single AC0 inverter gate is about ns, so ns is fairly impressive. With a khz frequey for example, a ns pulse width translates to a duty cycle of only 0.0%. Much time and effort has gone into this design, and it is my hope that it should prove useful in many areas of research involving pulsed coils. As a final note, I wish to extend credit to David Johnson and Associates for the Divide by. circuit, and to Dallas Semiconductor for inspiring the pulse circuit. Good luck and enjoy, Sierely, Darren (z_p_e)

3 TP00 TPU PULSER A BRIEF THEORY OF OPERATION The Oscillator The core of the TP00 is the oscillator formed around a Schmitt trigger and RC timing components. This configuration is fairly well known and some information about them can be located on the web. A good place to start is here: The Harmonic Divider I simply took the Divide by. circuit designed by David Johnson and Associates, and modified it to provide a Divide by as well. The input frequey is thus divided by., then again by, and an output is taken from each resulting in the fundamental, and the second and third harmonics. The F oscillator is the master clock in the SYNCHRONIZED mode of operation. 0% Duty Cycle Following the Data Multiplexer U which is used to select either INDEPENDENT or SYNCHRONIZED frequeies, flipflops configured for divide by are used to establish a guaranteed 0% duty cycle output before the Pulse Generator circuitry. This is required because both the Schmitt oscillators and the Divide by. circuits yield asymmetrical wave forms. The Current Sink and Current Mirror The pulse circuit is composed of several key components, and the precision Ramp Generator is certainly one of them. The operational amplifier U0A and associated transistors form a high quality current source for linearly ramping up the chosen timing capacitor. The cascode transistor Q was implemented to augment the current source output impedae, and limit the maximum ramp voltage. The timing capacitor charging current is determined by.v/r pulse width. Without a switch to reset the ramping voltage, we would not have a futioning pulse circuit. To facilitate this need, I implemented a rather unlikely candidate for the switch a AC0 Octal Buffer/Line Driver with STATE Outputs. Some may be scratching their heads right now wondering what the heck I am doing!

4 TP00 TPU PULSER Well, I tried a few MOSFETs and transistors as switches, but was not completely satisfied with the results. In fact, I could not get any MOSFET to work properly. All that is required really is something that can bring down the timing capacitor s voltage quickly and completely, and through a novel approach, the AC0 worked quite well indeed. Being a buffer/line driver, the AC0 has relatively robust outputs, and as there are eight in a package, paralleling them creates an effective switch to ground for resetting the capacitor. I simply hardwired the inputs HI and paralleled the outputs. Using the STATE capability of the device, I now had a pseudo switch. Delay and Detect The basic coept of the pulse circuit is to send an edgetrigger down two paths one directly, and one delayed by some userchosen amount. The ramp circuit facilitates the delayed path, and now all that has to be done is implement a detector which determines when the delay is finished. This is accomplished via a precision highspeed comparator, U. The threshold is set to. Volts by the precision voltage referee. Oe the threshold is reached, the comparator goes HI, and the NOR output goes LO, ending the pulse set into motion by the direct path leading edge. This circuit has an added benefit; it is somewhat idiotproofed in that the output pulse width can never exceed half of the square wave period. Not having this failsafe would be catastrophic! The NOR output then feeds the MAX0 MOSFET driver. Pulse or Square? At MHz frequeies, propagation delays are critical, and I did not want to introduce more than was necessary in order to maintain the ns spec. As such, in order to implement PULSE or SQUARE mode selection, I did not want to introduce yet another device in the pulse path. The solution was easy and was achieved by pulling down the timing capacitor with a transistor switch in parallel with the AC0 switch. In this way it acts as an override and prevents the capacitor from ever charging. No additional propagation delays are introduced, and when not active, the transistor is transparent to the circuit operation.

5 TP00 BOM Page of TP00 TPU PULSER Revised: Saturday, August 0, 00 TP00. Revision: Designed by z_p_e Copyright Darren Kozey 00 Bill Of Materials August,00 :: Item Quantity Referee Part Description C,C,C 0p Film C,C,C,C,C,C 00p Film C,C0,C,C,C,C n Film C,C,C,C,C,C 0n Film C,C,C,C,C,C 00n Film C,C,C0,C,C0,C u Film C,C,C,C,C,C 0u Film C,C,C,C,C,C,C,C,C 00u Electrolytic, 0V min. C,C,C,C,C,C,C0,C,C,C,C,C,C, C,C0,C,C,C,C,C,C,C,C,C,C0,C, C,C,C,C Mono or Ceramic 0 0 C0,C,C,C,C0.u Tantalum, 0V min. C,C 000u Electrolytic, V min. D,D,D LT00.. Volt Referee D,D,D LT00..V Referee D,D,D,D0 MUR0 Diode, Ultrafast M,M,M IRF0 MOSFET, Power Q,Q,Q,Q,Q,Q,Q,Q,Q QN0 High HFE, PNP Q,Q,Q QN0 High HFE, NPN Q,Q0,Q MPS0 Amplifying, NPN / R,R,R,R,R,R / R,R,R0 k R, R, and R0 are Rheostats/Potentiometers 0 R,R,R 00k Rheostat/Potentiometer R,R0,R,R,R,R 00 Resistor R,R,R Resistor R,R,R.k Resistor

6 TP00 BOM Page of TP00 TPU PULSER Revised: Saturday, August 0, 00 TP00. Revision: Designed by z_p_e Copyright Darren Kozey 00 Bill Of Materials August,00 :: Item Quantity Referee Part Description R Resistor SW,SW,SW RSW Rotary Switch, Position SW,SW SW SPDT Switch, SPDT SW,SW,SW RSW Rotary Switch, position TB? Terminal Block, position U,U AC0 Dual "JK" FlipFlop 0 U AC Hex Schmitt Inverter U,U,U0 AC0 Hex Inverter U AC0 Quad "AND" Gate U AC Dual "D" FlipFlop U AC0 Quad "NOR" Gate U AC Quad Data Multiplexer U0 TLC Quad OpAmp, LinCMOS U,U,U AC0 Octal Buffer/Line Driver with STATE Outputs U,U,U LT Comparator, Fast U,U,U MAX0 MOSFET Driver, Lowside 0 U LM0/TO0 Regulator, V, Medium Power HS,HS,HS Heat Sink Suitable for the IRF0 MOSFETs

7 R k UA R 00k AC F FREQUENCY UA AC0 UB AC0 UC AC0 UD UE 0 AC0 AC0 UA AC0 UA J Q CLK Q K AC0 F C 0p 0 C 00p SW RSW C n C 0n C 00n C u C 0u D PRE CLKQ UA Q AC F RANGE F FREQUENCY UB AC0 J Q CLK Q K C 0p 0 SW RSW C0 n F RANGE C 0u D PRE 0 CLKQ UB Q AC INDEPENDENT SYNCHRONIZED SW U AC I0A ZA IA I0B ZB IB ZC IC 0 I0D ZD ID S E UA J Q CLK Q K AC0 F F FREQUENCY UC AC C 00p F RANGE UB J Q CLK Q K AC0 F 0 UE 0 AC0 UB AC0 UA AC0 R k R 00k UA AC0 UC AC0 UB 0 C 00p AC C 0n C 00n C u UD AC0 R k R 00k C 0p 0 SW RSW C n C 0n C 00n C0 u C 0u POSITION ~ FREQUENCY RANGE 0.Hz ~ 0Hz Hz ~ 00Hz 0Hz ~ khz 00Hz ~ 0kHz khz ~ 00kHz 0kHz ~.MHz khz ~ MHz Gnd_C Designed by z_p_e Copyright Darren Kozey 00 Title TP00 TPU PULSER Frequey Generators and Harmonic Dividers Size Document Number Rev C TP00. Date: Saturday, August 0, 00 Sheet of

8 R k C 00u C Q QN0 Q QN0.V D LT00. C 00u C U0A TLC Q QN0 Q QN0 F PULSE WIDTH R k R 00 R0 00 C U G A A A A Y Y Y Y G A Y A Y A Y A Y AC0 D LT00. R C 00u C U LT out out gnd LE UB AC0 C0.u Tant. C IN U MAX0 OUT OUT M IRF0 D MUR0 SW_F U0A F AC0 SQUARE PULSE SW R.k Q MPS0 Pulse_Enable_F Pulse_Enable_F Gnd_C Gnd_N POSITION ~ PULSE WIDTH RANGE ms ~ 0us 00us ~ us 0us ~.us us ~ 0.us ns ~ ns C 00p C n C 0n SW RSW C 00n C u C 0u 0ns ~ ns F PULSE WIDTH RANGE Designed by z_p_e Copyright Darren Kozey 00 Title TP00 TPU PULSER F Pulse Generator and Driver Size Document Number Rev C TP00. Date: Saturday, August 0, 00 Sheet of

9 R k C 00u C Q QN0 Q QN0.V D LT00. C 00u C0 U0B TLC Q QN0 Q QN0 F PULSE WIDTH R k R 00 R 00 C U G A A A A Y Y Y Y G A Y A Y A Y A Y AC0 D LT00. R C 00u C U LT out out gnd LE UC AC0 0 C.u Tant. C IN U MAX0 OUT OUT M IRF0 D MUR0 SW_F U0B F AC0 Pulse_Enable_F R.k Q0 MPS0 Gnd_C Gnd_N POSITION ~ PULSE WIDTH RANGE ms ~ 0us 00us ~ us 0us ~.us us ~ 0.us ns ~ ns C 00p C n C 0n SW RSW C 00n C0 u C 0u 0ns ~ ns F PULSE WIDTH RANGE Designed by z_p_e Copyright Darren Kozey 00 Title TP00 TPU PULSER F Pulse Generator and Driver Size Document Number Rev C TP00. Date: Saturday, August 0, 00 Sheet of

10 R k C 00u C Q QN0 Q QN0.V D LT00. C 00u C 0 U0C TLC Q QN0 Q QN0 F PULSE WIDTH R0 k R 00 R 00 C U G A A A A Y Y Y Y G A Y A Y A Y A Y AC0 D LT00. R C 00u U LT outout gnd LE UD AC0 C C.u C0 Tant. IN U MAX0 OUT OUT M IRF0 D MUR0 SW_F U0C F AC0 Pulse_Enable_F R.k Q MPS0 Gnd_C Gnd_N POSITION ~ PULSE WIDTH RANGE ms ~ 0us 00us ~ us 0us ~.us us ~ 0.us ns ~ ns C 00p C n C 0n SW RSW C 00n C u C 0u 0ns ~ ns F PULSE WIDTH RANGE Designed by z_p_e Copyright Darren Kozey 00 Title TP00 TPU PULSER F Pulse Generator and Driver Size Document Number Rev C TP00. Date: Saturday, August 0, 00 Sheet of

11 DESIGN NOTES: ) The "AC" series was chosen for its high speed and low propagation delay, which becomes quite significant at MHz. Care has been taken in selecting device types; for best performae, please adhere to them if possible. ) Additional gates in the F, F, F divider section were added for propagation delay matching. As shown, all rising and falling edges are within ns. If further custom matching is necessary, unused gates are available. ) Outputs are guaranteed 0% duty cycle. ) Place the MAX0 and IRF0 as close together as possible. ) Keep the noisy "" ground separate from the CMOS "" ground until the Terminal Block TB where they are tied together. ) In the "SYNCHRONIZED" mode, only the "F" FREQUENCY and RANGE controls are used. ) Q/Q, Q/Q, Q/Q pairs should be matched as close as possible for best performae and matching. % matches for HFE and "Diode Check" readings with a good digital meter are adequate. ) Use good quality film types for all "timing" capacitors. Examples ilude polyproylene, polystyrene, and polyester (last choice). Recommend "polystyrene" for 0pF to 0nF values, and "polypropylene" for 00nF to 0uF values. ) If a "FINE" frequey adjust is desired, insert a 0k rheostat/potentiometer in series with R, R, and R. Note that this will extend the low end of the frequey ranges by about 0%. SW_F SW_F SW_F F F F TB Coil Low Side Coil Low Side Coil Low Side Battery in Battery gnd Gnd_C Gnd_N D0 MUR0 R U LM0/TO0 VIN VOUT V C 000u C.u Tant. C C0.u Tant. C C 000u U U U AC AC0 AC0 C C C 0 U AC0 C U AC C U AC0 C U AC0 C U AC0 C0 U AC C 0 0 U AC0 C 0 0 U AC0 C 0 0 U AC0 C U0 AC0 C U0D TLC Designed by z_p_e Copyright Darren Kozey 00 Title TP00 TPU PULSER V Supply and External Interface Size Document Number Rev C TP00. Date: Saturday, August 0, 00 Sheet of