EDA365. DesignCon Hybrid Statistical and Time- Domain Simulation Methodology for High-speed Links

Transcription

1 DesignCon 2010 Hyrid Statistical and Tie- Doain Siulation Methodology for High-speed Links Jihong Ren, Raus Inc. Dan Oh, Raus Inc. Sa Chang, Raus Inc.

2 Astract Accurate analysis of link perforance including deterinistic and rando effects as well as advanced signal conditioning schees is crucial in odern high-speed I/O design. In recent years, statistical link perforance tools such as Linkla and StatEye, and fast tiedoain siulation tools such as IBIS Algorithic Modeling Interfaces (AMI) are introduced to efficiently co-siulate deterinistic and rando effects as well as advanced signaling schees. However, these statistical and tie-doain approaches have liitations in ters of their capaility of accurately siulating syste nonlinearity, general jitter, jitter tracking as well as coding. In this paper, we present a hyrid approach that coines statistical and tie-doain techniques to efficiently overcoe these liitations. It has several key contriutions: 1) capture syste nonlinearity using ultiple-edge responses (MER), a fast tie-doain ethod; 2) separately siulate deterinistic and rando jitter, one in tie-doain to capture jitter nonlinearity and the other in statistical doain to capture tail statistics; 3) co-siulate signal and power integrity to include siultaneous switching output noise (SSO) which is one of the ajor liiting factors for single-ended signaling systes such as GDDR5; 4) co-siulate clock and data channel to correctly capture jitter tracking in source-synchronous systes. We deonstrate this hyrid approach y studying the jitter tracking capaility of clock forwarding and effectiveness of coding in ters of syste it error rate. Author(s) Biography Jihong Ren received her Ph.D in Coputer Science fro University of British Coluia in Since January 2006, She has een with Raus working on high-speed link analysis, adaptive equalization algoriths, advanced signaling schees and circuit analysis. Kyung Suk (Dan) Oh is a Senior Principal Engineer at Raus Inc. He received the B.S., M.S., and Ph.D. in electrical engineering fro the University of Illinois, at Urana- Chapaign in 1990, 1992, and 1995, respectively. His doctoral research was in the area of coputational electroagnetics applied to transission line odeling and siulation. Since 2000, he is with Raus Inc., Los Altos, CA. During last five years, he had anaged a tea responsile for providing signal integrity analysis for various products including serial, parallel, and eory interfaces. Additional responsiilities of his group included an advance CAD tool developent for high-speed link siulation. Recently, he ecae a technical leader aintaining the sae responsiilities. His current interests include advance signal and power integrity odeling and siulation techniques, optiization of channel designs for various standard or proprietary I/O links, and application of signaling techniques to high speed digital links. He has pulished over 60 papers and holds 14 issued patents and pending patent applications in areas of high-speed link design. He received two Best Paper Awards in DesignCon and 2008 Best Paper Award in IEEE Adv. Packaging journal. He is a eer of the Technical Progra Coittee of IEEE EPEPS. Sa Chang is currently an engineer for the Signal Integrity Division of Raus Inc., located in Los Altos, California. His current work involves odeling and developent of

3 solutions for high-speed digital links. Sa holds a Ph.D in Electrical Engineering (2005) fro University of California, Riverside.

4 I. Introduction As data rate arched into Gps and eyond era, with advanced signaling schees that coonly in use to coat inter-syol interference (ISI), link perforance is no longer only liited y deterinistic effects. Rando noise such as rando jitter has ecoe critical in deterining the final syste perforance. Accurate analysis including oth the deterinistic and rando effects as well as advanced signal conditioning is crucial for next-generation high-speed I/O design. In recent years, novel siulation techniques ased on statistical analysis or fast tie-doain ethods are introduced to co-siulate oth deterinistic and rando effects. LinkLa [1] and StatEye [2] are exaples of the statistical link analysis tools. IBIS algorithic odeling interface (AMI) [3] is an exaple of fast tie-doain siulation engines. Intel also presented a fast tie-doain siulation ethod ased on superposition [4]. Both statistical and tie-doain approaches have their liitations in ters of their capaility of accurately siulating syste nonlinearity, general jitter, jitter tracking as well as coding. In this paper, we first discuss these liitations and present a hyrid approach that ixes statistical and tiedoain techniques to overcoe these liitations. First, currently oth the statistical approach and the fast tie-doain approach are ased on single-it response (SBR) analysis or equivalent single edge response analysis. The underline assuption ehind SBR analysis is that the syste is linear tie invariant (LTI) and can e characterized y the syste response excited y a single pulse lasting for one it tie. Typical differential signaling systes with current ode drivers can e well approxiated y an LTI. For low-power application with low-swing voltage-ode drivers [5], driver nonlinearity starts to kick in. Moreover, single-ended systes, such as GDDR5, typically have different rising and falling edge responses due to either asyetric I/O design or isatches etween pull-up and pull-down drivers. For these systes, SBR ethod is no longer applicale. Moreover, as data rate increases, device tiing jitter consues a large portion of the tiing udget of the interface. [2, 3] odels transitter jitter as receiver sapling distriution and ignores jitter aplification of the passive channel [7]. In [1], transitter jitter is apped into equivalent voltage noise using first-order Taylor expansion. This approach can capture jitter aplification ut ignores the nonlinear nature of jitter and is not accurate when jitter is ig. In [4], DJ and RJ are separately handled. It siulates DJ in tie doain and deals with RJ y extrapolating athtu ased on dual-dirac ethod. Therefore, jitter aplification of RJ through the channel is not odeled. Moreover, dual- Dirac odel is rather inadequate for accurate BER estiation [9]. For systes with a forwarded clock, jitter tracking etween data and receiver sapling clock is generally ignored. Furtherore, SSO noise, which is typically negligile in differential signaling, is one of the ajor ottlenecks in designing high-speed single-ended signaling systes such as GDDR5 [13]. The next generation graphics eory systes are running at 5Gps and eyond. At this data rate, various jitter effects ust e considered in evaluating I/O perforance. Predicting syste perforance degradation due to SSO noise requires accurate odels for power distriution network (PDN) and signal channels. The

5 voltage (V) siulation fraework presented in this paper is the first to include SSO in it error rate estiation. Finally, current statistical link analysis approach assues true rando data patterns to ease the coputation of ISI proaility distriution. Therefore, strictly speaking, they are not applicale when coding, such as DBI (data us inversion), is used. This paper presents a hyrid siulation fraework that ixes statistical and transient siulation ethods to overcoe these liitations (Figure 1). It has several key contriutions: 1) a fast tie-doain ethod that captures syste nonlinearity; 2) separately siulate deterinistic and rando jitter, one in tie-doain to capture jitter nonlinearity and the other in statistical doain to capture rando jitter tail statistics; 3) co-siulate clock and data channel to correctly capture jitter tracking in sourcesynchronous systes; 4) co-siulate signal and power integrity to include siultaneous switching output noise (SSO) which is one of the ajor liiting factors for single-ended signaling systes such as GDDR5. The rest of the paper is organized as follows. Section II riefly overviews the overall siulation flow. Section III discusses the liitations of SBR-ased ethods and introduces ultiple-edge response (MER) ethod. It then descries the extree-value decoposition (EVD) ethod which extrapolates ISI PDFs ased on tie-doain histogras. Section IV uses GDDR syste as an exaple to illustrate how we can efficiently handle SSO noise using MER ased on the SI-PI co-siulation ethodology presented in [13]. Section V focuses on jitter odeling ethodologies. It uses sourcesynchronous systes as an exaple to show how to co-siulate clock and data channels to correctly capture any jitter tracking etween clock and data. Pre-characterization (SPICE) PDN Models (VRM, Decaps, Packages, onchip PDN ) Channel Models (Packages, connectors, PCB traces ) tie (ns) Histogra Generation (Tie Doain) TX, RX (RJ) RX (RN,DN) BER Estiation (Statistical Doain) Data TX (DJ) CLK TX (DJ) RX (DJ) RX (DJ) voltage voltage ISI PDF (DN) Effective Voltage PDF Bathtu Curve Figure 1. Hyrid statistical and tie-doain siulation flow with signal and power integrity odels. Clock channel is optional. tie

6 II. Hyrid Statistical and Tie-doain Siulation Flow Overview LinkLa [1], a statistical link perforance analysis tool, takes into account the link architecture, channel odels, different equalization algoriths as well as various noise sources to evaluate the perforance of the syste using a BER criterion. The hyrid statistical and tie-doain flow (LinkLa/MER) presented in this paper copleents the LinkLa statistical flow with a fast tie-doain engine. The entire LinkLa/MER flow is suarized in Fig. 1. First, SPICE decks for the whole link are set up for pre-characterization in order to extract the edge responses required for MER. The SPICE decks include detailed channel odels with packages, connectors and PCB traces etc. as well as detailed PDN odels with VRM, decaps, packages, on-chip PDN etc. Therefore, the extracted edge responses include the effects of channels and non-ideal PDN. In this set up, SSO noise is treated as another for of crosstalk and characterized y edge responses. Details on SSO noise siulation are presented later in Section IV. With the extracted edge responses, MER engine constructs syste response for illions of its and gathers signal histogra. Deterinistic jitters are included in tie-doain histogra generation to accurately capture jitter nonlinearity, while rando jitter is dealt in statistical doain y converting it into equivalent voltage noise seen y the receiver. This allows efficient siulation as it is very hard to capture the rando jitter statistics in tie doain. Both the tie-doain approach for DJ and the statistical approach for RJ capture the jitter aplification effect of the passive channel. Moreover, for source synchronous systes with a forwarded clock, the clock channel is siulated to generate receiver sapling clock ticks for the data channel. Therefore, jitter tracking etween clock and data for DJ is correctly captured. The jitter tracking of the transitter rando jitter is again odeled in statistical doain [7]. Finally, ased on the tie-doain histogra, we estiate ISI PDF with extree value decoposition (EVD) [11,12] and generate athtu curves y including equivalent voltage noise fro RJ and other noise sources such as additional independent receiver jitter, sapling offsets and receiver voltage noise. III. Fast Syste Siulation Based on Superposition of Bit or Edge Responses Accurate channel siulation including ISI and rando effects is crucial in designing high-speed I/O systes. Although conventional circuit siulators, such as HSPICE, can accurately characterize the syste response, it is coputationally prohiitive for estiating syste it error rate (BER). To overcoe this liitation, the superposition technique ased on a single it response (SBR) is widely used to calculate the ISI proaility distriution y channel siulators to predict syste BER [1,2,3]. For the SBR ased techniques to accurately siulate syste response, the syste has to e linear tie invariant (LTI) or can e well approxiated as an LTI syste. Differential systes with

7 differential drivers generally satisfy this criterion. In contrast, single-ended signaling systes typically have different rising and falling edge responses due to either asyetric I/O design or isatches etween pull-up and pull-down drivers. For these systes, SBR-ased techniques are no longer applicale. For asyetric cases, SBR ethod results in spurious glitches etween consecutive ones due to the isatch etween rising and falling edges. To handle ore general cases with asyetric rising and falling edges, we can construct the syste response in ters of edge transitions instead of it responses. For the rest of this section, we first review SBR ethod and the doule edge response (DER) ethod. Then we extend DER to ultiple edge response (MER) ethod to handle ore general nonlinearities. A. Matheatical Forulation Single it response (SBR) ethod constructs the syste response of an aritrary input data pattern using SBR fro either siulation or easureent. Assuing the syste is linear, the response to any data pattern is the linear su of the shifted versions of the single it response. Let (t) e the single it response of the channel, t s e the data sapling phase, T e the it tie, and e the th transitted syol. The voltage seen y the receiver s data sapler at the th data saple is given y: y ( t ). (1) s 1 k ( ts ( k 1) T) k 0... The DER ethod decoposes the input data pattern in ters of rising and falling edge transitions. The syste response is calculated y superiposing the shifted version of rising and falling edge responses. where y ( 1 ) s ( t kt y (2) k k k s ) k si ( t) r( t) Vlow if ( i i 1) f ( t) V otherwise. r(t) and f(t) are the rising and falling edge responses respectively, V high and V low are the steady state DC levels in response to a constant strea of ones and zeros respectively. high Both SBR and DER ethods have liited capaility to odel nonlinear driver effects although DER approach iproves the siulation accuracy over SBR approach when the nonlinear driver effect is liited y asyetric rising and falling edge responses within a it tie. However, it cannot copletely capture the nonlinear effect for the rest of the responses as the driver switching activity is not considered during the rest of responses. To overcoe this liitation, we construct edge responses depending on the status of the previous its as follows: r f,..., 2,..., 0 2 ( t) 1 ( t) y y,...,,..., ( t) ( t) y y,...,,..., k 1 k 1 k k ( t ( t kt) kt) V V low high (3) (4)

8 Voltage (V) Voltage (V) Voltage (V) where k is the right ost it index of the it pattern -,, -2-1 such that -k+1 k and - -,, -k+1 -k is the right shifted version of -,, -1 0 where the leftost its exposed y the right shift are filled with -. Based on the constructed ultiple edge responses, the syste response can e estiated siilarly as (2) except now the edge responses are selected depending on previous it patterns. For exaple, for 2 nd order MER, when a rising edge is preceded y 00, 01, 10, and 11 data patterns, r 000 (t), r 010 (t), r 100 (t), and r 110 (t) responses are selected respectively. The th order MER which requires the total of 2 rising and falling edge responses can e prepared using 2 data patterns. Although higher order MERs take longer tie to prepare input wavefors, its ipact on the actual siulation tie is negligile. For any applications, the second order MER, which is ased on rising and falling edges and single-it up and down responses, provides reasonale accuracy. We use this siple version in ost of our nuerical exaples. For highly nonlinear systes, we used the 5 th order MER HSPICE SBR DER MER Ti e (nsec) HSPICE DER MER2 MER5 (a) Tie (nsec) (c) B. Nuerical Exaples HSPICE SBR DER MER Tie (nsec) () Figure responses for (a) an exaple differential signaling syste using SBR, DER, 2 nd order MER, and SPICE; () an exaple single-ended syste with SSTL driver; (c) an exaple single-ended syste with PODL signaling. In this section, we present nuerical exaples to copare SBR, DER and MER ethods against HSPICE. Let us first consider a siple differential signaling syste using a current-ode driver. The syste response of data pattern is approxiated using SBR, DER, and 2 nd order MER. Fig. 2a copares the siulation results. An excellent atch is found for all cases. All three approaches result in siilar errors for this exaple.

9 For the second exaple, an RDRAM eory channel is considered. The overall syste consists of an RDRAM controller with two 16-device eory odules. The siulation is perfored for the write transaction fro the controller to a dra. Fig. 2 shows the calculated wavefors for the sae data pattern. Due to asyetric rising and falling edge responses, the SBR ethod results in erroneous glitches etween continuous 1s. For this exaple, DER and 2 nd order MER ethods oth achieve good accuracy. The third exaple is ased on another popular single-end signaling syste with Pseudo Open Drain Logic (PODL) which is widely used for high-speed graphic eory applications. A significant terination isatch is introduced to ake the siulation ore challenging. For this syste, DER introduces large error and 5 th order MER is required to achieve excellent accuracy. C. EVD and ISI Distriution Calculation Accurate BER siulation needs accurate ISI noise distriution which requires to siulate an extreely large nuer of data its. For exaple, for a typical ackplane channel, the SBR could e ore than 100 its long due to reflections. To capture the exact ISI distriution we need to siulate its. Siulating a liited nuer of its results in truncation of the ISI distriution as shown in Fig. 3. Fig. 3a copares the exact PDF with the histogra generated y a tie-doain siulation of 10 5 its. The exact PDF ends around while the tie-doain histogra truncated at around Fig. 3 shows the ipact of such truncation on the syste perforance estiation. As shown in Fig. 3, the tie-doain approach using truncated distriution directly significantly underestiates the deterinistic noise at lower BER. (a) () Figure 3. (a) Coparison of the exact PDF and the transient PDF generated with 10 5 its. () Coparison of the tiing athtus generated ased on the exact PDF and the transient PDF. To etter estiate the perforance at lower BER, extrapolation is generally used, assuing Gaussian distriution of rando noises [4]. This approxiation fundaentally assues the tail of distriution is generated y unounded Gaussian noises, and it is not

10 adequate for ounded distriutions such as ISI distriution. Recently, the ethod ased on extree value distriution (EVD) has een applied to estiate tails of CDF in the field of coputational iology, where CDFs are used to evaluate the likelihood of a protein structure prediction eing correct [9,10]. EVD theory states that the asyptotic distriutions of axiu (iniu) value in a very large collection of saples fro one rando variale elong to three distriution failies in general regardless the rando variale type [11]. These failies are Guel, Frechet and Weiull whose CDFs are defined y respectively: F( x) e e ( x ) / 0 F( x) (( x ) / ) e F( x) e 1 (( x ) / ) a for x a x x x x (5.a) (5.) (5.c) The second and third types are linked to the first type y shifting and taking ln operation [11]. Depending on applications, one ay choose to use one of the three types. For exaple, for the lifetie distriution odeling in iology, Weiull (5.c) is the est choice ecause tie is always positive and Weiull guarantees positive F(x). For our particular application, we choose to use (5.a) as a starting point to curve fit the tail portion of ISI distriution. The original Guel distriution is slightly odified using second order polynoial for etter curve fitting properties: P( X x) e ( ax 2 x c ) e The results of ln(-ln(f(x))) is used to fit the 2 nd order polynoial series 2 ax x c ln( ln( P( X x))) (7) where a,, and c paraeters can e estiated using the least square approxiation. Then the tail of the exact CDF is estiated and extrapolated to a desired ound fro the truncated tie-doain histogra. Finally, PDF is otained y differentiating the approxiate CDF tail. Fig. 4a shows a good atch etween the extrapolated PDF and the exact PDF. As shown in Fig. 4a, EVD extrapolates the PDF ounds with good accuracy. It extended the ound fro 10-5 to This ound is sufficient to odel BER values elow when coined with rando jitter as shown in Fig. 4. (6)

11 (a) () Figure 4. (a) Coparison of the exact PDF, the original transient PDF and the extrapolated PDF using EVD. () Coparison of the tiing athtus generated ased on the exact PDF and the extrapolated PDF. IV. Link Analysis including Siultaneous Switching Noise To eet the ever increasing andwidth requireent at low cost, single-ended signaling systes, popular in eory I/O interfaces, are pushing a pin data rate to ulti-gps and eyond [8]. At such high data rate, siultaneous switching noise (SSO), which is generally ignored in perforance analysis for differential links, has ecoe one of the ajor ottlenecks in designing single-ended signaling systes [13,14,15]. In this section, we riefly overview how to include SSO noise ipact in link argin analysis ased on MER [19]. Alternatively, [16] approxiates SSO noise in statistical doain y characterizing SSO as a linear ipulse transfer function and treating SSO as a regular crosstalk aggressor. Syste perforance degradation due to SSO noise requires accurate power distriution network (PDN) odel, signal channel odel and correct current profiles that excite the PDN during operation. Moreover, the final syste odel should accurately capture signal-to-signal coupling, power-to-signal coupling, the collapse of power nets and its ipact on link perforance. The signal and power integrity co-siulation ethodology presented in [14,15] elegantly solves the prole. In [14,15], a detailed PDN odel is first generated and then siplified to allow efficient co-siulation with channel odels. Moreover, only a sall nuer of transistor-level driver odels are added. Other drivers are sustituted with current-controlled current sources in order to excite accurate current profiles while at the sae tie aintaining low coplexity of the overall syste odel. The final syste odel is shown in Fig. 5. In this section, we show how the hyrid flow handles SSO noise y treating SSO noise as another for of crosstalk, ased on the SI and PI co-siulation ethodology.

12 We use the GGDR syste for high-end graphics application as a test vehicle. The GDDR syste uses pseudo open drain circuits with push/pull drivers of 60 and 40. The channel odel consists ten coupled transission lines for DQ and RQ. All DQ and RQ lines are point-to-point signaling. By exciting the driver for the victi channel only and oserve the signal at victi channel output right efore the slicer, we can extract the edge responses for the victi channel. Siilarly y exciting the aggressor channels and keep the victi channel quiet, we can extract the edge responses for the crosstalk. In this set up, we only consider the crosstalk fro the nearest neighors and ignore the crosstalk generated fro the second nearest neighors. For worst-case SSO noise generation, we have all other lines (including CCCS) switching at the sae tie and capture the noise generated on the victi line. Note that with the PDN odel incorporated, the crosstalk generated includes the effect of SSO. By doing so, MER naturally siulates SSO noise without any increase in coputational coplexity. Figure 6 shows the correlation etween MER and SPICE for SSO only, crosstalk only and final victi channel response. Fig. 7a shows the eye diagra for the victi channel running at 5Gps with rando data pattern. SSO noises fro other 39 DQs are included. Since MER is tie-doain, it is straightforward to use LinkLa/MER flow to study the effectiveness of different coding schees on final syste argin. Fig. 7 shows the syste argin iproveent with DBI-DC (data us inversion) coding which is used in GDDR4 syste to reduce the ipact of SSO noise [8,20]. Copared with rando data, DBI-DC iproves tiing argin fro 13ps to 25ps at BER. Figure 7c and d copare the ISI distriution and SSO noise distriution on the victi channel for rando data and DBI-DC coded data. As shown in Fig. 7c, DBI-DC shifts the ISI distriution and akes the upper and lower eye asyetric. Statistical siulators such as LinkLa and StatEye can t capture this effect. Fig. 7d shows that DBI-DC indeed tightens the SSO noise distriution significantly and therefore iproves syste argin. TX- PHY +- Vdu1 +- Vdu2 Vdu CCCS MB PKG DQ & RQ VSS VDDR VDDIO - + Channels MB PKG DQ & RQ VSS VDDR VDDIO RX- PHY Vdu Vdu2 - + CCCS Vdu3 - + On- chip Cap (#drv- 5)xI(Vdu) On- chip Cap (# rcv- 5)xI(Vdu) VRM with MB Decaps Figure 5. Final channel odel coining oth signal and power integrity odels [14,15]. The victi channel under consideration is the iddle line highlighted. There are 40 DQs in total, 35 of which are sustituted with CCCS.

13 Voltage (V) Noralized Error Voltage (V) Voltage (V) 0.8 SSO only 0.65 Crosstalk only MER SPICE 0.6 MER SPICE Tie (ns) (a) SSO only Final victi response with crosstalk and SSO Tie (ns) (c) Final victi response MER SPICE Figure 6. MER and SPICE siulated wavefors. a c d 0.5 6% 4% 2% 0% -2% -4% Tie (ns) () Crosstalk only Error in final victi response Tie (ns) (d) Error copared with SPICE Figure 7. Siulated statistical eye diagras and athtus for a 32-it gddr syste with a) no coding and ) DBI-DC coding; Histogras at data sapling location: c) ISI only and d) SSO only.

14 V. Jitter Modeling Methodology As we push the perforance, device jitter takes a significant portion of link tiing udget, particularly for extreely short channel applications such as POP and MCM etc. For these applications, it is crucial to accurately odel tiing jitter sources such as power-supply induced jitter (PSIJ) and rando jitter. This section first discusses jitter characteristics such as jitter aplification through passive channel and jitter nonlinearity. Then, we suarize the jitter odeling ethodology used in the LinkLa/MER flow. Finally, we use the flow to study jitter tracking properties of source-synchronous syste. A. Jitter Aplification and Jitter Nonlinearity The dispersiveness of the passive channel not only results in inter-syol interference, ut also aplifies transitter jitter [7,17,18]. Intuitively, transitter jitter directly odulates the width of the transitted pulses. For extreely lossy channels, transitter jitter ay even result in loss of pulses. Such jitter aplification can severely liit the applicaility of the clock forwarding architecture where a high-speed clock is forwarded to the receiver to avoid the coplexity of recovering clock fro the data signals. As a result, in recent years, jitter aplification through clock channel has gained a lot of interest [7,17,18]. It has een shown that jitter aplification is dependent on the channel loss characteristic as well as the input jitter spectru. Fig. 8 shows the jitter aplification factor (ratio of the output to input jitter) as a function of channel loss as well as the input jitter spectru. Jitter aplification ainly results fro high-frequency jitter. This is consistent with the intuition that high-frequency jitter odulates the transitted pulse width ore heavily than low-frequency jitter therefore results in ore severe jitter aplification. Moreover, jitter aplification grows with channel loss. The channel with 20dB loss at 2.5GHz has uch ore severe jitter aplification for high frequency jitters than the low loss channel. Figure 8. Jitter aplification as a function jitter frequency for two channels with different loss characteristic. The clock is 2.5GHz. For clock channel, the ipact of channel loss can e characterized through a jitter ipulse response. In [7], a closed for for jitter ipulse response was derived ased on

15 Noralized Aplitude the first-order Taylor expansion. The sae approxiation was used in the equivalent voltage noise odel in LinkLa [1] for jitter odeling. However, this approxiation holds only for sall jitters. Even though passive channel is linear in voltage doain with respect to input and output voltages, it is inherently nonlinear for jitter. Fig. 9 shows the jitter ipulse responses for a passive channel easured y perturing a single edge of the clock. Different aounts of perturation results in different noralized jitter ipulse response. This clearly shows that jitter is nonlinear. The linear approxiation ased on first-order Taylor expansion is going to result in large errors if jitter is ig. Even though jitter ipulse response only akes sense for clock signals, the concept of jitter aplification holds for data signal as well. Figure 9. Siulated jitter ipulse responses y perturing a single clock edge (5GHz clock) for a 15 PCB trace with ideal terination. B. Jitter Modeling Methodologies UIs 5ps -5ps 15ps -15ps In recent years, any approaches have een developed to include the ipact of tiing jitter sources on syste argin. Each of the has its advantages and liitations. StatEye [2] odels transitter jitter as receiver sapling distriution and ignores jitter aplification of the passive channel. As shown in Fig. 8, ignoring jitter aplification can result in overly optiistic perforance estiation. LinkLa [1] aps transitter jitter into equivalent voltage noise using first-order Taylor expansion. This approach can capture jitter aplification ut ignores jitter nonlinearity. Therefore, it is not accurate when jitter is ig. In order to accurately handle jitter nonlinearity, jitter has to e siulated in tie doain. [4] separately handles deterinistic jitter (DJ) and rando jitter (RJ). It siulates DJ in tiing doain ut RJ is dealt y extrapolation with dual- Dirac ethod. Therefore, jitter aplification of RJ through the channel is not odeled. Moreover, dual-dirac odel is rather inadequate for accurate BER estiation [9]. As shown in Fig. 1, siilar to [4], we separately handle DJ and RJ. In order to capture jitter nonlinearity, we siulate DJ such as sinusoidal jitter (SJ), periodic jitter (PJ), DCD etc. in tie doain. Different fro [4], we rely on statistical approach to ap RJ into

16 equivalent voltage noise seen y the receiver sapler [1,7]. The equivalent voltage noise odel for RJ presented in [7] uses jitter spectru content and captures jitter aplification of the passive channel. In a syste with a forwarded clock, clock jitter within a certain spectral range can e all or partially tracked out and have inial ipact on the overall syste perforance. The tie-doain ased approach can accurately siulate the edge-to-edge correspondence etween data and clock, therefore can accurately capture the jitter tracking ehavior etween the two. As shown in Fig. 1, data and clock channels are siulated with coon and/or independent deterinistic jitter sources. The received clock channel ticks are used to directly saple the received data wavefor. Thus the histogra generated has already taken the jitter tracking etween data and clock channel into account. On top of this histogra, RJ is apped into equivalent voltage noise and taken into account in the final athtu generation, along with other rando noise sources such as receiver offset and theral noise. Tx Data TXclk TX TX TXd TXc Data Channel Clk Channel RXd RXc AMP Sapler Figure 10. An exaple source synchronous syste with forwarded clock. Rx Data (a) Ideal Rx Clock () Forwarded Clock Figure 11. Statistical eye diagras and athtu curves for the exaple syste shown in Fig. 10 with 32ps (peak to peak) 50MHz SJ injected into the transitter clock. (a) Receiver clock is assued to e ideal; () Receiver clock is a forwarded clock that carries the sae aount of jitter as the data.

17 Figure 12. Jitter tracking vs. SJ frequency for the exaple syste shown in Fig. 10. Fig. 10 shows an exaple source-synchronous syste with a forwarded clock. Any jitter that is present on Txclk is in coon to oth data and clock channel. Additional jitter injection on the Tx clock distriution network, such as power supply induced jitter (PSIJ) is only present in the data channel. Siilarly, the Rx clock distriution network also adds jitter onto the received clock, independent of data. The siulation results shown here ignore these independent jitter coponents for the purpose of illustrating jitter tracking ehavior of forwarded clock architecture. Fig. 11 copares the eye diagras with and without tracking. Fig. 11a assues 32ps (peak to peak) 50MHz SJ is only injected in the data path while Fig. 11 assues the sae aount of SJ injected into oth data and the forwarded clock. The eye diagras clearly show that in the latter case ost of the injected jitter is tracked out. To further illustrate the tracking capaility of forwarded clock architecture, Fig. 12 shows jitter tracking across jitter frequency. Such syste can successfully track at least half of the jitter up to 100MHz. For jitter frequency eyond 250MHz, 32ps peak-to-peak SJ at transitter side results in ore than 32ps argin loss. In this case, jitter on the incoing data and forwarded clock is out of phase and antitracking. This shows, at the design stage, it is iportant to understand the jitter spectru of the syste and the tracking capaility of the clocking architecture. The siulation flow presented in the paper provides such capaility. Conclusion This paper presents a hyrid siulation fraework that ixes statistical and transient siulation ethods to overcoe soe of the liitations of current state-of-the-art link perforance analysis tools. It is the first to have the capaility to capture syste nonlinearity and accurately siulate single-ended signaling systes. Moreover, it cosiulates signal and power integrity and includes siultaneous switching output noise (SSO) into syste argin analysis. Finally, it accurately captures jitter characteristics such as jitter aplification and jitter nonlinearity as well as jitter tracking etween clock and data channels in a clock forwarding architecture.

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