Single-Phase Full-Wave Phase-Controlled Rectifier

Transcription

1 EE410L, Experiment #1 Brett Allan I. Introduction The objective of this experiment is to design, construct, and test a Single-Phase Full-Wave Phase-Controlled Rectifier. The subsequent block diagram depicts the general circuit configuration to be implemented. The design analysis is broken into sections with each corresponding to a block or specific component shown in Figure 1 below. Full - Wave N1 N2 Rectifier *R of Z R of L Trigger Circuit SCR Figure 1: Phase-Controlled Rectifier (Block Diagram) *Note: R Z (i. e., R of Z ) acts as a current limiter for the trigger circuit.

2 II. Design Operational Concept A typical implementation of a phase-controlled rectifier is to provide control over the average voltage delivered to a load. The subsequent discussion describes how phase-control accomplishes this proposition. - Assume that a fully rectified sine wave is provided: - The objective is to vary the average or D.C. voltage to a load. We know - If we can vary α between 0 and 180 we can achieve substantial control over the average voltage seen by our load. α 45 α 160 After examining the foregoing graphs, it become evident that we can control the time (or phase) at which our SCR is pulsed (and subsequently conducts) during each cycle. We are controlling the D.C. voltage seen by the load. This is our primary objective.

3 EE410L, Experiment #1 Brett Allan II. Design (con t) Section #1 Design Specifications: 1) Average maximum load current (I L ): 2.0 Amps 2) User adjustable range angle range: α = 30 to 160 Section #2 Design Analysis: Part 1: Assuring Specified Load Current (I L ) Discussion: The objective herein is to calculate a value of R L (indicated in Figure #1) that will ensure the average load current to be less than or equal to 2.0 Amps. I of L --> V of S V of R E avg SCR Figure 2: Load Current (Simplified Block Diagram) V S = V M avg = 1/π = [ ] = [ ] = [ ] = => E avg = Thus: E avg = ( ) = ( ) => E avg = Volts

4 II. Design (con t) Part 1 (cont.) Now using the equivalent circuit with E avg By KVL E avg = I L R L + V SCR R L = = V SCR 1.0 V = 2.0 Amps R L = = 53.5 Ω Let: R L 54 Ω Power dissipation of R L (worst case) P avg = (R L ) = (2.0) 2 (54) = Watts Part 2: Trigger Circuit Design Discussion: The objective of this section is to design a trigger circuit such that a trigger pulse will be generated to activate the phase angles between 30 and 160. Additionally, this range is to be user adjustable. Applicable Circuit and Calculations Figure 3: Trigger Circuit

5 II. Design (con t) Part 2 (cont.) - We know: ( ) Choose - Hence, we see that after one time constant (τ = RC) the node A is V Z. - The node B constitutes a reference voltage for the P.U.T. (i. e., when the node A is infinitesimally greater than the reference node B, the P.U.T. conducts). - Subsequently, for convenience, we will establish a reference node B equal to V Z. Thus: V B = VZ V B = * (15V) By V.D. : V B = 9.48 Volts Solving for R 2 : = kω V B = 9.48 V Choose R 1 = 2.0 kω Let R 1 = 2.0 kω & R 2 = 1.2 kω Solving for ID (Assuming P.U.T. gate current is negligible) ) = 4.69 ma Power Dissipated by Voltage Divider (worst case R 1 ) 75.2 Watts

6 II. Design (con t) Part 2 (cont.) Timing Analysis for R-C Charging Branch Input signal f = 60 Hz Rectified Signal f = 120 Hz - Solving for the number of milliseconds per degree of phase shift Now solve for the time required to shift 30 and 160 in phase. T α = 30 = msec/degree (30 ) = msec T α = 160 = msec/degree (160 ) = msec msec τ msec The foregoing range of τ will ensure a phase shift range from 30 to 160 as long as the reference voltage is approximately 0.632V Z - Solving for R adj and C: Τ = R adj C Choose C = 0.2 µf R adj α = 30 = = ( τ = R adj α = 160 = = ( τ = = 6,940 Ω = 37,020 Ω (Note: A 50 kω pot will be implemented)

7 II. Design (con t) Part 3: Trigger Circuit Current Limiter (R Z ) Discussion: In this section the worst case current requirements calculated in the previous sections will be used to determine the minimum current required to drive the trigger circuit. Subsequently, R Z and its power dissipation are determined. Applicable Circuit and Calculations I Z required to drive trigger circuit (worst case) I Z = I ZENER + I R + I D = ( ) ma = 32 ma (I ZENER 25 ma to ensure Zener operates in avalanche mode.) Figure 4: Trigger Circuit Current Limiter Let I Z = 40 ma = 2,350.0 Ω Choose R Z = 2.2 kω Power Dissipation through R Z 3.93 Watts III. Experimental Circuit (Complete Schematic) Discussion: The subsequent circuit depicts the actual circuit (with measured component values to be employed as a single-phase full-wave phase-controlled rectifier.

8 III. Experimental Circuit (con t) Circuit (w/ component values): Figure 5: Complete Single-Phase Full-Wave Phase Controlled Rectifier Schematic IV. Bill of Materials Component Types, Values, & Part Numbers Component Value Rating Specs Part No. Rectifier V 2.0 A NTE 167 R Z 2.52 kω 5.0 Watts --- V Z V / 5 Watts NTE 5130 A R adj 0 50 kω 1 Watt --- C F R kω 0.5 Watts --- R kω 0.5 Watts --- R G 50 Ω 0.5 Watts --- SCR V/4 Amps (RMS) NTE 5455 R L 75 Ω High Power Decade EE 5412 P.U.T V / I ± 20 ma NTE 6402

9 V. Experimental Results Discussion: The circuit indicated in Figure #5 was established and tested as a phase-controlled rectifier. - Initially, the rectifier and Zener diode were tested to insure proper operation prior to connecting the reminder of the circuit. - The Zener diode was observed to clamp input 15 Volts while R Z acted as a current limier for the Zener diode. - The rectifier was observed to generate a fully rectified sine wave at its output terminals. - Subsequently, the load and remaining trigger circuit were connected (as shown in Figure #5) and the power scope placed across R L. - R adj was adjusted between 5 kω and 40 kω and the phase angle was observed shifting between 20 and 170. Typical Phase Shift Waveform across R L : - Finally, α was varied between 30 and 160 while monitoring I L and V L. Corresponding data tables, plots, and conclusions were generated. Part 1 Table I Half Divisions on the Scope Test Data for SCR type Phase-Controlled Rectifier Division Phase Angle α V L Volts I L (A)(V L /R L ) (degree)

10 V. Experimental Results (con t) Part 2 Table II Test Data for Load Variation of SCR type Phase-Controlled Rectifier α ( ) R L V L I L (Ω) (V) (A) < < < < < < Plot of SCR type Phase-Controlled Rectifier (Load Voltage vs. Phase Angle α) y = x x R² =

11 Load Voltage VL (Volts) EE410L, Experiment #1 Brett Allan V. Experimental Results (con t) Plot for Load Variation of SCR type Phase-Controlled Rectifier Load Current IL (Amps) VI. Conclusion The objective of this experiment was to design, build, and test a Full-Wave Phase-Controlled Rectifier. Initially, we generated a design to provide triggering pulses to the SCR for phase angles between 30 and 160. Additionally, we were careful to ensure sufficient current to drive the trigger circuit under worst-case conditions. The worst case power dissipation was determined for each element and the appropriate components were selected. Subsequently, the network indicated in Figurer #5 was constructed and tested. The test results were very favorable as the analogue phase-controlled rectifier performed flawlessly to beyond the specifications. The phase angle was controllable between 20 and 170 and the load current never exceeded 2 Amps. With regard to the experimental plots, the V L, V S and α characteristic results were just as expected. Additionally, V L remained approximately constant as I L varied at various phase angles.