PART MAX1684EEE MAX1685EEE. Maxim Integrated Products 1

Transcription

1 ; Rev 2; 7/1 ELUTION KIT ILBLE Low-Noise, 14 Input, 1, PWM General Description The / are high-efficiency, internalswitch, pulse-width modulation (PWM) step-down switching regulators intended to power cellular phones, communicating PDs, and handy-terminals. These devices deliver a guaranteed 1 output current from two lithium-ion (Li+) batteries. Their wide-input voltage range of 2.7 to 14 gives design flexibility and allows batteries to charge from a wall cube, since the Is operate at the higher voltages that occur when the battery is removed. The output voltage is preset to 3.3 or can be externally adjusted from 1.25 to IN. The low on-resistance power switch and built-in synchronous rectifier provide high efficiencies of up to 96%. There are four modes of operation: fixed-frequency, normal, low-power, and shutdown. The fixed-frequency PWM mode of operation offers excellent noise characteristics. The normal mode maintains high efficiency at all loads. The low-power mode is used to conserve power in standby or when full load is not required. The shutdown mode is used to power down the device for minimal current draw. The runs at 3kHz for applications that require highest efficiency. The runs at 6kHz to allow the use of smaller external components. These devices can also be synchronized to an external clock. Other features include a % duty cycle for low-dropout applications, an auxiliary 3/5m output, and a 1% accurate reference. Both devices are available in a space-saving 16-QSOP package. n evaluation kit is also available to help speed designs. For a similar device in a -pin µmx package with lower input voltage requirements (5.5 max), refer to the MX1692 data sheet. Features Up to 96% Efficiency 1 Guaranteed Output urrent % Duty ycle in Dropout 2.7 to 14 Input Range (15 bsolute Max) ±1% ccurate Reference Output.24Ω P-hannel On-Resistance Synchronizable Switching Frequency Fixed-Frequency PWM Operation 3kHz () 6kHz () 15µ Normal-Mode Quiescent urrent 25µ Low-Power Mode Quiescent urrent 2µ Shutdown urrent Dual Mode Fixed 3.3 (±1%) Output or djustable Output (1.25 to IN) Small 16-QSOP Package uxiliary Output (L): 3/5m PRT EEE EEE Ordering Information TEMP RNGE -4 to to +85 PIN-PKGE 16 QSOP 16 QSOP Typical Operating ircuit / ellular Phones Two-Way Radios and Walkie-Talkies omputer Peripherals Personal ommunicators pplications INPUT 2.7 TO 14 + IN IN SHDN LX GND OUTPUT 3.3 T 1 + PDs and Handy-Terminals H L BOOT STBY SYN/PWM Pin onfiguration appears at end of data sheet. FB REF Dual Mode is a trademark of Maxim Integrated Products, Inc. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 / BSOLUTE MXIMUM RTINGS IN to GND to +15 IN to PGND to ( IN +.3) LX to PGND to ( IN +.3) PGND to GND...±.3 SHDN to GND to ( IN +.3) ILIM/SS, FB,, BOOT, REF to GND to ( L +.3) H to IN...-6 to +.3 L, STBY, SYN/PWM to GND to +6 Reference urrent...±1m Stresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELETRIL HRTERISTIS L urrent...-1m to +m LX Peak urrent (Internally Limited) ontinuous Power Dissipation (T = +7 ) 16-Pin QSOP (derate 8.3mW/ above +7 )...667mW Operating Temperature Range...-4 to +85 Junction Temperature Storage Temperature Range to +15 Lead Temperature (soldering, s)...+3 ( IN = SHDN = 6, STBY = SYN/PWM = L, BOOT = OUT, FB = GND, circuit of Figure 1, T = to +85, unless otherwise noted. Typical values are at T = +25.) PRMETER SYMBOL ONDITIONS MIN TYP MX Input oltage Range Feedback oltage FB FB = OUT, I LOD = to Output oltage (3.3 Mode) OUT FB = GND, I LOD = to Output Load Regulation FB = OUT, I LOD = to 1.1 Output urrent apability IN = 5 to 14 1 Output djust Range BOOT = GND (Note 1) REF IN FB Input urrent I FB FB = On-Resistance, P-hannel High-side switch, IN = I LX = 1 IN = On-Resistance, N-hannel Low-side switch, IN = 2.7, I LX = m 3 8 urrent Limit in PWM Mode I LIM Pulse-Skipping urrent Threshold SYN/PWM = low urrent Limit in Low-Power Mode urrent Limit, N-hannel Zero rossing Threshold Quiescent Power onsumption I LIMLP STBY = low SYN/PWM = high SYN/PWM = low PWM mode, SYN/PWM = high, BOOT = 3.3 (Note 2) Normal mode, SYN/PWM = low, BOOT = 3.3 (Note 2) UNITS % n Ω Ω m m m mw Low-power mode, STBY = low, BOOT = 3.3 (Note 2)

3 ELETRIL HRTERISTIS (continued) ( IN = SHDN = 6, STBY = SYN/PWM = L, BOOT = OUT, FB = GND, circuit of Figure 1, T = to +85, unless otherwise noted. Typical values are at T = +25.) PRMETER Quiescent Supply urrent in Dropout Shutdown Supply urrent LX Leakage urrent Oscillator Frequency SYN apture Range Maximum Duty ycle onstant-frequency Minimum Duty ycle Reference Output oltage Reference Load Regulation Reference Supply Regulation L Regulator Output oltage L Dropout oltage L Undervoltage Lockout Threshold H with Respect to IN BOOT Switchover Threshold Thermal Shutdown Threshold ILIM/SS Source urrent Logic Input High oltage Logic Input Low oltage Logic Input urrent SYN/PWM Pulse Width SYMBOL I LX f OS REF IH IL ONDITIONS STBY = low, IN = 2.7 MIN TYP MX UNITS SHDN = low 2 6 µ IN = 14, LX = or 14, SHDN = low (Note 3) % I REF = µ < I REF < 5µ 4 15 m 2.7 < BOOT < m IN = 3 to 14, BOOT = GND, I L = to 5m BOOT = GND, I L = 5m BOOT = GND, L falling edge, typical hysteresis is 4m I H = -1m BOOT falling edge, typical hysteresis is Typical hysteresis is + (Note 4) ILIM/SS = µ SHDN, STBY, SYN/PWM High or low period SHDN, STBY, SYN/PWM -1 1 µ µ µ khz khz % m ns / 3

4 / ELETRIL HRTERISTIS ( IN = SHDN = 6, STBY = SYN/PWM = L, BOOT = OUT, FB = GND, circuit of Figure 1, T = -4 to +85, unless otherwise noted.) (Note 5) PRMETER SYMBOL ONDITIONS MIN MX UNITS Input oltage Range Output Feedback oltage FB FB = OUT, I LOD = to Output oltage (3.3 Mode) OUT FB = GND, I LOD = to Output urrent apability IN = 6 to 14 1 Output djust Range BOOT = GND (Note 1) REF IN FB Input urrent I FB FB = n urrent Limit in PWM Mode I LIM urrent Limit in Low-Power Mode Quiescent Power onsumption I LIMLP STBY = low m Normal mode, SYN/PWM = low, BOOT = 3.3 (Note 2) Low-power mode, STBY = low, BOOT = 3.3 (Note 2).27 Shutdown Supply urrent SHDN = low 6 µ Oscillator Frequency f OS khz Reference Output oltage I REF = L Regulator Output oltage IN = 3 to 14, BOOT = GND, I L = to 5m 2 mw L Undervoltage Lockout Threshold BOOT = GND, L falling edge, typical hysteresis is 4m H with Respect to IN I H = -1m BOOT Switchover Threshold BOOT falling edge, typical hysteresis is ILIM/SS Source urrent ILIM/SS = µ Logic Input High oltage IH 2 SHDN, STBY, SYN/PWM Logic Input Low oltage IL.7 Note 1: The output adjust range with BOOT connected to OUT is REF to 5.5. onnect BOOT to GND for OUT > 5.5. Note 2: The quiescent power-consumption specifications include chip supply and gate-drive loss only. Divide these values by IN (6) to obtain quiescent currents. In normal and low-power modes, chip supply current dominates and quiescent power is proportional to BOOT (BOOT connected to OUT). In PWM mode, gate-drive loss dominates and quiescent power is proportional to IN ( IN - H ). In addition, IR losses in power switches and external components typically increase PWM quiescent power consumption by 5mW to mw. Note that if the device is not bootstrapped, additional power is dissipated in the L linear regulator. Note 3: When the duty factor ( OUT / IN ) is less than this value, the switching frequency decreases in PWM mode to maintain regulation. Note 4: Thermal shutdown is disabled in low-power mode (STBY = low) to reduce power consumption. Note 5: Specifications to -4 are guaranteed by design, not production tested. 4

5 (ircuit of Figure 1, T = +25, unless otherwise noted.) B ( IN = 3.3, OUT = 1.8, 2.5) F D E : OUT = 2.5 LP MODE B: OUT = 1.8 LP MODE : OUT = 2.5 NORM MODE D: OUT = 1.8 NORM MODE E: OUT = 2.5 PWM MODE F: OUT = 1.8 PWM MODE.1 1, ( OUT = 5) D 9 B E 8 E F : IN = 6 LP MODE B: IN = 9 LP MODE : IN = 12 LP MODE D: IN = 6 NORML MODE E: IN = 9 NORML MODE F: IN = 12 NORML MODE.1 1, B ( OUT = 3.3).1 1, D : IN = 4 LP MODE B: IN = 12 LP MODE : IN = 4 NORML MODE D: IN = 12 NORML MODE /85 toc1 /85 toc4 /85 toc B ( OUT = 3.3) : IN = 4 LP MODE B: IN = 12 LP MODE : IN = 4 NORML MODE D: IN = 12 NORML MODE.1 1, B ( OUT = 5, PWM MODE) 1, D : IN = 6 B: IN = 9 : IN =12 ( OUT = 5 PWM MODE) IN = 6 IN =12 1, Typical Operating haracteristics IN = 9 /85 toc2 /85 toc5 /85 toc B ( OUT = 3.3, PWM MODE) D : IN = 4 B: IN = 5 : IN = 9 D: IN = 12 1, ( OUT = 3.3, PWM MODE) IN = 4 IN = 9 IN = 12 IN = 5 1, ( OUT = 5) B.1 1, F : IN = 6 LP MODE B: IN = 9 LP MODE : IN = 12 LP MODE D: IN = 6 NORML MODE E: IN = 9 NORML MODE F: IN =12 NORML MODE E D /85 toc3 /85 toc6 /85 toc9 / 5

6 / Typical Operating haracteristics (continued) (ircuit of Figure 1, T = +25, unless otherwise noted.) LOD URRENT () MXIMUM LOD URRENT vs. INPUT OLTGE PWM OR NORML MODE INPUT OLTGE () /85 toc SFE OPERTING RE INPUT OLTGE () OUT = 3.3 /85 toc11 DROPOUT OLTGE (m) 4 3 DROPOUT OLTGE vs. LOD URRENT OUT = OUT = 5 INDUTOR RESISTNE INLUDED /85 toc12 1 NO-LOD SUPPLY URRENT vs. INPUT OLTGE /85 toc NO-LOD SUPPLY URRENT vs. INPUT OLTGE ( OUT = 3.3, PWM MODE) /85 toc PWM FIXED-FREQUENY OPERTION RE M X1684/85 toc15 SUPPLY URRENT (µ) 8 6 NORML MODE SUPPLY URRENT (m) INPUT OLTGE () LOW-POWER MODE INPUT OLTGE () INPUT OLTGE () OUTPUT OLTGE () LOD-TRNSIENT RESPONSE /85 toc16 SWITHING WEFORM /85 toc17 SWITHING WEFORM /85 toc18 I LOD 5m/div OUT m/div LX 5/div OUT 5m/div I LX m/div I LX m/div 2ms/div, I LOD =.1m TO 1, OUT = 3.3, IN = 5, SYN/PWM = 3.3 1µs/div, I LOD = m, OUT = 3.3, IN = 5, SYN/PWM = 3.3 1µs/div, I LOD = m, OUT = 3.3, IN = 5, SYN/PWM = 3.3 6

7 Typical Operating haracteristics (continued) (ircuit of Figure 1, T = +25, unless otherwise noted.) IN 5/div OUT m/div LINE-TRNSIENT RESPONSE /85 toc19 2ms/div, I LOD = m, IN = 5 TO, SYN/PWM = 3.3 SHDN 5/div I IN 5m/div STRTUP URRENT ms/div /85 toc, I LOD = m, OUT = 3.3, IN = 5, ILIM/SS =.1µF, SYN/PWM = 3.3 / PIN , NME H IN IN L GND REF FB SYN/PWM ILIM/SS STBY BOOT LX SHDN PGND FUNTION Pin Description High-Side MOSFET Gate Bias. Bias voltage for P-channel switch. Bypass to IN with a.1µf capacitor. nalog Supply oltage Input. onnect to IN with a.2in metal trace. Bypass to PGND with a.1µf capacitor. Supply oltage Input Logic Supply oltage Output and I Logic Supply. Sources 5m for external loads. Bypass to GND with 1µF capacitor. nalog Ground Reference Output reference output supplies µ for external loads. Bypass to GND with.1µf capacitor. Dual-Mode Feedback Input. onnect FB to OUT for 1.25 output. onnect to an external resistor divider to adjust the output voltage. onnect to GND to set output voltage to 3.3. Integrator apacitor onnection. onnect a.1µf capacitor to GND. SYN/PWM Input: For synchronized-pwm operation, drive with TTL level, 5% square wave. onnect to L for PWM mode. onnect to GND for normal mode. urrent-limit djust/soft-start Input. See the urrent Limit and Soft-Start section. Standby ontrol Input. onnect to L for normal operation. onnect to GND for low-power mode (Table 1). This pin overrides SYN/PWM setting. Bootstrap Input. onnection for the bootstrap switch and internal feedback path. onnect BOOT to OUT for OUT < 5.5. onnect BOOT to GND for OUT > 5.5. Inductor onnection. Drain for internal P-channel MOSFETs. onnect inductor from LX to OUT. ctive-low Shutdown Input. onnect to ground for shutdown. SHDN can withstand the input voltage. Power Ground 7

8 /.1µF INPUT 1 L OUTPUT 14 MX µh* 3 H 13, T 1 IN LX 22µF 2 IN MBRS OUT µf 13LT3.1µF 16 PGND 5 ON/OFF 15 GND SHDN 4 12 L BOOT 1µF 11 STBY 9 7 SYN/PWM FB ILIM/SS.1µF (OPTIONL) 8.1µF REF 6 Figure 1. Standard pplication ircuit.1µf *SUMID D54-; USE 22µH FOR Detailed Description The / step-down, PWM D-D converters provide an adjustable output from 1.25 to the input voltage. They accept inputs from 2.7 to 14 and deliver up to 1.6. n internal MOSFET and synchronous rectifier reduce P board area while maintaining high efficiency. Operation with up to % duty cycle minimizes dropout voltage. Fixed-frequency PWM operation reduces interference in sensitive communications and data-acquisition applications. SYN input allows synchronization to an external clock. The / can operate in five modes. Setting the devices to operate in the appropriate mode for the intended application (Table 1) achieves highest efficiency. PWM ontrol The / use an oscillator-triggered minimum/maximum on-time current-mode control scheme (Figure 2). The minimum on-time is typically 2ns unless the regulator is in dropout. The maximum on-time is 2 / f OS, allowing operation to % duty cycle. urrent-mode feedback provides cycle-by-cycle current limiting for superior load- and line-transient response. t each falling edge of the internal oscillator, the internal P-channel MOSFET (main switch) turns on. This allows current to ramp up through the inductor to the load and stores energy in a magnetic field. The switch remains on until either the current-limit comparator trips, the maximum on-time expires, or the PWM comparator signals that the output is in regulation. When the switch turns off during the second half of each cycle, the inductor s magnetic field collapses, releasing the stored energy and forcing current through the output diode to the output filter capacitor and load. The output filter capacitor stores charge when the inductor current is high and releases it when the inductor current is low, smoothing the voltage across the load. During normal operation, the / regulate the output voltage by switching at a constant frequency and modulating the power transferred to the load on each cycle using the PWM comparator. multiinput comparator sums three weighted differential signals (the output voltage with respect to the reference, the main switch current sense, and the slope-compensation ramp) and changes states when a threshold is reached. It modulates output power by adjusting the Table 1. Operating Modes MODE PWM Sync PWM Normal Low Power Shutdown SYN/PWM H locked L X X STBY H SHDN H FUNTION Fixed-frequency PWM TYPIL OUTPUT PBILITY () H H Fixed-input clock-frequency PWM 1.6 PFM at light loads (<15m); fixedfrequency PWM at heavy loads H H 1.6 (>15m) L H Low-power or standby mode 16m X L ircuit disabled 1.6 8

9 ILIM/SS IN IN SHDN L REF L REF THERML SHUTDOWN UNDEROLTGE OMPRTOR 2.5 ON PWM OMPRTOR 4µ PFM URRENT OMPRTOR L ILIM THRESHOLD ILIM OMPRTOR ONTROL ND DRIER LOGI H H LX / SYN/PWM STBY SYN ND STNDBY ONTROL OS SLOPE OMPENSTION PWM MODE NORML MODE LOW-POWER MODE ZERO-ROSSING OMPRTOR L PGND 2.5 PFM OMPRTOR BOOT GM INTEGRTOR FB.125 GND Figure 2. Functional Diagram 9

10 / inductor peak current during the first half of each cycle, based on the output error voltage. The / s loop gain is relatively low to enable the use of a small, low-value output filter capacitor. The 1.4% transient load regulation from to 1 is compensated by an integrator circuit that lowers D load regulation to.1% typical. Slope compensation accounts for the inductor-current waveform s down slope during the second half of each cycle, and eliminates the inductorcurrent staircasing characteristic of current-mode controllers at high duty cycles. PFM ontrol In low-power mode, the / switch only as needed to service the load. This reduces the switching frequency and associated losses in the P-channel switch, the synchronous rectifier, and the external inductor. During this PFM operation, a switching cycle initiates when the PFM comparator senses that the output voltage has dropped too low. The P-channel MOSFET switch turns on and conducts current to the output-filter capacitor and load. The / then wait until the PFM comparator senses a low-output voltage again. In normal mode at light load (<15m), the device also operates in PFM. The PFM current comparator controls both entry into PWM mode and the peak switch current during PFM operation. onsequently, some jitter is normal during transition from PFM to PWM with loads around 15m, and it has no adverse impact on regulation. % Duty-ycle Operation s the input voltage drops, the duty cycle increases until the P-channel MOSFET turns on continuously, achieving % duty cycle. Dropout voltage in % duty cycle is the output current multiplied by the onresistance of the internal switch and inductor, approximately.35 (IOUT = 1). ery Low Duty-ycle Operation Because of the P-channel minimum on-time and deadtime (duration when both switches are off), the /s switching frequency must decrease in PWM or normal mode to maintain regulation at a very low duty cycle. The total P-channel ontime and dead-time is 29ns typical. s a result, the / maintain fixed-frequency regulation at no load for IN up to OUT and 5 OUT, respectively (see PWM Fixed-Frequency Operation rea graph in the Typical Operating haracteristics). For higher IN at no load, the frequency decreases based on the following equation: f = OUT / ( IN 29ns) t medium- to full-load current (>m), IN can increase slightly higher before the frequency decreases. Synchronous Rectification lthough the primary rectifier is an external Schottky diode, a small internal N-channel synchronous rectifier allows PWM operation at light loads. During the second half of each cycle, when the inductor current ramps below the zero-crossing threshold or when the oscillator period ends, the synchronous rectifier turns off. This keeps excess current from flowing backward through the inductor. hoose an appropriate inductor to limit the PWM ripple current through the N-channel FET to 4m P-P. urrent Limit and Soft-Start The voltage at ILIM/SS sets the PWM current limit (I LIM = 1.75) and the low-power current limit (I LIMLP = 38m). The PWM current limit applies when the device is in PWM mode, in synchronized PWM mode, or delivering a heavy load in normal mode (Table 1). The I LIMLP limit applies when the device is in low-power mode. n internal 4µ current source pulls ILIM/SS up to L. To use the maximum current-limit thresholds, leave ILIM/SS unconnected or connect it to a soft-start capacitor. onnect an external resistor from ILIM/SS to GND to adjust the current-limit thresholds. The PWM current-limit threshold is (ILIM R ILIM/SS 4µ) / REF and is adjustable from.5 to The low-power current-limit threshold is equal to (ILIMLP RILIM/SS 4µ) / REF and is adjustable from 1m to 38m. For example, when RILIM/SS is 156kΩ, the PWM current limit threshold is.88 and the low-power current limit threshold is.19. onnect a low-value capacitor from ILIM/SS to GND to achieve soft-start, limiting inrush current. ILIM/SS internally shorts to GND in shutdown to discharge the soft-start capacitor. Do not connect ILIM/SS to REF or L. Determine the soft-start duration by: tsoft-strt = ILIM/SS (1.25 / 4µ) where t SOFT-STRT is the time from SHDN going high to the regulator being able to supply full load current. For example, a.1µf capacitor yields 31ms of soft-start.

11 The output current capability for each mode is determined by the following equations: I OUTMX = I LIM -.5 I RIPPLE (for PWM and normal modes) IOUTMX =.5 ILIMLP (for low-power mode) where: IRIPPLE = ripple current = (IN - OUT) OUT / (IN f OS L) I LIM = current limit in PWM mode I LIMLP = current limit in low-power mode Internal Low-oltage Regulators and Bootstrap (BOOT) The / have two internal regulators (H and L) that generate low-voltage supplies for internal circuitry (see the Functional Diagram). The H regulator generates -4.6 with respect to IN to supply the P-channel switch and driver. Bypass H to IN with a.1µf capacitor. The L regulator generates a 3 output at L to supply internal low-voltage blocks, as well as the N-channel switch and driver. Bypass L to GND with a 1µF capacitor. To reduce the quiescent current in low-power and normal modes, connect BOOT to OUT. fter startup, when BOOT exceeds 2.6, the internal bootstrap switch connects L to BOOT. This bootstrap mechanism causes the internal circuitry to be supplied from the output and thereby reduces the input quiescent current by a factor of OUT / IN. Do not connect BOOT to OUT if the output voltage exceeds 5.5. Instead, connect BOOT to GND to keep L regulated at 3. L has a 5m capability to supply external logic circuitry and is disabled in shutdown mode. pplications Information Output oltage Selection onnect FB to GND to select the internal 3.3 output mode. onnect BOOT to OUT in this configuration. To select an output voltage between 1.25 and IN, connect FB to a resistor voltage-divider between the output and GND (Figure 3). Select R2 in the kω to kω range. alculate R1 as follows: R1 = R2 [( OUT / FB) - 1] where FB = FB Figure 3. Setting Output oltage onnect a small capacitor across R1 to compensate for stray capacitance at the FB pin: 7 5 ( ) 1= R2 where: R2 = kω, use 4.7pF. Inductor Selection The /s high switching frequency allows the use of small surface-mount inductors. Table 2 shows a selection of suitable inductors for different output voltage ranges. alculate the minimum inductor by: L =.9( OUT -.3) / (I RIPPLE MX f OS ) where: I RIPPLE MX = should be less than or equal to 4m f OS = 3kHz () or 6kHz () apacitor Selection Select input and output filter capacitors to service inductor currents while minimizing voltage ripple. The input filter capacitor reduces peak currents and noise at the voltage source. The /s loop gain is relatively low to enable the use of small, lowvalue output filter capacitors. Higher capacitor values provide improved output ripple and transient response. Low-ESR capacitors are recommended. apacitor ESR is a major contributor to output ripple (usually more than 6%). void ordinary aluminum electrolytic capacitors, as they typically have high ESR. Low-ESR aluminum electrolytic capacitors are acceptable and relatively inexpensive. Low-ESR tantalum capacitors are better and provide a compact solution for spaceconstrained surface-mount designs. Do not exceed the ripple-current ratings of tantalum capacitors. eramic capacitors offer the lowest ESR overall. Sanyo OS-ON R1 R2 OUT 1 / 11

12 / capacitors have the lowest ESR of the high-value electrolytic types. Use ceramic and OS-ON capacitors for very compact, high-reliability, or wide-temperature applications, where expense is justified. When using very low ESR capacitors, such as ceramic or OS-ON, check for stability while examining load-transient response, and increase the output compensation capacitor if needed. Table 3 lists suppliers for the various components used with the /. Ensure that the minimum capacitance value and maximum ESR values are met: OUT > I OUT MX / ( OUT Load Reg f OS ) RESR < 2 Load Reg OUT /I OUT MX Table 2. Inductor and Minimum Output apacitor Selection OUT () L (µh) (3kHz) MIN OUT (µf) where I OUT MX = 1, Load Reg 1.4%, and f OS = 3kHz () or 6kHz (). Output Diode Selection Use a 1 external Schottky diode (MBRS13LT3 or equivalent) for the output rectifier to pass inductor current during the start of the second half of each cycle. This diode operates before the internal N-channel MOSFET completely turns on and during high-current operation. Use a Schottky diode to avoid forward biasing the internal body diode of the N-channel MOSFET. L (µh) (6kHz) MIN OUT (µf) 1.25 to to 4 4 to 6 6 to Table 3. omponent Suppliers SUPPLIER PHONE FX PITORS X Matsuo Sanyo Sprague INDUTORS oilcraft Murata-Erie Sumida µF IN 1µF.1µF.1µF.1µF IN IN H SHDN STBY L SYN/PWM REF ILIM/SS LX FB BOOT PGND GND MBRS 13LT3 L R1 R2 1 - OUT TO -5.5 µf TDK µF.1µF DIODES Motorola IN, MX = 14 - OUT Figure 4. Inverting Output R2 - OUT = ( + 1 ) R1 12

13 Inverting Output Interchanging the ground and OUT connections yields a negative voltage supply (Figure 4). The component selections are the same as for a positive voltage converter. The absolute maximum ratings limit the output voltage range to to -5.5 and the maximum input voltage range to 14 - OUT. P Board Layout High switching frequencies and large peak currents make P board layout a very important part of design. Poor design can result in excessive EMI on the feedback paths and voltage gradients in the ground plane, both of which result in instability or regulation errors. Power components such as the / inductor, input filter capacitor, and output filter capacitor should be placed as close together as possible, and their traces kept short, direct, and wide, onnect their ground nodes in a star-ground configuration. Keep the extra copper on the board and integrate into ground as a pseudo-ground plane. When using external feedback, the feedback network should be close to FB, within.2 inch (5mm), and the output voltage feedback should be tapped as close to the output capacitor as possible. Keep noisy traces, such as those from LX, away from the voltage feedback network. Separate the noisy traces by grounded copper. Place the small bypass capacitors within.2 inch (5mm) of their respective inputs. The evaluation kit manual illustrates an example P board layout, routing, and pseudo-ground plane. onnect IN to IN with a short (.2 inch) metal trace or a 1Ω resistor and bypass IN to PGND with a.1µf capacitor. This acts as a lowpass filter to reduce noise at IN. TOP IEW H IN IN L GND REF FB Pin onfiguration QSOP TRNSISTOR OUNT: PGND 15 SHDN 14 LX 13 LX 12 BOOT 11 STBY ILIM/SS 9 SYN/PWM hip Information / 13

14 / Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to QSOP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 Maxim Integrated Products, 1 San Gabriel Drive, Sunnyvale, Maxim Integrated Products Printed US is a registered trademark of Maxim Integrated Products.