Rev 0; 9/96 EVALUATION KIT MANUAL AVAILABLE 100% Duty Cycle, Low-Noise, Step-Down, PWM DC-DC Converter TOP VIEW GND R2

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1 Rev ; 9/96 ELUTION KIT MNUL ILLE 1% Duty ycle, Low-Noise, General Description The high-efficiency, step-down D-D converter provides an adjustable output from 1.25 to 1.5. It accepts inputs from 3.5 to 11 and delivers 6m. Operation to 1% duty cycle minimizes dropout voltage (3m typ at 5m). Synchronous rectification reduces output rectifier losses, resulting in efficiency as high as 95%. Fixed-frequency pulse-width modulation (PWM) reduces noise in sensitive communications applications. Using a high-frequency internal oscillator allows tiny surface-mount components to reduce P board area, and eliminates audio-frequency interference. SYN input allows synchronization to an external clock to avoid interference with sensitive RF and dataacquisition circuits. The features current-mode operation for superior load/line-transient response. ycle-by-cycle current limiting protects the internal MOSFET and rectifier. low-current (2.5µ typ) shutdown mode conserves battery life. pplications Portable Instruments ellular Phones and Radios Personal ommunicators Distributed Power Systems omputer Peripherals Features 95% Efficiency 6m Output urrent ycle-by-ycle urrent Limiting Low-Dropout, 1% Duty-ycle Operation, 3m at 5m Internal.6Ω (typ) MOSFET Internal Synchronous Rectifier High-Frequency urrent-mode PWM External SYN or Internal 3kHz Oscillator Guaranteed 26kHz to 34kHz Internal Oscillator Frequency Limits 2.5µ Shutdown Mode Ordering Information PRT TEMP. RNGE PIN-PKGE H/D HES to +7-4 to +85 Dice* 8 SO *ontact factory for availability. Dice are tested at T = +25. Typical Operating ircuit Pin onfiguration IN = 3.5 to 11 + LX 33µH OUT = 3.3 TOP IEW R1 47µF.33µF 165kΩ 47µF 1 1pF ON OFF SHDN SYN F L GND R2 1kΩ 2.2µF.47µF OUT = 1.25 (R1/R2 + 1) SHDN F L SO LX SYN GND Maxim Integrated Products 1 For free samples & the latest literature: or phone

2 SOLUTE MXIMUM RTINGS, F, SYN, L to GND to +6 + to GND to +12 SHDN, LX to GND to (+ +.3) PGND to GND to +.3 ontinuous Power Dissipation (T = +7 ) SO (derate 9.9mW/ above +7 )...471mW Operating Temperature Ranges H/D... to +7 HES...-4 to +85 Storage Temperature Range to +165 Lead Temperature (soldering, 1sec) Stresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELETRIL HRTERISTIS (+ = +7, PGND = GND =, SHDN = +, (T = to T MX ), unless otherwise noted.) PRMETER SYMOL ONDITIONS MIN TYP MX UNITS Supply Range Quiescent Supply urrent (PWM Mode) I +, PWM I OUT = m, SYN = m Quiescent Supply urrent (PFM Mode) I +, PFM I OUT = m, SYN = GND.2.5 m Shutdown Supply urrent I +, SHDN SHDN = GND µ Output oltage Range OUT, RNGE ircuit of Figure Load Regulation I OUT = m to 5m.5 %/m Line Regulation IN = 4 to 11, PWM mode.2 %/ PWM F Feedback Threshold F SYN = 3., PWM duty cycle = 5% F Input urrent I F F = 1.3 ±.1 µ SYN Frequency f SYN khz SYN Pulse Width High or Low SYN, PW 5 ns PWM Maximum Duty ycle PWM, DUTY SYN = 3., F = % PWM Switching Frequency f OS SYN = khz High-Side urrent Limit I LIM LX On-Resistance R ON, LX I LX = ±1m.6 Ω LX Leakage urrent I LXLKG + = 12, LX = GND to µ LX Reverse Leakage urrent, Regulator Off I LXLKGR + = floating, LX = 5, SHDN = GND 1. 2 µ Undervoltage Lockout +, ULO + falling Startup oltage +, STRT + rising SYN Input High oltage IH, SYN 2.5 SYN Input Low oltage IL, SYN.5 SYN Input urrent I IN, SYN SYN = GND or 3 ±1 µ SHDN Input High oltage IH, SHDN 2.4 SHDN Input Low oltage IL, SHDN.8 SHDN Input urrent, Sinking I IN-, SHDN SHDN = GND or + ±1 µ SHDN Input apacitance IN, SHDN (Note 1) 1 pf L Output oltage L I L = m to 1m 3.3 Output oltage µ to 3µ 1.25 Note 1: Guaranteed by design and not production tested. 2

3 ELETRIL HRTERISTIS (+ = +7, PGND = GND =, SHDN = +, (T = -4 to +85 ), unless otherwise noted.) (Note 2) PRMETER Supply Range Quiescent Supply urrent (PWM Mode) Quiescent Supply urrent (PFM Mode) Shutdown Supply urrent Output oltage Range PWM F Feedback Threshold F Input urrent PWM Switching Frequency High-Side urrent Limit Undervoltage Lockout Startup oltage SYMOL + I +, PWM I +, PFM I +, SHDN OUT, RNGE F I F f OS I LIM+ +, ULO +, STRT I OUT = m, SYN = 3. I OUT = m, SYN = GND SHDN = GND ircuit of Figure 2 SYN = 3., PWM duty cycle = 5% F = 1.3 SYN = 3. + falling + rising ONDITIONS MIN TYP MX ± UNITS m m µ µ khz Note 2: Specifications from to -4 are guaranteed by design and not production tested. Typical Operating haracteristics (ircuit of Figure 2, T = +25, unless otherwise noted.) DROPOUT OLTGE () DROPOUT OLTGE vs. LOD URRENT 3.3 SETTING OUT = SETTING OUT = LOD URRENT (m) -1 EFFIIENY (%) EFFIIENY vs. OUTPUT URRENT 1 9 PWM MODE (SYN = L) 8 OUT = IN = 4 IN = IN = 5 4 IN = 7 IN = OUTPUT URRENT () -2 EFFIIENY (%) EFFIIENY vs. OUTPUT URRENT PWM MODE (SYN = L) OUT = 5 IN = 7 IN = 5.5 IN = 11 IN = OUTPUT URRENT () -3 3

4 Typical Operating haracteristics (continued) (ircuit of Figure 2, T = +25, unless otherwise noted.) EFFIIENY (%) EFFIIENY vs. OUTPUT URRENT IN = 4 IN = 5 IN = 7 IN = 9 IN = OUTPUT URRENT () IDLE MODE (SYN = GND) OUT = EFFIIENY (%) EFFIIENY vs. OUTPUT URRENT 1 IN = IN = IN = IN = 7 2 IDLE MODE 1 (SYN = GND) OUT = OUTPUT URRENT () -5 MXIMUM OUTPUT URRENT (m) MXIMUM OUTPUT URRENT vs. SUPPLY OLTGE 3.3 SETTING, OUT = SETTING, OUT = 4.75 GURNTEED OUTPUT URRENT OF FIGURE 2 IS 6m SUPPLY OLTGE () -6 MXIMUM OUTPUT URRENT (m) MXIMUM OUTPUT URRENT vs. SYN FREQUENY 2, 3 = 47µF L1 = 33µH IN = 5 OUT = 3.3 OUT = -5% at I OUT(MX) SYN FREQUENY (khz) -7 QUIESENT URRENT (m) QUIESENT SUPPLY URRENT vs. SUPPLY OLTGE : OUT = 3.3, PWM MODE : OUT = 3.3, PFM MODE SUPPLY OLTGE () -8 QUIESENT URRENT (m) IN = 5.3 OUT = 3.3 QUIESENT URRENT vs.temperture TEMPERTURE ( ) PWM MODE PFM MODE -9 SWITHING FREQUENY (khz) SWITHING FREQUENY vs. SUPPLY OLTGE OUT = FREQUENY (khz) SWITHING FREQUENY vs. TEMPERTURE OUT = OUTPUT NOISE (m) OUTPUT RIPPLE ND HRMONIS IN = 5 OUT = 3.3 I OUT = 5m PWM MODE TO SUPPLY OLTGE () TEMPERTURE ( ) -1 1k 1k 1M 1M FREQUENY (Hz) 4

5 Typical Operating haracteristics (continued) (ircuit of Figure 2, T = +25, unless otherwise noted.) HEY-LOD, PWM-MODE SWITHING WEFORMS -12 LIGHT-LOD, PWM-MODE SWITHING WEFORMS -13 m 1µs/div IN = 5, OUT = 3.3, LOD = 5m : LX, 5/div : OUT, 2m/div, OUPLED : INDUTOR URRENT, 5m/div 1µs/div IN = 5, OUT = 3.3, LOD = m : LX, 5/div : OUT, 2m/div, OUPLED : INDUTOR URRENT, 5m/div LIGHT-LOD, PFM-MODE SWITHING WEFORMS MEDIUM-LOD, PFM-MODE SWITHING WEFORMS µs/div IN = 5, OUT = 3.3, LOD = m : LX, 5/div : OUT, 2m/div, OUPLED : INDUTOR URRENT, 2m/div 1µs/div IN = 5, OUT = 3.3, LOD = 7m : LX, 5/div : OUT, 2m/div, OUPLED : INDUTOR URRENT, 2m/div 5

6 Typical Operating haracteristics (continued) (ircuit of Figure 2, T = +25, unless otherwise noted.) LOD-TRNSIENT RESPONSE -16 LINE-TRNSIENT RESPONSE -17 4µs/div IN = 5, OUT = 3.3, LOD = m TO 5m, PWM MODE : LX, 5/div : OUT, 5m/div, OUPLED : LOD URRENT, 5m/div 2µs/div IN = 5 TO 11, OUT = 3.3, LOD = 5m, PWM MODE : IN, 5/div : OUT, 2m/div, OUPLED REOERY FROM 1% DUTY YLE (DROP OUT) SHUTDOWN ND STRTUP RESPONSE D 2µs/div IN = 3.3 TO 11, OUT = 3.3, LOD = 5m, PWM MODE : IN, 5/div : OUT, 5m/div, OUPLED : LX, 1/div 5µs/div IN = 5, OUT = 3.3, LOD = 1m, PWM MODE : SHDN, 5/div : OUT, 2/div, OUPLED : LX, 5/div D: INDUTOR URRENT, 5m/div 6

7 Pin Description PIN NME FUNTION 1 SHDN Shutdown, ctive-low, Logic-Level Input. onnect SHDN to + for normal operation. 2 F Feedback Input. onnect F to a resistor voltage divider between the output and GND. 3 Reference ypass Output. onnect a.47µf capacitor to GND very close to the, within.2 in. (5mm). 4 L 3.3 Internal Logic Regulator Output. ypass L to GND with a 2.2µF capacitor very close to the, within.2 in. (5mm). 5 GND Ground 6 SYN Oscillator Synchronization and PWM ontrol Input. SYN is a logic-level input. Tie SYN to L for internal 3kHz PWM operation at all loads. The oscillator synchronizes to the negative edge of an external clock between 1kHz and 4kHz. The operates in PWM mode when SYN is clocked. Tying SYN to GND allows a reduced supply-current mode at light loads. 7 LX Inductor onnection to the drain of an internal P-channel MOSFET 8 + Supply-oltage Input. 3.5 min to 11 max. ypass + to GND with a.33µf and large-value electrolytic capacitor in parallel. These capacitors must be as close to the + and GND pins as possible. Place the.33µf capacitor within.2 in. (5mm) of the. SHDN L + L GND 25m PFM URRENT OMPRTOR 1Ω + GND 1m ILIM OMPRTOR LEEL SHIFTER.1X SENSE FET LX SYN RMP GEN SYN ELL PWM SLOPE OMPENSTION FROM ONTROL LOGI F PWM OMPRTOR ONTROL & DRIER LOGI SENSE FET.1X F PWM ON SIGNL F 5m NEGLIM OMPRTOR 1Ω GND PFM OMPRTOR OEROLTGE OMPRTOR m in PFM DJ. IN PWM Figure 1. Simplified Functional lock Diagram 7

8 Detailed Description The is a step-down, pulse-width modulation (PWM) D-D converter that provides an adjustable output from 1.25 to 1.5. It accepts inputs from 3.5 to 11 and delivers up to 6m. n internal MOSFET and synchronous rectifier reduce P board area while maintaining high efficiency. ycle-by-cycle current limiting protects the internal MOSFETs and reduces system stress during overload conditions. Operation with up to 1% duty cycle for an output of 3 and higher minimizes dropout voltage. Fixed-frequency PWM operation reduces interference in sensitive communications and data-acquisition applications. SYN input allows synchronization to an external clock. When enabled, Idle Mode extends battery life under light loads by placing the regulator in low quiescent current (2µ typ) pulse-frequency modulation (PFM) operation. Shutdown quiescent current is 2.5µ typ. PWM ontrol Scheme The uses an oscillator-triggered minimum/ maximum on-time current-mode control scheme. The minimum on-time is approximately 28ns unless in dropout. The maximum on-time is approximately 4/f OS, allowing operation to 1% duty cycle. urrentmode feedback provides cycle-by-cycle current limiting for superior load and line response and protection of the internal MOSFET and rectifier. t each falling edge of the internal oscillator, the SYN cell sends a PWM ON signal to the control and drive logic, turning on the internal P-channel MOSFET (main switch) (Figures 1 and 2). This allows current to ramp up through the inductor (Figure 2) to the load, and stores energy in a magnetic field. The switch remains on until either the current-limit (ILIM) comparator is tripped, the maximum on-time is reached (not shown), IN = 3.5 to 11 + LX 33µH R1 47µF.33µF 165kΩ 47µF 1 1pF ON OFF SHDN SYN F L GND R2 1kΩ 2.2µF.47µF OUT = 1.25 (R1/R2 + 1) Figure 2. Typical Operating ircuit OUT = 3.3 or the PWM comparator signals that the output is in regulation. When the switch turns off, during the second half of each cycle, the inductor s magnetic field collapses, releasing the stored energy and forcing current through the output diode to the output filter capacitor and load. The output filter capacitor stores charge when the inductor current is high and releases it when the inductor current is low, smoothing the voltage across the load. During normal operation, the regulates output voltage by switching at a constant frequency and then modulating the power transferred to the load per pulse using the PWM comparator. multi-input comparator sums three weighted differential signals (the output voltage with respect to the reference, the main switch current sense, and the slope-compensation ramp) and changes states when a threshold is reached. It modulates output power by adjusting the inductor peak current during the first half of each cycle, based on the output error voltage. The s loop gain is relatively low to enable the use of a small, low-valued output filter capacitor. The resulting load regulation is 2.5% typ at 5m. Slope compensation is added to account for the inductor current waveform s down slope during the second half of each cycle, and to eliminate the inductor current staircasing characteristic of current-mode controllers at high duty cycles. 1% Duty-ycle Operation For the internal oscillator frequency, the f OS /4 maximum on-time exceeds one cycle and permits operation to 1% duty cycle. s the input voltage drops, the duty cycle increases until the P-channel MOSFET is held on continuously and 1% duty cycle is reached. Dropout voltage in 1% duty cycle is the output current multiplied by the on-resistance of the internal switch and inductor around 3m (I OUT = 5m). In PWM mode, subharmonic oscillation can occur near dropout, but subharmonic voltage ripple is small, since the ripple current is low. When using synchronization to an external oscillator, 1% duty cycle is available for SYN frequencies higher than f OS /4. Synchronous Rectification lthough an external Schottky diode is used as the primary output rectifier, an N-channel synchronous rectifier turns on to reduce power loss across the diode and improve efficiency. During the second half of each cycle, when the inductor current ramps below the threshold set by the NEGLIM comparator or when the end of the oscillator period is reached, the synchronous rectifier turns off. This keeps excess current from flowing 8

9 backward through the inductor, from the output filter capacitor to GND, or through the switch and synchronous rectifier to GND. During PWM operation, the NEGLIM threshold adjusts to permit small amounts of reverse current to flow from the output during light loads. This allows regulation with a constant switching frequency and eliminates minimum load requirements. The NEGLIM comparator threshold is m if F < 1.25, and decreases as F exceeds 1.25 to prevent the output from rising. The NEGLIM threshold in PFM mode is m. (See Forced PWM and Idle Mode operation.) Forced PWM and Idle Mode Operation onnect SYN to L for normal forced PWM operation. Forced PWM operation is desirable in sensitive RF and data-acquisition applications, to ensure that switchingnoise harmonics do not interfere with sensitive IF and data-sampling frequencies. minimum load is not required during forced PWM operation, since the synchronous rectifier passes reverse inductor current as needed to allow constant-frequency operation with no load. onnecting SYN to GND enables Idle Mode operation. This proprietary control scheme places the in PFM mode at light loads to improve efficiency and reduce quiescent current to 2µ typ. With Idle Mode enabled, the initiates PFM operation when the output current drops below 1m. During PFM operation, the switches only as needed to service the load, reducing the switching frequency and associated losses in the internal switch and synchronous rectifier, Schottky diode, and external inductor. During PFM mode, a switching cycle is initiated when the PFM comparator senses that the output voltage has dropped too low. The P-channel MOSFET switch turns on and conducts current to the output filter capacitor and load until the inductor current reaches the PFM peak current limit (1m). Then the switch turns off and the magnetic field in the inductor collapses, forcing current through the output diode to the output filter capacitor and load. The output filter capacitor stores charge when the inductor current is high and releases charge when it is low, smoothing the voltage across the load. Then the waits until the PFM comparator senses a low output voltage again. During PFM mode, the synchronous rectifier is disabled and the external Schottky diode is used as an output rectifier. The PFM current comparator controls both entry into PWM mode and the peak switching current during PFM mode. onsequently, some jitter is normal during transition from PFM to PWM modes with loads around 1m, and has no adverse impact on regulation. Output ripple is higher during PFM operation, and the output filter capacitor should be selected on this basis when PFM mode is used. Output ripple and noise are higher during PFM operation. SYN Input and Frequency ontrol The H comes with an internal oscillator set for a fixed switching frequency of 3kHz. onnect SYN to L for normal forced-pwm operation. Do not leave SYN floating. onnecting SYN to GND enables Idle Mode operation to reduce supply current at light loads. SYN is a logic-level input useful for operating-mode selection and frequency control. It is a negative edge triggered input that allows synchronization to an external frequency between 25kHz and 44kHz. When SYN is clocked by an external signal, the converter operates in PWM mode. If SYN is low or high for more than 1µs, the oscillator defaults to 3kHz. Operating at a lower switching frequency reduces quiescent current, but reduces maximum load current as well (Table 1). For example, at 33kHz, maximum output current is 6m, while at 3kHz, maximum output current is only 3m. Note that 1% duty cycle will only occur for f SYN > f OS /4. L Regulator The uses an internal 3.3 linear regulator for logic power in the I. This logic supply is brought out using the L pin for bypassing and compensation with an external 2.2µF capacitor to GND. onnect this capacitor close to the, within.2in (5mm). Shutdown onnecting SHDN to GND places the in a lowcurrent shutdown mode (I Q = 2.5µ typ at + = 7). In shutdown, the reference, L regulator, control circuitry, internal switching MOSFET, and the synchronous rectifier turn off and the output falls to. onnect SHDN to + for normal operation. urrent-sense omparators Several internal current-sense comparators are used inside the. In PWM operation, the PWM comparator is used for current-mode control. urrent-mode control imparts cycle-by-cycle current limiting and provides improved load and line response, allowing tighter specification of the inductor saturation current limit to reduce inductor cost. second 1m current-sense comparator is used across the P-channel switch to control entry into PFM mode. third current-sense comparator monitors current through the internal N-channel MOSFET to set the NEGLIM threshold and determine 9

10 when to turn off this synchronous rectifier. fourth comparator (ILIM) is used at the P-channel MOSFET switch for overcurrent detection. This protects the system, external components, and internal MOSFETs under overload conditions. Design Information Output oltage Selection To select an output voltage between 1.25 and 1.5, connect F to a resistor voltage divider between the output and GND (Figure 2). Select feedback resistor R2 in the 5kΩ to 1kΩ range, since F input leakage is ±1n max. R1 is then given by: R1 R2 OUT = 1 F where F = small ceramic capacitor (1) around 1pF to 47pF should be added in parallel with R1 to compensate for stray capacitance at the F pin, and output capacitor equivalent series resistance (ESR). Inductor Selection 1.3 inductor with the value recommended in Table 1 is sufficient for most applications. However, the exact inductor value is not critical, and values within 5% of those in Table 1 are acceptable. For best efficiency, the inductor s D resistance should be less than.25ω. The inductor saturation current rating must exceed the 1 I LIM current limit. Table 2 lists component suppliers. Table 1. Inductor and Output Filter vs. Sync Frequency SYN RNGE (khz) L1 (µh) OUT (µf) apacitor Selection Input and output filter capacitors should be chosen to service inductor currents with acceptable voltage ripple. The input filter capacitor also reduces peak currents and noise at the voltage source. See Table 1 for suggested values. The s loop gain is relatively low, to enable the use of small, low-valued output filter capacitors. Higher values provide improved output ripple and transient response. Lower oscillator frequencies require a larger-value output capacitor. When Idle Mode is used, verify capacitor selection with light loads during PFM operation, since output ripple is higher under these conditions. Low-ESR capacitors are recommended. apacitor ESR is a major contributor to output ripple (usually more than 6%). Ordinary aluminum-electrolytic capacitors have high ESR and should be avoided. Low-ESR aluminum-electrolytic capacitors are acceptable and relatively inexpensive. Low-ESR tantalum capacitors are better and provide a compact solution for spaceconstrained surface-mount designs. Do not exceed the ripple current ratings of tantalum capacitors. eramic capacitors have the lowest ESR overall, and OS-ON capacitors have the lowest ESR of the highvalue electrolytic types. It is generally not necessary to use ceramic and OS-ON capacitors for the ; they need only be considered in very compact, highreliability, or wide-temperature applications, where the expense is justified. When using very-low-esr capacitors, such as ceramic or OS-ON, check for stability while examining load-transient response, and increase the compensation capacitor 1 if needed. Table 2 lists suppliers for the various components used with the. Table 2. omponent Suppliers OMPNY PHONE FX X US (83) (83) (8) oilcraft US (847) (847) oiltronics US (561) (561) Dale US (65) (65) International US (31) (31) Rectifier Motorola US (62) (62) Nichicon US (847) (847) Japan Nihon US (85) (85) Japan Sanyo US (619) (619) Japan Siliconix US (48) (48) (8) Sprague US (63) (63) Sumida US (847) (847) Japan United US (714) (714) hemi-on 1

11 ypass + to GND using a.33µf capacitor. lso bypass L to GND with a 2.2µF capacitor, and to GND using a.47µf capacitor. These capacitors should be placed within.2in (5mm) of their respective pins. small ceramic capacitor (1) of around 1pF to 47pF should be added in parallel with R1 to compensate for stray capacitance at the F pin and output capacitor ESR. Output Diode Selection 1 external diode (D1) is required as an output rectifier to pass inductor current during the second half of each cycle. This diode operates in PFM mode and during transition periods while the synchronous rectifier is off. Use a Schottky diode to prevent the slow internal diode of the N-channel MOSFET from turning on. hip Information TRNSISTOR OUNT: 26 SUSTRTE ONNETED TO GND P oard Layout and Routing High switching frequencies and large peak currents make P board layout a very important part of design. Poor design can result in excessive EMI on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. Power components, such as the, inductor, input filter capacitor, and output filter capacitor should be placed as close together as possible, and their traces kept short, direct, and wide. onnect their ground pins at a common node in a star-ground configuration. Keep the extra copper on the board and integrate into ground as a pseudo-ground plane. The external voltage-feedback network should be very close to the F pin, within.2in (5mm). Keep noisy traces, such as from the LX pin, away from the voltagefeedback network, and separate using grounded copper. Place the small bypass capacitors (1, 3, 5, and 6) within.2in (5mm) of their respective pins. The evaluation kit manual illustrates an example P board layout, routing, and pseudo-ground plane. 11

12 Package Information e D 1.11mm.4in. L -8 DIM 1 E e H L MIN INHES.5 MX MILLIMETERS MIN MX E H Narrow SO SMLL-OUTLINE PKGE (.15 in.) DIM D D D PINS INHES MIN MX MILLIMETERS MIN MX

PART MAX1684EEE MAX1685EEE. Maxim Integrated Products 1

PART MAX1684EEE MAX1685EEE. Maxim Integrated Products 1 19-1454; Rev 2; 7/1 ELUTION KIT ILBLE Low-Noise, 14 Input, 1, PWM General Description The / are high-efficiency, internalswitch, pulse-width modulation (PWM) step-down switching regulators intended to