What is it? Why SLHC? What s the challenge? Can we do it? How will the tracker look like?

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Eunice Grant
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1 Silicon Trackers for the Super-LHC System design and overview Marc Weber, Rutherford Appleton Laboratory What is it? Why SLHC? What s the challenge? Can we do it? How will the tracker look like? 10 th Topical seminar on innovative particle and radiation detectors, Siena,

2 7 TeV protons vs. 7 TeV protons; 27 km circumference 7 x the energy and 100 x the luminosity of the Tevatron ATLAS detector 2

3 ATLAS detector Huge multi-purpose detector; 46 m long; diameter 22 m; weight 7000 t Tracking system much smaller; 7 m long; diameter 2.3 m; 2 T field 3

4 The ATLAS cavern (in 2005) Huge multi-purpose detector; 46 m long; diameter 22 m; weight 7000 t Toroid magnets and muon detectors dominate size Note that the lower part of the detector is not visible in the picture 4

5 2 m ATLAS silicon tracker 5.6 m 1 m 1.6 m 40 MHz event rate; > 50 kw power 17 thousand silicon sensors (60 m 2 ) 6 M silicon strips (80 µm x 12.8 cm) 80 M pixels (50 µm x 400 µm) 5

6 Why tracking at LHC is tough? Too many particles in too short a time particles / bunch collision - too short: collisions every 25 ns Too short need fast detectors and electronics; power! Too many particles - need high resolution detectors with millions of channels - detectors suffer from radiation damage (1 to 50 MRad) tracking at SLHC is tougher! 6

7 SLHC: LHC luminosity upgrade in 2015 H ZZ µµee + minimum bias events (M H = 300 GeV) LHC in 2008?? : cm -2 s -1 LHC first years: 1033 cm -2 s -1 LHC: cm -2 s -1 SLHC: cm -2 s -1 Need new tracker! 7

8 Why SLHC and detector upgrade? After all, LHC will should have made major discoveries in 2015 already must fully exploit discovery potential of LHC - time to decrease stat. errors becomes too long; upgrade is more efficient - LHC tracker dies after 8 years (did not know then how to do it better) need to replace tracker What else? Only SLHC keeps us at energy frontier Tevatron experience shows that hadron colliders can be competitive for 20 years It s best value for money 8

9 SLHC Physics Motivation Extend LHC discovery mass reach by 30% - increased reach for squark and gluino by 500 GeV to 3 TeV - increased reach for add. heavy gauge bosons from 5.3 to 6.5 TeV - extended sensitivity (100 GeV) to heavy MSSM Higgses (important for distinction of MSSM and SM) - increased quark compositeness limit (indirect) from 40 to 60 TeV Increased precision in SM and Higgs physics - triple gauge boson and Higgs couplings improved by 2 Increased sensitivity to rare processes/decays - FNC top decays: e.g. limit for t->qz increased from 1.1 to 0.1 x some sensitivity to Higgs self-coupling in gg->hh channel (hopeless at LHC!) - some sensitivity to strongly coupled vector boson systems, if no Higgs (hopeless at LHC!) 9

10 SLHC tracker will be one of most complex detectors ever built ten-fold increase in luminosity tenfold radiation levels ( >100 MRad, 3x10 16 n/cm 2 ) tenfold track density/collision (if 25 ns bc distance) Radiation hardness affects readout chips, sensors, sensor temperature, cooling system; possibly support materials Track densityaffects number of channels, power, cooling, packaging, etc. Many individual R&D challenges, but also complex, multidimensional system optimization puzzle 10

11 Watch material, when solving the puzzle!! naively extrapolating from an SCT to an SLHC layer assuming 5 times more channels, we get (one layer, barrel, normal impact): Component R.L. for SCT Scaling factor* R.L. for SLHC *crude estimate; no innovation Cable 0.2 % x 5 1 % Hybrid 0.3 % x % Sensor 0.6 % x % Cooling; CF cylinders; module baseboard; etc. 0.4; 0.3; 0.2 % x 3; x 1; x % Total 2 % 5 % too big innovate! Silicon fraction 30 % 12 % Material budget will explode at SLHC without innovations in powering, packaging, and cooling 11

12 Challenge: radiation-hard sensors 1. Radiation induced leakage current independent of impurities; every 7 C of temperature reduction halves current cool sensors to -25 C (SCT = -7 C) 2. type inversion from n to p-bulk increased depletion voltage oxygenated silicon helps (for protons); n+-in-n-bulk or n+-in-p-bulk helps 3. Charge trapping the most dangerous effect at high fluences collect electrons rather than holes reduce drift distances 12

depletion voltage Difficulty was non-standard via process; meanwhile much progress

13 Strong candidate for inner layer: 3D pixels 3D pixel proposed by Sherwood Parker in 1985 vertical electrodes; lateral drift; shorter drift times; much smaller depletion voltage Difficulty was non-standard via process; meanwhile much progress in hole etching; many groups; simplified designs see talk of Sabina R. (ITC-irst) 3D planar 13

14 Signal loss vs. fluence see C. da Via s talk at STD6 Hiroshima conference 100 Fluence [p/cm 2 ] Signal efficiency [%] D silicon C. DaVia et a. March 06 Diamond W. Adam et al. NIMA 565 (2006) n-on-p strips P. Allport et al. IEEE TNS 52 (2005) 1903 n-on-n pixels CMS T. Rohe et al. NIMA 552(2005) Fluence [n/cm 2 ] C. Da Via'/ Aug.06 3D pixels perform by far the best 14

15 Challenge: radiation-hard electronics Incredible progress in understanding of LHC electronics not quite good enough for SLHC radiation levels Successful commercial 0.25µm CMOS processes will disappear Main candidate 0.13µm CMOS technology (e.g. CMOS8FR from IBM) Need much more R&D but 0.13µm CMOS looks almost unaffected by radiation doses of 100 MRad Interesting alternative are bipolar SiGe processes as used in wireless communication; large current gains (β several 100s, f T 100s of GHz) Main incentive for SiG bicmos processes: power savings and noise performance at large input capacitances (similar for ABCD chip) 15

16 ATLAS HRFE: bicmos Front-End µ µ µ µ µ µ µ µ µ µ Power Comparison 7 pf strips 15 pf strips SiGe IHP-SG25H1 70 µa 180 µa CMOS IBM 0.25 mm * 450 µa 630 µa * CMOS values from Kaplon et al. 1-Oct SiGe for Readout Front-Ends ATLAS Upgrade Workshop A.A. Grillo SCIPP-UCSC

17 need more channels otherwise, don t find the tracks! Track density What does this imply?? more channels more chips hybrids more material more chips also means more power more cables denser/shorter modules packaging challenge Let s look into power, packaging and integrated structures below 17

18 Independent powering The way we always did it! The powering scheme of the upgraded ATLAS tracker PS PS PS PS PS PS PS PS PS PS Power in PS Power out 18

19 Power budget and distribution is key challenge affects cooling, material budget, packaging and more but work on powering schemes and the like is not sexy Example ATLAS Semiconductor Tracker SCT: cables too long (up to 160 m), cable resistance to high ( 3.5 Ω), 6 M channels 50 kw power (modules and cables) Best estimate for SLHC tracker: M channels; 50 kw module power; 20% power efficiency 200 kw total power This is a power station not a tracker! 19

20 Why independent powering fails at SLHC? 1. Don t get 5 or 10 times more cables in 2. Power efficiency is too low (50% SCT 20% SLHC) 3. Material budget: 0.2% of R.L. per layer (barrel normal incidence) 1% or 2% SLHC 4. Packaging constraints Each reason by itself is probably sufficient for a No-No 20

21 Alternatives to IP IP M1 M2 M3 Analog and digital voltage Serial powering and parallel power bus with DC-DC conversion SP PP with DC-DC conversion M1 M2 M3 M1 M2 M3 Constant current for both analog and digital power Note: Parallel powering without DC-DC conversion is problematic due to low power efficiency and large IR drops 21

22 Advantages of alternatives Reduce number of cables by factor 2x2n/2=2n (even more if counting sense wires) Combining analog and digital cables IP M1 M2 M3 Analog and digital voltage M1 M2 M3 M1 M2 M3 SP PP with DC-DC conversion Huge increase of power efficiency over IP as Vdd goes down (see page 23) huge material reduction cost savings (cables and PS) Similar benefits for Serial powering and DC-DC conversion PP 22

23 Power efficiency Consider n modules with module current and voltages I and V, off-detector cable resistance R, DC-DC gain g, define x= IR/V power consumed by n modules is always: n I V power wasted in the cable depends on powering scheme I sm V drop V sm P cab Efficiency: P sm /P total IP n I I R V n I 2 R 1/[1 + x] PP n I n I R V n 2 I 2 R 1/[1 + nx] SP I I R nv I 2 R 1/[1 + x/n] DC- DC (n/g) I (n/g) I R gv (n/g) 2 I 2 R 1/[1 + xn/g 2 ] Low V is bad, large R and I are bad message to IC designers: don t go there! Problem also relevant for industry (1+x)/(1+x/n) Power efficiency ratio (SP/IP) vs # of modules # of modules (n) SLHC Vdd=1V x 4.5 ~1+x SCT Vdd=4V x= module in series increases efficiency by factor 4 23

24 Serial powering of six ATLAS SCT modules SP interface board RAL clean room. This was also used for QA of ~800 SCT modules 24

25 Noise performance of 6 SCT modules For more details see my talk at the Hiroshima conference STD6 <ENC> <ENC> Vs module number for IP and SP with 6 modules Module # IP SP Conclusion is valid for all channels Gain does not change either Created noise sources by various means: current injection at different frequencies; HV off for 1 module; increased threshold for 1 module SP circuitry copes nicely with it Precise measurements; noise performance of SP is excellent 25

26 Digital PS 1 Risk comparison: IP vs SP Analog PS 1 Distribution Board Module 1 Module 2 Module n Independent Powering Wire bonds Cables Type 1 Cables Type 2 Digital PS 2 Analog PS 2 IP Connections (analog + digital) Probability of a failure 4n + 4n 4n + 4n 4n + 4n a IP b IP c IP Lost modules Digital PS n Analog PS n Power supply Distribution Board Module 1 Module 2 Module n SP: one broken connection loses n modules SP Serial Powering connections (analog + digital) Probability of a failure Lost modules Wire bonds 2 (n+1) Cables Type a SP b SP c SP n n n Cables Type 2 however, much less cables and less connections 26

27 What is risk?? Risk = (# of power connections) x (probability of a failure) x (# of modules lost per failure) Risk ratio (SP/IP) Risk ratio (SP/IP) a ( n + 1) # of modules Case 1 Case 2 Case 3 Case 4 SP 4 SP ( a + b + c ) IP + 2 b IP + IP 2 c SP Make your own choices for values of a,b, and c Mine are here Risk due to breaking connections seems larger for SP, but less than one might think Risk increases ~ number of modules/4 Build in increased redundancy 27

Challenge: packaging Packaging is what makes

MCMs; chips; CF support; cables and cooling

28 Challenge: packaging Packaging is what makes your cell phone small How to stack sensors; MCMs; chips; CF support; cables and cooling while connecting them electrically, thermally and mechanically? innovative example: ATLAS pixels - sophisticated, crowded flex-hybrid - carbon-carbon support structures - bump-bonding of chips to sensors - direct cooling of chips 28

3D technology for SLHC 3D technology is major trend in industry; would open many possibilities never done in HEP; can we afford it; yield; do we need it; is there enough time to make this work?

29 3D technology for SLHC 3D technology is major trend in industry; would open many possibilities never done in HEP; can we afford it; yield; do we need it; is there enough time to make this work? Need to develop: - conducting vias through ASICs and/or MCM-D Artist s view - MCM-Ds high power capability, multilayer, rad-hard - stacking it all together using bump-bonding of chips to sensors or MCM-Ds (cost, bare die, not wafer level) 29

Services and support structures determine detector properties SCT has the ideal mechanical structure precision carbon fiber support cylinders (15µm radial precision, creep<20µm/m) overlapping

30 Services and support structures determine detector properties SCT has the ideal mechanical structure precision carbon fiber support cylinders (15µm radial precision, creep<20µm/m) overlapping precision modules (<5 µm internal precision) greatly simplified calibration and alignment, but preparation of barrels, robotic module mounting, and 4-barrel assembly took 3 years The robot in action Barrel 6 at CERN 30

31 Challenge:supermodules CDF Run IIb stave Concept could save years of production and assembly time ATLAS pixel bi-stave The robot in action CMS TOB Rod 31

32 from Raffaello D Alessandro, University and INFN Firenze, Vertex 2006 TOB Example CMS Outer Tracker 5550 modules 1 Wheel 688 Rods (24 different species) 1.1m

different Excellent mechanical and thermal

33 Detailed FEA has started see W. Miller s talk as STD6 Hiroshima conference Disclaimer: these are early layouts to gain understanding; final detector could be entirely different Excellent mechanical and thermal properties 11 µm peak to peak distortion when changing temperature by 50 C C Chip/ Silicon C 33

arrangement LBNL SP supermodule with 6 hybrids (no sensors) same supermodule with 5 hybrids and 1 module supermodule

34 Implement SP on densely packed supermodule For more details see Carl Haber s talk at the Hiroshima conference STD6 Testbed for electrical system design; allows search for noise sources and study G+S issues in challenging packaging arrangement LBNL SP supermodule with 6 hybrids (no sensors) same supermodule with 5 hybrids and 1 module supermodule is electrically functional and noise performance is promising needs many more months of work before definitive conclusions 34

35 Conclusions Tracking at LHC is tough; but tracking for SLHC is much tougher Don t know yet if we can do it. Will know in 2-3 years Key challenges are not sexy : power distribution; packaging; integrated structures; etc. It is prudent to invest in R&D effort now, if we want to exploit the LHC high-energy frontier fully Well, you could also prefer to wait for another 20 years to do it without SLHC 35

36 Appendix 36

Extreme radiation levels! Plots show radiation dose and fluence per high luminosity LHC year for ATLAS (assuming 10 7 s of collisions; source: ATL-Gen-2005-001) Fluence [1 MeV eq.

37 Extreme radiation levels! Plots show radiation dose and fluence per high luminosity LHC year for ATLAS (assuming 10 7 s of collisions; source: ATL-Gen ) Fluence [1 MeV eq. neutrons/cm 2 ] Radiation dose [Gray/year] Uniform thermal neutron gas Put your cell phone into ATLAS! It stops working after 1 s to 1 min. Neutrons are everywhere and cannot easily be suppressed 37

38 Extreme radiation levels! Radiation levels vary from 1 to 50 MRad in tracker volume - less radiation at larger radii; more close to beam pipe - more radiation in forward regions Fluences vary from to to particles/cm 2 Vicious circle: need silicon sensors for resolution and radiation hardness cooling (sensors and electronics) more material even more secondary particles etc. Don t win a beauty contest in this environment, but detectors are still very good! 38

39 How does it look in real life? SCT Detector 4 barrel layers at 30, 37, 45, 52 cm radius and 9 discs (each end) 60 m 2 of silicon; 6 M strips; typical power consumption 50 kw Precision carbon fiber support cylinder carries modules, cables, optical fiber, and cooling tubes Evaporative cooling system based on C 3 F 8 (same for pixel detector) Barrel 6 at CERN 39

40 Technological challenges: Pixel detector Pioneering project: first pixel detector in hadron colliders Sensors: n+ on n-bulk, oxygenated silicon; max. voltage 700 V; multi-guard ring structure; operates up to MeV neq/cm 2 ; total input capacitance: <400 ff; signal after irradiation: > 10Ke - Readout chip: complex; fast; low-noise (<400 e - ); radiation-hard to 50 MRad; sensitive to small signals (6K e - ); 3.5 M transistors in 80 mm 2 ; 0.25 m CMOS process; 2880 pixels/chip; various attractive novel features 40

41 If it all works, what will it do for us? Tracker performance η <2.5 η 0 P T (GeV) Transverse momentum resolution (d 0 ) based on latest simulation (Geant 4) and reconstruction software; curves are not a fit but an earlier simulation Asymptotic resolution is close to 10 µm at lower momenta, resolution depends on η and increases with η 41

42 Q: How will the detector look like? A: Overall layout is wide open Detector must fit into current tracker and service volume Tracker will almost certainly be silicon pixels and strips I see interesting alternatives, but our time window is limited Detailed simulation will provide clarity about: - number and position of layers - size of pixels - pitch/length/stereo angle of strips In my view, these things need not to be well-understood before a year from now 42

43 First look at real estate penalty for strip SP Small 2+2 layer Serial powering PCB; 38 x 9 mm 2 (this is a PCB for cost reasons only) Hybrid SSPPCB ABCD3TV2 Further shrinkage if SP integrated into hybrid and if most circuit elements integrated into readout ICs Estimated extra hybrid floor area due to SP: ~10% 43

Layout and prototyping of the new ATLAS Inner Tracker for the High Luminosity LHC

Layout and prototyping of the new ATLAS Inner Tracker for the High Luminosity LHC Ankush Mitra, University of Warwick, UK on behalf of the ATLAS ITk Collaboration PSD11 : The 11th International Conference