SP mA Charge Pump Inverter or Doubler

Transcription

1 SP0 200mA Charge Pump Inverter or Doubler Inverts or Doubles Input Supply Voltage 9% Power Efficiency at.v 0kHz/0kHz Selectable Oscillator External Oscillator up to 700KHz Ω Output Resistance at.v Low Voltage Battery Operation Ideal for.v Lithium Ion Battery High Output Current 200mA Pin-Compatible High-Current Upgrade of the ICL70 and 0 Industry Standard Smallest Package Available for the 0 Industry Standard pin µsoic Now Available in Lead Free Packaging DESCRIPTION The SP0 is a CMOS DC-DC Monolithic Voltage Converter that can be implemented as a Voltage Inverter or a Positive Voltage Doubler. As a Voltage Inverter, a -.V to -.2V output can be converted from a +.V to +.2V input. As a Voltage Doubler, the SP0 can provide a +.0V output at 00mA from a +.2V input. The SP0 is ideal for both battery-powered and board level voltage conversion applications with a typical operating current of 00µA and a high efficiency (>90%) over most of its load-current range. Typical end products for this device are operational amplifier and interface power supplies, medical instruments, and handheld and laptop computers. The SP0 is available in -pin DIP, SOIC, and µsoic packages. TYPICAL CIRCUIT: VOLTAGE INVERTER + +.V to +.2V TYPICAL CIRCUIT: VOLTAGE DOUBLER +V + +.V to +.2V C µf to 0µF SP0 LV NEGATIVE VOLTAGE PUT C µf to 0µF SP0 +V LV DOUBLE VOLTAGE PUT C2 µf to 0µF C2 µf to 0µF

2 ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Power Supply Voltage (V+ to or to )...+.V LV Input Voltages...( - 0.V) to (V+ + 0.V) and Input Voltages...The least negative of ( - 0.V) or (V+ -.V) to (V+ + 0.V) and V+ Continuous Output Current...20mA Output Short-Circuit Duration to...s Operating Temperature Ranges SP0C_...0 C to +70 C SP0E_...-0 C to + C Continuous Power Dissipation (T AMB = 70 C) PDIP (derate 9.09mW/ C above +70 C)...727mW NSOIC (derate.mw/ C above +70 C)...7mW µsoic (derate.0mw/ C above +70 C)...0mW Operating Temperature...-0 C to + C Storage Temperature...- C to +0 C Lead Temperature (soldering 0s) C SPECIFICATIONS P ARAMETER M IN. T YP. MAX. I nverter Circuit at Low Frequency with 0µ F Capacitors UNITS CONDITIONS V+ =.V, C = C2 = 0µF, = open, T AMB = T to T MIN MAX ; refer to Figure test circuit. Note 2 Supply Voltage V R L = 00Ω, Note Supply Current ma No Load Output Current 200 ma Oscillator Input Current ± µ A Oscillator Frequency 0 20 khz Output Resistance. 2 0 Ω = 00mA, Note Voltage Conversion Efficiency % No Load Power Efficiency % R L = 00Ω = 00mA = 200mA D oubler Circuit at Low Frequency with 0µ F Capacitors V+ =.V, C = C2 = 0µF, = open, T AMB = T to T MIN MAX ; refer to Figure 2 test circuit. Note 2 Supply Voltage V R L = kω, Note Supply Current ma No Load Output Current 200 ma Oscillator Input Current ± µ A Oscillator Frequency 0 20 khz Output Resistance. 2 0 Ω = 00mA, Note Voltage Conversion Efficiency % No Load Power Efficiency % R L = KΩ = 00mA = 200mA 2

3 SPECIFICATIONS (continued) P ARAMETER M IN. T YP. MAX. I nverter Circuit at High Frequency with 22µ F Capacitors UNITS CONDITIONS V+ =.V, C = C2 = 22µF, = V+, T AMB = T to T MIN MAX ; refer to Figure test circuit. Note 2 Supply Voltage V R L = 00Ω, Note Supply Current 0.. ma No Load Output Current 200 ma Oscillator Input Current ± µ A Oscillator Frequency khz Output Resistance. 0 0 Ω = 00mA, Note Voltage Conversion Efficiency % No Load Power Efficiency % R L = 00Ω = 00mA = 200mA D oubler Circuit at HIgh Frequency with 22µ F Capacitors V+ =.V, C = C2 = 22µF, = V+, T AMB = T to T MIN MAX ; refer to Figure 2 test circuit. Note 2 Supply Voltage V R L = kω, Note Supply Current 0.. ma No Load Output Current 200 ma Oscillator Input Current ± µ A Oscillator Frequency khz Output Resistance. 0 0 Ω = 00mA, Note Voltage Conversion Efficiency % No Load Power Efficiency % R L = KΩ = 00mA = 200mA NOTE : Specified output resistance is a combination of internal switch resistance and capacitor ESR. NOTE 2: In the test circuit capacitors C and C2 are 0µF, 0.2 maximum ESR, tantalum or 22µF, 0.2 maximum ESR, tantalum. Capacitors with higher ESR may reduce output voltage and efficiency. Refer to Capacitor Selection section. NOTE : Specified output resistance is a combination of internal switch resistance and capacitor ESR. Refer to Capacitor Selection section. NOTE : Typical value indicates start-up voltage.

4 PIN V+ 2 SP0 7 LV PIN ASSIGNMENTS Pin Frequency Control for the internal oscillator. = open,f OS C = 0KHz typical; = V+, f = 0KHz typical Pin 2 Connect to the positive terminal of the charge pump capacitor. Pin (Voltage Inverter Circuit) Ground. Pin (Positive Voltage Doubler Circuit) Positive supply voltage input. Pin Connect to the negative terminal of the charge pump capacitor. Pin (Voltage Inverter Circuit) Negative voltage output pin. Pin (Positive Voltage Doubler Circuit) Ground pin for power supply. Pin LV Low-voltage operation input pin in 0 circuits. In SP0 circuits can be connected to, or left open as desired with no effect. Pin 7 Control pin for the oscillator. Internally connected to pf capacitor. An external capacitor can be added to slow the oscillator. Be careful to minimize stray capitance. An external oscillator can be connected to overdrive the pin. Pin V+ (Voltage Inverter Circuit) Positive voltage input pin for the power supply. Pin V+ (Positive Voltage Doubler Circuit) Positive voltage output.

5 DESCRIPTION The SP0 Charge Pump DC-DC Voltage Converter either inverts or doubles the input voltage. As a negative voltage inverter, as shown in Figure, a +.V to +.2V input can be converted to a -.V to -.2V output. Figure 2, as a positive voltage doubler, a +2.V to +.2V input can be converted to a +.0V to +.V output. Typical performance curves in Figures to 20 are generated using the test circuits found in Figure and Figure 2. Four operating modes are shown in the curves: Voltage inverter in low and high frequency modes and voltage doubler in low and high frequency modes. TEST CIRCUIT: VOLTAGE INVERTER V+ I S + SP0 C LV V C2 R L Figure. SP0 Test Circuit for the Voltage Inverter + I S TEST CIRCUIT: VOLTAGE DOUBLER +V V SP0 C2 R L C LV Figure 2. Test Circuit for the Positive Voltage Doubler

6 TYPICAL PERFORMANCE CHARACTERISTICS = +.V, T AMB = 2 o C unless otherwise noted. LF = Low Frequency, = Open, C = C2 = 0µF. HF = High Frequency, = V+, C = C2 = 22µF. Inverter Circuit use Figure. Doubler Circuit use Figure 2. A: Doubler Supply Current (ma) HF LF Supply Voltage (V) B: Inverter Supply Current (ma) HF LF Supply Voltage (V) Figure A and B Supply Current vs. Supply Voltage Supply Current (ma) 2 Inverter Doubler Oscillator Frequency (khz) Figure. Supply Current vs. Oscillator Frequency

7 TYPICAL PERFORMANCE CHARACTERISTICS = +.V, T AMB = 2 o C unless otherwise noted. LF = Low Frequency, = Open, C = C2 = 0µF. HF = High Frequency, = V+, C = C2 = 22µF. Inverter Circuit use Figure. Doubler Circuit use Figure 2. Voltage Drop (V) Figure. Output Voltage Drop vs. Load Current Inverter LF g V+ =.V V+ = 2.V V+ =.V Load Current (ma) Power Efficiency (%) Figure. Power Efficiency vs. Load Current Inverter LF V+ =.V V+ = 2.V V+ =.V Load Current (ma) Output Voltage (V) Figure 7. Output Voltage vs. Oscillator Frequency Inverter IL = 0mA Inverter IL = 00mA Inverter IL = 200mA Doubler IL = 0mA Doubler IL = 00mA Doubler IL = 200mA Oscillator Frequency (khz) 7

8 TYPICAL PERFORMANCE CHARACTERISTICS = +.V, T AMB = 2 o C unless otherwise noted. LF = Low Frequency, = Open, C = C2 = 0µF. HF = High Frequency, = V+, C = C2 = 22µF. Inverter Circuit use Figure. Doubler Circuit use Figure Oscillator Frequency (khz) Power Efficiency (%) Figure. Power Efficiency vs. Oscillator Frequency Figure 9. Oscillator Frequency vs. Supply Voltage HF Inverter IL = 0mA Inverter IL = 00mA Inverter IL = 200mA Doubler IL = 0mA Doubler IL = 00mA Oscillator Frequency (khz) Supply Voltage (V) Oscillator Frequency (khz) Supply Voltage (V) Figure 0. Oscillator Frequency vs. Supply Voltage LF

9 TYPICAL PERFORMANCE CHARACTERISTICS = +.V, T AMB = 2 o C unless otherwise noted. LF = Low Frequency, = Open, C = C2 = 0µF. HF = High Frequency, = V+, C = C2 = 22µF. Inverter Circuit use Figure. Doubler Circuit use Figure 2. Oscillator Frequency (KHz) Capacitance (pf) LF HF Figure. Oscillator Frequency vs. External Capacitance Oscillator Frequency (KHz) Temperature (C) Figure 2. Oscillator Frequency vs. Temperature where =V+ Oscillator Frequency (KHz) Temperature (C) Figure. Oscillator Frequency vs. Temperature where =open 9

10 TYPICAL PERFORMANCE CHARACTERISTICS = +.V, T AMB = 2 o C unless otherwise noted. LF = Low Frequency, = Open, C = C2 = 0µF. HF = High Frequency, = V+, C = C2 = 22µF. Inverter Circuit use Figure. Doubler Circuit use Figure 2..0 Output Source Resistance (Ohms) LF HF Supply Voltage (V) Figure. Output Source Resistance vs. Supply Voltage 7 Output Resistance (ohms) Temperature (C) Figure. Output Source Resistance vs. Temperature Inverter LF 7 Output Resistance (ohms) Temperature (C) Figure. Output Source Resistance vs. Temperature where Inverter HF 0

11 TYPICAL PERFORMANCE CHARACTERISTICS = +.V, T AMB = 2 o C unless otherwise noted. LF = Low Frequency, = Open, C = C2 = 0µF. HF = High Frequency, = V+, C = C2 = 22µF. Inverter Circuit use Figure. Doubler Circuit use Figure 2. =.V V =.V = 00mA =.V V = -.0V = 00mA Figure 7. Output Noise and Ripple - Doubler LF Figure. Output Noise and Ripple - Inverter LF =.V V =.V = 00mA =.V V = -.0V = 00mA Figure 9. Output Noise and Ripple - Doubler HF Figure 20. Output Noise and Ripple - Inverter HF

12 THEORY OF OPERATION Negative Voltage Inverter This is the most common application of the SP0 where a +.V to +.2V input is converted to a -.V to -.2V output. In the inverting mode, the SP0 is typically operated with LV connected to. Since the LV may be left open, the substitution of the SP0 for the ICL70 industry standard is simplified. The circuit for the voltage inverter mode can be found in Figure 2. This operating circuit uses only two external capacitors, C and C2, for the internal charge pump. This allows designers to avoid any EMI concerns with the costly, space-consuming inductors typically used with switching regulators. The SP0 is insensitive to load current changes. Output Source Resistance vs. Supply Voltage and Temperature curves are shown in Figures to. A typical output source resistance of.2ω allows an output voltage of -.2V under light load with an input of +.2V. This output voltage decreases to only -.0V with a load current draw of 00mA. The peak-to-peak output ripple voltage is calculated as follows: V RIPPLE = I 2(f PUMP )(C2) + I (ESRC2) TYPICAL CIRCUIT: VOLTAGE INVERTER +V + +.V to +.2V SP0 C µf to 0µF LV NEGATIVE VOLTAGE PUT C2 µf to 0µF Figure 2. Typical Operating Circuit for the Voltage Inverter 2

13 For a nominal f PUMP of khz (where f =0kHz) and C2=0µF with an ESR of 0.2Ω, the ripple is approximately 90mV with a 00mA load current. If C2 is raised to 90µF, the ripple drops to mv. The output ripple voltage is calculated by noting that capacitor C2 supplies the output current during one-half of the charge pump cycle. is internally connected to a pf capacitor. An external capacitor can be added to slow the oscillator. Designers should take care to minimize stray capacitance. An external oscillator may also be connected to overdrive. Refer to the Oscillator Control section for further details. Positive Voltage Doubler The SP0 can double the output voltage of an input power supply or battery. From a +.2V input, the circuit in Figure 22 can provide 00mA with +.0V at V+. The no-load voltage output at V+ is 2(L ). LV may be tied to pin for all input voltages in the positive voltage doubler mode. Connect the power-supply positive voltage input to pin. Connect the power-supply ground input to pin. V+ is the positive voltage output in this mode. Designers may overdrive in the positive voltage doubler mode. Refer to the Oscillator Control section for further details. + +.V to +.2V TYPICAL CIRCUIT: VOLTAGE DOUBLER +V DOUBLE VOLTAGE PUT C µf to 0µF SP0 LV C2 µf to 0µF Figure 22. Typical Operating Circuit for the Positive Voltage Doubler

14 open V+ open open Oscillator Frequenc requency 0kHz typical 0kHz typical Optimizing Loss Conditions Losses in SP0 applications can be anticipated from the following:. Output Resistance: open or V+ open external capacitor external clock refer to Figure external clock frequency Figure 2. Four control modes for the SP0 Oscillator Frequency V LOSSΩ = OAD x R where V LOSSΩ is the voltage drop due to the SP0 output resistance, OAD is the load current, and R is the SP0 output resistance. 2. Charge Pump Capacitor ESR: Oscillator Control Refer to Figure 2 for a table of the four control modes of the SP0 internal oscillator frequencies. In the first mode, and are open (unconnected) and the internal oscillator typically runs at 0kHz. is internally connected to a pf capacitor. In the second mode, is connected to V+. The charge and discharge current at changes from.0µa to.0µa, increasing the oscillator frequency eight times to 0kHz. In the third mode, the oscillator frequency is lowered by connecting a capacitor between and. can still multiply the frequency by eight times in this mode, but for a lower range of frequencies. Refer to Figure for these ranges. In the fourth mode, any standard CMOS logic output can be used to drive. may be overdriven by an external oscillator that swings between and. When is overdriven, has no effect. Unlike the 70 and 0 industry standards, designers may overdrive the oscillator of the SP0 in both the inverting and the Voltage Doubling Mode. V LOSSC x ESR C x OAD where V LOSSC is the voltage drop due to the charge pump capacitor, C, ESR C is the ESR of C, and OAD is the load current. The loss in C is larger than the loss in the reservoir capacitor, C2, because it handles a current almost four times larger than the load current during chargepump operation. As a result of this, a change in the capacitor ESR has a much greater impact on the performance of the SP0 for C than for C2.. Reservoir Capacitor ESR: V LOSSC2 = ESR C2 x OAD where V LOSSC2 is the voltage drop due to the reservoir capacitor C2, ESR C2 is the ESR of C2, and OAD is the load current. Increasing the capacitance of C2 and/or reducing its ESR can reduce the output ripple that may be caused by the charge pump. A designer can filter high-frequency noise at the output by implementing a low ESR capacitor at C2. Generally, capacitors with larger capacitance values and higher voltage ratings tend to reduce ESR.

15 Optimizing Capacitor Selection Refer to Figure 2 for the total output resistance for various capacitance values and oscillator frequencies. The reservoir and charge pump capacitor values are equal. The capacitance values required to maintain comparable ripple and output resistance typically diminish proportionately as the pump frequency of the SP0 increases. The test conditions for the curves of Figure 2 are the same as for Figures 2 to 20 for the circuits in Figures and 2; additional conditions are as follows: C = C2 = 0.2Ω ESR capacitors R =.2Ω The flat portion of the curves shown at a.2ω effective output resistance is a result of the SP0's.2Ω output resistance where.2ω = R (SP0) + ( x ESR C ) + ESR C2. Instead of the typical.2ω, R =.2Ω is used because the typical specification includes the effect of the ESRs of the capacitors used in the test circuit in Figures and 2. Refer to Figures 7,, 9 and 20 for the output currents using 0.µF to 220µF capacitors. Output currents are plotted for.0v and.v inputs taking into consideration a 0% to 20% loss in the input voltage. The SP0.2Ω series resistance limits increases in output current vs. capacitance for values much higher than 7µF. Larger values may still be useful to reduce ripple. Designing a Multiple of the SP0 Negative Inverted Output Voltage The SP0 can be cascaded to allow a designer to provide a multiple of the negative inverted output voltage of a single SP0 device. The approximate total output resistance, R TOT,of the cascaded SP0 devices is equal to the sum of the individual SP0 output resistance values, R. The output voltage, V TOT, is a multiple of the number of cascaded SP0 devices and the output voltage of an individual SP0 device, V. Refer to Figure 2 for the circuit cascading SP0 devices. Note that the capacitance value of C for the charge pump and C2 at V is multiplied respectively to the number of cascaded SP0 devices. Connecting the SP0 in Parallel SP0 devices can be connected in parallel to reduce the total output resistance. The approximate total output resistance, R TOT, of the multiple devices connected in parallel is equal to the output resistance of an individual SP0 device divided by the total number of devices connected. Refer to Figure 2 for the circuit connecting multiple SP0 devices in parallel. Note that only the charge pump capacitor value of C is multiplied respectively by the number of SP0 connected in parallel. A single capacitor C2 at the output voltage V of the "nth" device connected in parallel serves all devices connected.

16 + + + C SP0 SP0 LV C x 2 2 LV C x n SP0 n LV V C2 C2 _ 2 C2 _ n V = -n x where V = output voltage, = input voltage, and n = the total number of SP0 devices connected. Figure 2. SP0 Devices Cascaded to Provide a Multiple of a Negative Inverted Output Voltage + C SP0 C _ 2 SP0 LV 2 + LV C _ n SP0 n + LV R TOT R TOT = R n where R TOT = total resistance of the SP0 devices connected in parallel, R = the output resistance of a single SP0 device, and n = the total number of SP0 devices connected in parallel. C2 Figure 2. SP0 Devices Connected in Parallel to Reduce Output Resistance

17 C + V+ D D2 V SP0 C C LV V 2 C2 V = (2 x ) - V FD - V FD2 V 2 = - where V = positive doubled output voltage, = input voltage, V FD = forward bias voltage across D, V FD2 = forward bias voltage across D2, and V 2 = inverted output voltage. Figure 27. The SP0 Connected for Negative Voltage Conversion with Positive Supply Multiplication Circuit for Negative Voltage Conversion with Positive Supply Multiplication A designer can use the circuit in Figure 27 to provide both an inverted output voltage at V and a positive multiple of at V 2 (subtracting the forward biased voltages of D and D2). Capacitor C is for the charge pump and capacitor C2 is for the reservoir function to generate the inverted output voltage at V 2. Capacitor C is for the charge pump and capacitor C is for the reservoir function to generate the multiplied positive output voltage at V. Designers should pay special attention to the possibility of higher source impedances at the generated supplies due to the finite impedance of the common charge pump driver. 7

18 + C 0µF Tant. + C 0µF Tant. 2 DOUBLER SP0 V+ 7 LV D C2 0µF + Tant. V 2 LP29 V ON/OFF_N BYPASS + C.7µF Cer. C 0nF Cer. Figure 2. The SP0 and a LDO Regulator Connected as a V Input to Regulated V Output Converter. APPLICATIONS The SP0 Evaluation Board provides a V to V 0mA DC to DC Converter using the SP0 Doubler Circuit and a V LDO Regulator. SP0 Ripple 00 g =.2V V 0 =.V V LDO =.9V OAD = 0mA Power Efficiency y( (%) ) IL = 0mA VLDO Ripple Figure 29. Ripple and Noise output of the SP0 and a LDO Regulator with OAD = 0mA Input Voltage (V) Figure 0. Power Efficiency vs Input Voltage - SP0 Doubler with V LDO Power Efficiency (%) Vin =.0V Vin =.V Vin =.V Load Current (ma) Ripple Voltage (mv) Ripple IL = 0mA LDO Ripple IL = 0mA Input Voltage (V) Figure. Power Efficiency vs Load Current - SP0 Doubler with V LDO Figure 2. Ripple Voltage vs Input Voltage - SP0 Doubler with V LDO

19 PACKAGE: PLASTIC DUAL IN LINE (NARROW) E E D = 0.00" min. (0.27 min.) D A = 0.0" min. (0.min.) A = 0.20" max. (. max). e = 0.00 BSC (2.0 BSC) B B ALTERNATE END PINS (BOTH ENDS) L A2 Ø C e A = 0.00 BSC (7.20 BSC) DIMENSIONS (Inches) Minimum/Maximum (mm) A2 B B C D E E L Ø PIN PIN PIN 0./0.9 (2.92/.9) 0.0/0.022 (0./0.9) 0.0/0.070 (./.77) 0.00/0.0 (0.20/0.) 0./0.00 (9.07/0.0) 0.00/0.2 (7.20/.2) 0.20/0.20 (.09/7.2) 0./0.0 (2.92/.0) 0 / (0 / ) 0./0.9 (2.92/.9) 0.0/0.022 (0./0.9) 0.0/0.070 (./.77) 0.00/0.0 (0.20/0.) 0.7/ /0.00 (.9/9.) (9.2/20.20) 0.00/0.2 (7.20/.2) 0.20/0.20 (.09/7.2) 0./0.0 (2.92/.0) 0 / (0 / ) 0./0.9 (2.92/.9) 0.0/0.022 (0./0.9) 0.0/0.070 (./.77) 0.00/0.0 (0.20/0.) 0.00/0.2 (7.20/.2) 0.20/0.20 (.09/7.2) 0./0.0 (2.92/.0) 0 / (0 / ) PIN 0./0.9 (2.92/.9) 0.0/0.022 (0./0.9) 0.0/0.070 (./.77) 0.00/0.0 (0.20/0.) 0.0/0.920 (22.2/2.) 0.00/0.2 (7.20/.2) 0.20/0.20 (.09/7.2) 0./0.0 (2.92/.0) 0 / (0 / ) 20 PIN 0./0.9 (2.92/.9) 0.0/0.022 (0./0.9) 0.0/0.070 (./.77) 0.00/0.0 (0.20/0.) 0.90/.00 (2.92/2.92) 0.00/0.2 (7.20/.2) 0.20/0.20 (.09/7.2) 0./0.0 (2.92/.0) 0 / (0 / ) 22 PIN 0./0.9 (2.92/.9) 0.0/0.022 (0./0.9) 0.0/0.070 (./.77) 0.00/0.0 (0.20/0.)./. (29.0/29.7) 0.00/0.2 (7.20/.2) 0.20/0.20 (.09/7.2) 0./0.0 (2.92/.0) 0 / (0 / ) 9

20 PACKAGE: PLASTIC SMALL LINE (SOIC) (NARROW) E H D h x A Ø e B A L DIMENSIONS (Inches) Minimum/Maximum (mm) A A B D E e H h L Ø PIN 0.0/0.09 (./.7) 0.00/0.00 (0.02/ /0.09 (0./0.9) 0.9/0.97 (.0/.00) 0.0/0.7 (.02/.9) 0.00 BSC (.270 BSC) 0.22/0.2 (.0/.9) 0.00/0.020 (0.2/0.9) 0.0/0.00 (0.0/.270) 0 / (0 / ) PIN 0.0/0.09 (./.7) 0.00/0.00 (0.02/0.29) 0.0/0.020 (0.0/0.0) 0.7/0. (.2/.7) 0.0/0.7 (.02/.9) 0.00 BSC (.270 BSC) 0.22/0.2 (.0/.9) 0.00/0.020 (0.2/0.9) 0.0/0.00 (0.0/.270) 0 / (0 / ) PIN 0.0/0.09 (./.7) 0.00/0.00 (0.02/0.29) 0.0/0.020 (0.0/0.0) 0./0.9 (9.02/0.000) 0.0/0.7 (.02/.9) 0.00 BSC (.270 BSC) 0.22/0.2 (.0/.9) 0.00/0.020 (0.2/0.9) 0.0/0.00 (0.0/.270) 0 / (0 / ) 20

21 PACKAGE: PLASTIC MICRO SMALL LINE (µsoic) 0.09 ± BSC 0. ± ± ±0.00 R ± ± ± ± ± Ref.0 ± 0. ± ± ± ± ± ± ± ±0.00 All package dimensions in inches 0 µsoic devices per tube 2

22 ORDERING INFORMATION Model Temperature Range Package Type SP0CP C to +70 C... -Pin PDIP SP0EP C to + C... -Pin PDIP SP0CN C to +70 C... -Pin NSOIC SP0EN C to + C... -Pin NSOIC SP0CU C to +70 C... -Pin µsoic SP0EU C to + C... -Pin µsoic SP0EB... Evaluation Board Please consult the factory for pricing and availability on a Tape-On-Reel option. Available in lead free packaging. To order, add "-L" suffix to the part number. Example: SP0EU/TR=Tape & Reel. SP0EU-L/TR = lead free. Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 02 TEL: (97) FAX: (97) sales@sipex.com Sales Office 2 South Hillview Drive Milpitas, CA 90 TEL: (0) FAX: (0) Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. 22