FIRST ORDER SIGMA DELTA MODULATOR USING 0.25 µm CMOS TECHNOLOGY AT 2.5 V

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1 International Journal of Electronics and Communication Engineering and Technology (IJECET) Volume 7, Issue 4, July-August 2016, pp , Article ID: IJECET_07_04_002 Available online at Journal Impact Factor (2016): (Calculated by GISI) ISSN Print: and ISSN Online: IAEME Publication FIRST ORDER SIGMA DELTA MODULATOR USING 0.25 µm CMOS TECHNOLOGY AT 2.5 V Sonali Gandewar, Megha Soni and Vijay Sharma Swami Vivekanand College of Engineering, Indore, India ABSTRACT First order modulator is used in the sigma-delta modulator oversampled analog-to-digital (ADC) converter. Pseudo two phase latch based comparator with three stage cascading is used to get 2500 DC gain. Floating gate MOSFET is used at the input of integrator and comparator.adc is implemented using 0.25 µm CMOS technology at 2.5 V. Index Terms: Analog-to-Digital Converter (ADC), Inverter, Sigma-Delta, nmos, pmos Cite this Article: Sonali Gandewar, Megha Soni and Vijay Sharma, First Order Sigma Delta Modulator Using 0.25 µm CMOS Technology at 2.5 V, International Journal of Electronics and Communication Engineering and Technology, 7(4), 2016, pp INTRODUCTION Over the years analog systems were dominating but the advantages digital signals made digital system designing more popular. Signals in general are analog in nature, so it becomes important to have systems that convert analog signals to digital signals to couple with digital systems. Every ADCs have their own advantages and disadvantages. Oversampled ADCs (sigma-delta) provides wide band frequency range from DC to several MHz with maximum accuracy [5]. Sigma delta ADC consists of oversampled modulator which is followed by decimation filter. Direct conversion of analog signal to digital signal is not possible. Figure 1 shows the general block diagram of a ADC which consist of prefilter, sample and hold, quantizer and encoder [6] 13 editor@iaeme.com

2 Sonali Gandewar, Megha Soni and Vijay Sharma Figure 1 Block diagram of a ADC with fundamental blocks Prefilter avoid the aliasing of high frequency signal, sample and hold circuit samples the circuit converts the continues signal to discrete continues signal hold circuit quantize the magnitude, during this period signal is converteded to equivalent digital code. 2. ARCHITECTUREE OF SIGMA DELTA ADC Architecture of sigma delta modulator ADC is shown in figure 2. The modulator convert analog signal to 1 bit pulse density stream. This ADC is oversampled ADC which operates at higher frequency f s >> f N. Figure 2 Block diagram of sigma delta modulator [7] Difference of input signal and the output of 1-bit digital to analog converter is applied to the integrator. Integrator output is given to comparator which gives digital single bit digital output. In first order sigma delta modulator analog input range is nearly equal to the DAC reference signal and the average value of digital output should be equal to the v in. The density of vdout is an inherently monotonic function of v in, the linearity of this ADC is independent of component matching. 3. VOLTAGE REFERENCE Variation in supply voltage and temperature are important factor for the circuit performance so it important to design a reference circuit. A band gap reference circuit is shown in the figure editor@iaeme.com

3 First Order Sigma Delta Modulator Using 0.25 µm CMOS Technology at 2.5 V Figure 3 Direct band gap voltage reference circuit Upper half of the circuit uses pmos and lower half uses nmos both works opposite to each other. Its response is shown in the figure reference v(l) v(m) v(h) Voltage (V) VVdd (V) Figure 4 Response of direct band gap voltage reference It has three reference levels V L = 0.52 V, V M = 1.25V and V H = 2 V. 4. LOW POWER LATCH Low power latch circuit is shown in the figure 5 which is used as dynamic memory with single φ -clock. The circuit uses few device switching due to which power reduces editor@iaeme.com

4 Sonali Gandewar, Megha Soni and Vijay Sharma Figure 5 Schematic of low power latch Power can further be reduced by sizing of MOS transistor. The transistor used in this schematic uses 0.25 µ m. Proper matching between pmos and nmos provides mid voltage transition. 5. DESIGN OF COMPARATOR The comparator is based on digital buffer which consumes low power and inverter is used at the output stage for the gain. Schematic of comparator is shown in the figure 6. Figure 6 Schematic of comparator The comparator uses three reference voltages reference v(in) v(out) v(l) v(m) v(h) Voltage (V) VVin (V) Figure 7 Comparator DC transfer characteristics with its reference voltages 16 editor@iaeme.com

5 First Order Sigma Delta Modulator Using 0.25 µm CMOS Technology at 2.5 V V L = 0.52 V, V M = 1.25V and V H = 2. External bias is required for the starved current inverters which is shown in figure 1 which provides low current bias to the V comparator stages, it also pulls the switching point towards by forcing equivalent current on pull-up and pull down stages. It reduces the comparator offset and improves the integration in the sigma delta modulator. 6. FIRST ORDER SELF REFERENCED DELTA SIGMA MODULATOR First order self-referenced delta sigma modulator is shown in the figure 8. The reference signal, MED is also switching point of the first stage of the comparator, thus the output of the integrator needs no further scaling. DD 2 Figure 8 First order self-referenced delta-sigma modulator with test setup This design uses less components and minimum switches which reduces the power of the ADC. The comparator stages are starved current inverters matched to the current in the reference circuit. The switches on the comparator pass the analog signals that are close to both power rails reference v(vin) v(in_pulse) Voltage (V) Time (us) Figure 9 Digital output of first order sigma delta modulator for the sinusoidal input signal Figure 9 shows the digital output of first order sigma delta modulator. Figure 10 shows the Spectral power density of the output editor@iaeme.com

6 Sonali Gandewar, Megha Soni and Vijay Sharma db (Relative to W rms ) reference - FFT p(vvdd) Frequency (MHz) Figure 10 Power spectral density of the output point FFT 7. PERFORMANCE SUMMARY Technology 0.25 µ m Supply Voltage 2.5 V Comparator DC gain 2500 Power Consumption Sampling frequency 0.57 mw 5 MHz 8. CONCLUSION Inverter based comparator with proper scaling can reduce the power consumption. Higher order sigma delta modulator can further improve the performance. The main advantage of this architecture is its minimum component use and the switches that reduces the power. Inverter based comparator gives simplicity in construction, and avoids the complexity and clock handling. REFRENCES [1] Lukas Dorrer, Franz Kuttner, 10-bit 3mW Continuous time sigma Delta ADC for UMTS in a 0.12 µ m CMOS process, IEEE 2003, pp [2] Luis Hernandez Corporales, A 1.2 MHz 10 bit Continuous time sigma delta ADC using a time encoding quantizer, IEEE transactions on circuits and systems-ii: Express briefs, 56(1), January 2009, pp [3] Enrique Prefasi, A 0.1 mm, Wide Bandwidth Continuous Time ADC Based on a Time Encoding Quantizer in 0.13 µ m CMOS, IEEE Journal of Solid State Circuits, 44(10) October [4] Youngcheol Chae, Gunhee Han, Low voltage, low power, Inverter based Switch capacitor delta sigma modulator, IEEE Journal of solid state circuits, 44(2), February [5] editor@iaeme.com

7 First Order Sigma Delta Modulator Using 0.25 µm CMOS Technology at 2.5 V [6] Shafqat Ali, A Novel 1V,24uW, Modulator using amplifier & Comparator Based Switched Capacitor Technique, With 10 KHz Bandwidth and 64dB SNDR, IEEE 2010, pp [7] Bindu Patluri, Sigma Delta Modulator For Biomedical Applications With Reduced Nonidealities, Journal of Intelligent Electronic Systems, 2(1), July [8] Dattaprasad Madur, Dr. Deepak Bhoir and Swapnali Makdey, Three Dimensional Integration of CMOS Inverter, International Journal of Electronics and Communication Engineering and Technology, 5(11), 2014, pp [9] P.Sreenivasulu, Krishnna Veni, Dr. K.Srinivasa Rao, Dr.A.Vinayababu, Low Power Design Techniques of CMOS Digital Circuits, International Journal of Electronics and Communication Engineering and Technology, 3(2), 2012, pp [10] Prashant S. Patel, Mehul L. Patel, Implementation of CMOS 3.8 Ghz Narrow Band Pass (High Q) Switched Capacitor Filter In 180 Nm Technology, International Journal of Electronics and Communication Engineering and Technology, 4(1), 2013, pp [11] Iqbal A. Khan and Ahmed M. Nahhas, Reconfigurable Floating Impedance Using Single Digitally Programmable CMOS DVCC, International Journal of Electronics and Communication Engineering and Technology, 4(2), 2013, pp [12] Matthew Z. Straayer, Michael H. Perrot, A 12 Bit, 10 MHz Bandwidth, Continuous Time ADC With A 5 Bit,950-MS/s VCO based Quantizer, IEEE Journal of Solid State Circuits, 43(4), April editor@iaeme.com