EMTP-RV user group meeting, Dubrovnik. HVDC models in EMTP-RV

Transcription

1 EMTPRV user group meeting, Dubrovnik HVDC models in EMTPRV Sébastien Dennetière, EDF R&D, April 30th 009

2 Presentation layout Why do we develop HVDC models? Description of a detailed HVDC model in EMTPRV Simulation results Description of an average HVDCVSC model in EMTPRV Simulation results Next developments April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

3 Why do we develop HVDC models? Growing interest in HVDC links in transmission system Avoid overhead lines construction Flexibility HVDC links models are required : Determination of the best HVDC solution in a specific case Training of power system engineers 4 Models : Detailed models for transient studies: generic & specific Average models for system studies : generic & specific 3 April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

4 Detailed HVDC model Main characteristics : Generic standard HVDC (Bipolar pulses) Rated power : 00 MVA DC voltage : / 500 kv DC cable 400 mm², 70 km AC Filters : th, 5 th, 3 rd /5 th ; DC Filters : 6 th & th Reactive power compensation : filters capacitor bank Smoothing reactor : 370 mh AC Short Circuit Power : 6000 MVA Control system : Current controller on rectifier side Gamma controller or current controller on rectifier side Developed by : University of Ontario Institute of Technology, Ecole Polytechnique de Montreal and EDF R&D 4 April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

5 #R_3#,#L_3#,#C_3# #R_4p# #R_#,#L_#,#C_# #L_4p# _capa_bank 3 _HP Detailed HVDC model AC network : SCP = 6000 MVA R.5 400kVRMSLL /_50?v L 85mH AC filters: Each filter and capacitor bank generate ¼ of reactive power consumed by converters Filters parameters are calculated from analytical expressions included into scripts ligne #C_4p# Capacitor bank #C_bank# harmonic th harmonic 3th HP filter 5 April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

6 Detailed HVDC model Converters transformers : Sn = 300 MVA / transformer ratio_rec_y YY B6P_ 6pulse bridge 3phase Tap changer 368/05.45 gamma_min_star_bd firing_rec_star Xlf =.5% Converters : ratio_rec_d YgD_ 368/05.45 gamma_min_delta_bd B6P_3 6pulse bridge 3phase pulses firing_rec_delta RC snubbers ratio_rec_d YgD_ Rectifier B6P_4 6pulse bridge 3phase 368/05.45 gamma_min_delta_minus_bd firing_rec_delta ratio_rec_y YY9 368/05.45 gamma_min_star_minus_bd B6P_5 6pulse bridge 3phase firing_rec_star 6 April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

7 Detailed HVDC model DC Cables : Paper insulated / 500 kv, 400 mm² CP model s : RLC branches ( 6 th et th ) Smoothing reactance : 370 mh RL4 0.39,370mH cable_plus 500 kv 400 mm² Cu RL3 0.39,370mH 600 Hz 300 Hz 600 Hz 300 Hz 7 April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

8 Detailed HVDC model Rectifier / inverter control system firing_rec_star Regulation gamma_min_delta_bd gamma_min_star_bd gamma_min_delta_minus_bd gamma_min_star_minus_bd id_rec iref dp sp dn sn idc io Rectifier_inverter_control out iref iref DEV7 a g VKSood b g c g3 delay g4 width g5 blocking g6 single firing of 6pulse bridge v_pri_rec_a 5.3e6 v_pri_rec_b 5.3e6 v_pri_rec_c 3PH AC Line 5.3e6 voltages at Rectifier Synchronization v_rec_c v_rec_b v_rec_a v_pri_a v_pri_b v_pri_c delta_freq DEV6 V_sync_a V_sync_b V_sync_c V.K.Sood DQO_PLL_50Hz v_pri_a v_pri_b v_pri_c delta_freq DEV9 V_sync_a V_sync_b V_sync_c V.K.Sood DQO_PLL_50Hz Fm f(u) 3 Fm f(u) 3 Fm8 f(u) Fm9 f(u) Fm0 f(u) f(u) Star/Delta transformation Pulse generators DEV a g VKSood b g c g3 delay g4 width g5 blocking g6 single firing of 6pulse bridge firing_rec_delta Pulse generation DEV0 v_pri_a v_pri_b v_pri_c delta_freq V_sync_a V_sync_b V_sync_c V.K.Sood DQO_PLL_50Hz Fm3 f(u) 3 Synchronising System C c 365 c C0 tap_changer_rec v v ratio_y ratio_d ratio_rec_y ratio_rec_d Transformer tap changer 8 April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

9 Detailed HVDC model Rectifier control system Initialization sg0 idc from page step Step Initialisation amplitude pu width 4000ms time shift 00 ms Div 000 Current Scaling f(s) iref iref PI current controller Gain5 80 sg9 Ramp Initialisation amplitude pu width 50 ms time shift 50 ms sg3 ramp step SUM Current order to be sent to inverter (page 3) via telecoms step_change_io sum 0. lim8. err_idrec Gain7 0 Gain rc rv 0.8 Int4!h Kp=.65 Ki=.75 sum3!h deg_pu_delay lim7 0.8 deg_pu_delay_lim 0 alpha_delay in seconds divide by 0 elec. degs Alpha rectifier limits: alpha_min=5 degs =0.078 alpha_max=45 degs=0.8 Step change in Iorder amplitude 0. pu width 00 ms time shift 50 ms Step change in Iorder iref Iref 9 April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

10 Detailed HVDC model Inverter control system dp sp dn sn sg4 step MIN Step Gamma test amplitude 0.05 width 300 ms time shift 400 ms Step change in Gamma order idc io idc 3 4 Fm5 C c 0.0 Gamma ref V = 80 degs 0. = 8 degs Div3 000 current scaling!h gamma_step sum8 f(s)!h sum4 f(s) sum6!h 0.05 gamma_ref!h 0. lim6 lim sum3!h sum!h gamma_min Io_inv Users may select at the inverter either. Inverter Gamma control, or. Inverter Current control. This is normally biased off with the current margin setting Gain rc rv Int sum5 0!h!h lim4 Gain5 0. Kp=0.75 Ki=35.0 Kp=4.0 Ki=.0 inv gamma inv current 0.95 Gain rc rv Int3 sum 4!h!h lim Gain3.8 PI Gamma controller inv_gamma_controller MIN_SELECT MIN Gain 80 Alpha inverter limits: alphamininv =0 degs = 0.6 pu alphamaxinv =70 degs = pu!h inv_current_controller alpha_inv_degs beta_delay in seconds divide by 0 electrical degs Div 0 Step Io test at rec amplitude 0. pu width 70 ms time shift 470 ms 0 sg6 C9 c 0. step margin 0. pu simulates telecoms delay for margin setting PI current controller April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

11 Detailed HVDC model EMTPRV design v(t) v_pri_rec_a v_pri_rec_b v_pri_rec_c V_pri_rec_a vd_rec_filtered f(s) vd_rec_filtered V_pri_inv_a v(t) v_pri_inv_a p3 v_pri_inv_b v_pri_inv_c 400 kv AC system vd_inv VM vd_rec id_rec?v ratio_rec_y vd_rec id_rec ratio_inv_y B6P_ B6P_ L YY v(t) i(t) 6pulse bridge RL4 cable_plus _AC_rec RL3 p YY R 500 kv 6pulse bridge L 400 mm² Cu _AC_inv.5 3phase 85mH 0.39,370mH 0.39,370mH 3phase 85mH 400kVRMSLL /_50 368/05.45 gamma_min_star_bd?v gamma_min_star 40/ kv AC system R.5 400kVRMSLL /_0 _pole_rec firing_rec_star 600 Hz 300 Hz 600 Hz 300 Hz firing_inv_star _pole_inv ratio_rec_d Rectifier AC Filters AC filters harmonics, 3, 4 and Capacitor bank filters_rec Filters sizing _filter_rec YgD_ 368/05.45 ratio_rec_d YgD_ gamma_min_delta_bd firing_rec_delta B6P_3 6pulse bridge 3phase Rectifier B6P_4 6pulse bridge 3phase Pole B6P_6 6pulse bridge 3phase B6P_7 6pulse bridge 3phase gamma_min_delta firing_inv_delta ratio_inv_d YgD_3 40/ M R ratio_inv_d YgD_4 _filter_inv AC filters harmonics, 3, 4 and Capacitor bank filters_inv Inverter AC Filters _pole_rec 368/05.45 ratio_rec_y gamma_min_delta_minus_bd firing_rec_delta Pole gamma_min_delta_minus 0M 40/05.45 firing_inv_delta R9 ratio_inv_y _pole_inv Filters sizing Rectifier AC system YY9 368/05.45 gamma_min_star_minus_bd firing_rec_star B6P_5 6pulse bridge 3phase RL 0.39,370mH 600 Hz 300 Hz cable_minus 500 kv 400 mm² Cu 600 Hz 300 Hz RL 0.39,370mH B6P_8 6pulse bridge 3phase gamma_min_star_minus firing_inv_star YY4 40/05.45 Inverter AC system April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

12 y y Detailed HVDC model Simulation results PLOT PLOT time (s) time (s) Step change in Iorder Step change in Gamma order Simulation options : Δt = 5µs, t max = s, CPU time = 30s April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

13 y y y y Detailed HVDC model Voltage sag AC voltage rectifier side PLOT AC voltage inverter side PLOT time (s) time (s) DC Current PLOT DC Voltage PLOT time (s) time (s) 3 April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

14 Detailed HVDC model, next developments Available on demand Implementation of the Voltage Dependent Current Limit Unit : Static characteristic adapts I ref as a function of DC voltage Dynamic characteristic adapts I ref as a function of DC voltage according to the fast down time and slow up time Modeling of protection systems (overvoltage, overcurrent, commutation failures) Implementation of start up algorithm Integration of control systems designed by manufacturers (DLL connection) to obtain specific HVDC models 4 April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

15 Average HVDC VSC model Main Characteristics : Rated power : 00 MVA DC voltage : / 30 kv DC cable 500 mm² XLPE insulation, 70 km Converters transformers AC & s Capacitor bank : 0 µf AC short circuit power : 6000 MVA Control system : Active power regulation DC voltage regulation Reactive power regulation Developed by EDF R&D 5 April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

16 Q_mes P_mes P_mes Q_mes Average HVDC VSC model LF TD AC_network YY 400/450 GND GND DC link HVDC_VSC_Link YY 400/450 GND GND AC_network LF TD F fault 3phase fault during 00 ms Loadflow Initialization Loadflow Initialization Q_mes P_mes P_mes Q_mes k_hvdc Q P P Q m_hvdc powermeter V V_mag phase_ V_mag phase_ V_mag V_mag powermeter XLPE_cable_ Idc_mes ci 0.50/00 Vdc_mes V 60uF!v CP E0 60uF!v V Vdc_mes ci 0.50/00 Idc_mes 60uF!v E0 CP 60uF!v XLPE_cable_ 6 April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

17 y y Average HVDC VSC model PLOT PLOT time (s) Active power step change time (s) DC voltage step change Simulation options : Δt = 50µs, t max = 3s, CPU time = 4.s 7 April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière

18 HVDC VSC model Next developments Reactive power controller has to be improved Contribution to CIGRE WG B4.38 (Simulation of HVDC and FACTS) Implementation of manufacturer controllers models using DLL connection to obtain specific HVDC models Available on demand 8 April 8th 009, EMTPRV UGM Dubrovnik, Sébastien Dennetière