ULTRA- DESCRIPTION APE8990. switch. maximum. channel per channel. control signals. resistor for outpu. switch is turned time is adjustable on the

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1 ULTRA- LOW ON RESISTANCE, 6-A DUAL LOAD SWITCH WITH CONTROLLED TURN-ON FEATURES Integrated dual channel load switch Input Voltage Range: 0.8V to 5.5V Ultra-low ON-Resistance, R ON = 20mΩ per channel 6A Maximum Continuous Current per channel Low Threshold Control Input Adjustable Rise Time Quick Output Discharge Transistor Over-Temperature Protection RoHS Compliant and Halogen Free Product APPLICATIONS Telecom Systems Industrial Systems Set-Top-Box Consumer Electronics Notebooks / Netbooks DESCRIPTION The is a small, ultra-low R ON dual load switch with controlled turn on. It contains two N-channel MOSFETs that can operate over an input voltage range of 0.8V to 5.5V and support maximum continuous current up to 6A each. Each load switch is controlled by an on/off input (ON), which is capable of interfacing directly with low-voltage control signals. Additional features include a 150Ω on-chip load resistor for outpu quick discharge when switch is turned off, in order to avoid inrush current, the rise time is adjustable by an external ceramicc capacitor on the CTx pin. The is available in an ultra-small, space saving 3mmx2mmm 14-pin DFN package with thermal pad. TYPICAL APPLICATION +5V ON1 VBIAS V IN1 VIN1 VOUT1 V OUT1 C IN1 R L1 C OUT1 ON2 VOUT2 V OUT2 CT1 CT2 GND R L2 C OUT2 C IN2 CT1 CT2 Data and specifications subject to change without notice V1.0 0

2 ORDERING / PACKAGE INFORMATION X-HF Top View DFN 3x2-14L Halogen Free Product Package Type GN3B: DFN 3x2-14L VIN1 VIN1 ON1 VBIAS Exposed Pad 11 VOUT1 VOUT1 CT1 GND ON CT2 6 7 GND 9 8 VOUT2 VOUT2 ABSOLUTE MAXIMUM RATINGS VIN1, VOUT1, VOUT2 VON1, VON2 VBIAS I MAX Storage Temperature Range (T ST ) Junction Temperature ( T J ) Lead Temperature (Soldering, 10sec.) Thermal Resistance from Junction to Ambient (Rθ JA ) DFN-14L (3mmX2mm) S (at T A =25 C) -0.3V to 6V VIN+ +0.3V -0.3V to 6V V 6A -65 to +150 C 150 C 260 C 65 C/W RECOMMENDEDD OPERATING CONDITIONS VIN1,2 VBIAS VON1,2 VOUT1,2 CIN1,2 Operating Temperaturee Range 0.8V to 5.5V 4.75V to 5.5V 0V to 5.5V VIN1,2 4. 7uF -40 C to 85 C 2

3 ELECTRICAL SPECIFICATIONS (VIN1, 2=0. 8 to 5.5V, VBIAS=5V, T A =25 C, unless otherwisee specified) PARAMETERR SYM TEST CONDITION MIN TYP MAX UNIT Quiescent Current I BIAS VIN1==VON1=VON2=5V IOUT1=IOUT2=0A ua Shutdown Current I SD VON1=VON2=GND, VOUT1=VOUT2= =0 1 ua ON Resistance (each sw witch) (Note1) R ON VONx=VBIAS=5V, IOUTx=1A mω Output Pull Down Resistance R ON VBIAS=5V, VONx=0V Ω ONx Input Leakage Current I ON VONx=5V or GND 1 ua ONx Logic High V IH Switch on 1.0 V ONx Logic Low V IL Switch off 0.5 V Thermal Shutdown Threshold T SD 150 C (Note1) T HYS Hysteresis 30 C Note1: Guarantee by design, not production tested. 3

4 PIN DESCRIPTIONS PIN No. 1, 2 3 PIN SYMBOL VIN1 ON1 PIN DESCRIPTION Channel 1 input, bypass this input with a ceramicc capacitor to ground. Channel 1 enable control input, active high. Do not leave floating. 4 VBIAS 5V bias voltage. 5 6,7 8, ,14 ON2 VOUT2 CT2 GND CT1 VOUT1 Channel 2 enable control input, active high. Do not leave floating. Channel 2 input, bypass this input with a ceramicc capacitor to ground. Channel 2 output. A capacitor to ground set the rise time of VOUT2. Ground. A capacitor to ground set the rise time of VOUT1. Channel 1 output. BLOCK DIAGRAM VIN1 VBIAS Oscillator VOUT1 Charge Pump Thermal Protection Control Logic Output1 Discharge ON1 VOUT2 ON2 Output2 Discharge GND CT1 CT2 4

5 TYPICAL PERFORMANCE CHARACTERISTICS VBIAS=5V, Io=0A, C IN =1µF, C OUT =0.1µF, ch1:on1, ch2:vout1, ch3:on2, ch4:vout2 Fig. 1 Turn-on Response, VIN=0.8V Fig.2 Turn-on Response, VIN= 1.2V Fig. 3 Turn-on Response, VIN=1.5V Fig.4 Turn-on Response, VIN= 1.8V Fig.5 Turn-on Response, VIN=3.3V Fig.6 Turn-on Response, VIN= 5.0V 5

6 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) VBIAS=5V, Io=0A, C IN =1µF, C OUT =0.1µF, ch1:on1, ch2:vout1, ch3:on2, ch4:vout2 Fig. 7 Turn-off Response, VIN=0.8V Fig.8 Turn-off Response, VIN= 1.2V Fig.9 Turn-off Response, VIN=1.5V Fig.10 Turn-off Response, VIN= =1.8V Fig.11 Turn-off Response, VIN=3.3V Fig.12 Turn-off Response, VIN= =5.0V 6

7 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) Turn-on Delay Time (us) Turn-off Delay Time (us) I BIAS (ua) CT=1nF CT=0.47nF 170 CT=0.22nF VBIAB=5V, Cout= =0.1uF, Io=0A VIN (V) Fig.13 t D-ON vs. VIN 1.0 CT=1nF 0.9 CT=0.47nF 0.8 CT=0.22nF VBIAB=5V, Cout= =0.1uF, Io=0A VIN (V) Fig.15 t D-OFF vs. VIN VBIAS=5V 0 VOUT Rise Time (us) VOUT Fall Time (us) V ON (V) CT=1nF CT=0.47nF CT=0.22nF VBIAB= =5V, Cout=0.1uF, Io=0A VIN (V) Fig.14 t R vs. VIN VBIAB= =5V, Cout=0.1uF, Io=0A VIN (V) Fig.16 t F vs. VIN VON-H 0.1 VON-L T J ( C) T J ( C) Fig.17 Quiescent Current vs. Temperature Fig.18 ON Threshold vs. Temperature 7

8 APPLICATION INFORMATION On/Off Control The load switch is controlled by the ON pin. The ONx pin is active highh and has a low threshold making it capable of interfacing with low voltage signals. The ONx pin can be used with standard 1.2V, 1.8V, 2.5V or 3.3V GPIO logic threshold. Do not leave the ONx pin float. The Figure19 show the VOUTx turn-on/off t R : VOUT rise time waveform. t D-ON : VOUT turn on delay t D-OFF : VOUT turn off delay t F : VOUT fall time ON 90% 90% VOUT 10% 10% t D-ON t R t D-OFF t F Fig19 ON/OFF Waveform Output Rise Time Control The rise time of each VOUTx is adjustable by an external capacitor on the CTx pin. The rise time shows on below Table 1 are typical measured value. Please refer it for determined rise time. CT (nf) Rise Time, t R (µs),10%~90%, C OUT =0. 1µF,C IN =1uF VIN=0.8V VIN=1.05V VIN=1.2V VIN=1.5V VIN=1.8V VIN=2.5V VIN=3.3V VIN=5V <Table 1> 8

9 APPLICATION INFORMATION (Continued) Input Capacitor An input capacitor is recommended to be placed between VINx and GND to limit the voltage drop on the input supply during high current application. Output Capacitor Setting a C IN greater than the C OUT is highly recommended. Since the internal body diode is in the NMOS switch, this prevents the current flows through the body diode from VOUTx to VINx when the system supply is removed. Layout Considerationss The Figure 20 shows the reference layout for. Below lists help start layout. 1. The current loop of two load switch should be separated and symmetrized to each other. 2. Keep the high current paths (VIN, VOUT and GND; blue circle) wide and short to obtain the best effect. 3. The input and outpu capacitors should be close to the device as possible to minimize the parasitic trace inductances. 4. Place the thermal vias under the exposed pad of the device (green circle). This help for thermal diffusion away from the device. Fig20 Reference Layout 9

10 MARKING INFORMATION DFN 3x2-14L 8990 YWWS Part Number Date Code (YWWS) Y:Year WW:Week S : Sequence 10